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4 2 8 2 ` 2 h 2 l 2 p 2 � 2 � 2 � 2 � 2 � 2 � 2 � 2 � 2 � 2 � 2 2 2 2 $ 2 ( 2 P 2 X 2 \ 2 ` 2 d 2 � 2 � 2 � 2 � 2 � 2 � 2 � 2 � 2 � 2 !2 !2 !2 !2 !2 @!2 H!2 L!2 P!2 T!2 |!2 �!2 �!2 �!2 �!2 �!2 �!2 �!2 �!2 �!2 �!2 �!2 "2 "2 "2 0"2 8"2 <"2 @"2 D"2 l"2 t"2 x"2 |"2 �"2 �"2 �"2 �"2 �"2 �"2 �"2 �"2 �"2 �"2 �"2 #2 (#2 ,#2 0#2 4#2 \#2 d#2 h#2 l#2 �#2 �#2 �#2 �#2 �#2 �#2 �#2 �#2 $2 $2 $2 $2 L$2 T$2 X$2 \$2 �$2 �$2 �$2 �$2 �$2 �$2 �$2 �$2 �$2 �$2 %2 %2 %2 %2 %2 <%2 D%2 H%2 L%2 P%2 x%2 �%2 �%2 �%2 �%2 �%2 �%2 �%2 �%2 �%2 �%2 �%2 �%2 &2 &2 ,&2 4&2 8&2 <&2 @&2 h&2 p&2 t&2 x&2 �&2 �&2 �&2 �&2 �&2 �&2 �&2 �&2 �&2 �&2 '2 $'2 ('2 ,'2 0'2 X'2 `'2 d'2 h'2 l'2 �'2 �'2 �'2 �'2 �'2 �'2 �'2 �'2 �'2 �'2 (2 (2 (2 (2 $(2 ((2 ,(2 H(2 P(2 T(2 X(2 `(2 d(2 h(2 �(2 �(2 �(2 �(2 �(2 �(2 �(2 �(2 �(2 �(2 �(2 �(2 �(2 �(2 �(2 )2 )2 )2 )2 )2 8)2 @)2 D)2 H)2 P)2 X)2 `)2 d)2 t)2 |)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 �)2 *2 *2 (*2 0*2 4*2 8*2 @*2 H*2 d*2 l*2 p*2 t*2 |*2 �*2 �*2 �*2 �*2 �*2 �*2 �*2 �*2 �*2 �*2 �*2 �*2 �*2 �*2 �*2 +2 +2 $+2 (+2 0+2 4+2 8+2 T+2 \+2 `+2 d+2 l+2 p+2 t+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 �+2 ,2 ,2 ,2 ,2 ,2 (,2 D,2 L,2 P,2 T,2 \,2 `,2 d,2 l,2 p,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 �,2 -2 -2 -2 -2 -2 -2 4-2 <-2 @-2 D-2 H-2 L-2 T-2 p-2 x-2 |-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 �-2 .2 .2 $.2 ,.2 0.2 4.2 8.2 <.2 D.2 `.2 h.2 l.2 p.2 t.2 x.2 �.2 �.2 �.2 �.2 �.2 �.2 �.2 �.2 �.2 �.2 �.2 �.2 �.2 �.2 �.2 /2 /2 /2 $/2 (/2 ,/2 4/2 P/2 X/2 \/2 `/2 d/2 h/2 p/2 �/2 �/2 �/2 �/2 �/2 �/2 �/2 �/2 �/2 �/2 �/2 �/2 �/2 �/2 02 02 02 02 02 02 $02 @02 H02 L02 P02 T02 X02 `02 |02 �02 �02 �02 �02 �02 �02 �02 �02 �02 �02 �02 �02 �02 �02 12 12 12 12 012 812 <12 @12 H12 P12 l12 t12 x12 |12 �12 �12 �12 �12 �12 �12 �12 �12 �12 �12 �12 �12 �12 22 22 (22 ,22 022 822 @22 \22 d22 h22 l22 t22 x22 |22 �22 �22 �22 �22 �22 �22 �22 �22 �22 �22 �22 �22 �22 �22 32 32 32 32 (32 ,32 032 L32 T32 X32 \32 d32 l32 �32 �32 �32 �32 �32 �32 �32 �32 �32 �32 �32 �32 42 42 42 42 42 42 <42 D42 H42 L42 T42 \42 x42 �42 �42 �42 �42 �42 �42 �42 �42 �42 �42 �42 �42 �42 �42 �42 �42 52 52 52 52 ,52 452 852 <52 D52 H52 L52 h52 p52 t52 x52 �52 �52 �52 �52 �52 �52 �52 �52 �52 �52 �52 �52 �52 �52 �52 �52 62 62 62 62 $62 (62 ,62 462 862 <62 D62 H62 X62 `62 d62 h62 p62 t62 x62 �62 �62 �62 �62 �62 �62 �62 �62 �62 �62 �62 �62 �62 �62 72 72 72 72 $72 (72 ,72 H72 P72 T72 X72 `72 d72 h72 p72 t72 �72 �72 �72 �72 �72 �72 �72 �72 �72 �72 �72 �72 �72 �72 �72 �72 �72 82 82 82 82 82 82 882 @82 D82 H82 L82 P82 X82 t82 |82 �82 �82 �82 �82 �82 �82 �82 �82 �82 �82 �82 �82 �82 �82 �82 �82 92 92 92 (92 092 492 892 <92 @92 H92 d92 l92 p92 t92 x92 |92 �92 �92 �92 �92 �92 �92 �92 �92 �92 �92 �92 �92 �92 �92 �92 :2 :2 $:2 (:2 ,:2 0:2 8:2 T:2 \:2 `:2 d:2 h:2 l:2 t:2 �:2 �:2 �:2 �:2 �:2 �:2 �:2 �:2 �:2 �:2 �:2 �:2 �:2 �:2 ;2 ;2 ;2 ;2 ;2 ;2 (;2 D;2 L;2 P;2 T;2 X;2 \;2 d;2 �;2 �;2 �;2 �;2 �;2 �;2 �;2 �;2 �;2 �;2 �;2 �;2 �;2 �;2 �;2 <2 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�D2 �D2 �D2 �D2 �D2 �D2 �D2 �D2 �D2 �D2 �D2 E2 E2 $E2 (E2 ,E2 0E2 4E2 <E2 XE2 `E2 dE2 hE2 lE2 pE2 xE2 �E2 �E2 �E2 �E2 �E2 �E2 �E2 �E2 �E2 �E2 �E2 �E2 �E2 �E2 F2 F2 F2 F2 F2 $F2 ,F2 HF2 PF2 TF2 XF2 \F2 `F2 hF2 �F2 �F2 �F2 �F2 �F2 �F2 �F2 �F2 �F2 �F2 �F2 �F2 �F2 �F2 �F2 G2 G2 G2 G2 G2 G2 8G2 @G2 DG2 HG2 LG2 PG2 XG2 tG2 |G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 �G2 H2 H2 H2 (H2 0H2 4H2 8H2 <H2 @H2 HH2 dH2 lH2 pH2 tH2 xH2 |H2 �H2 �H2 �H2 �H2 �H2 �H2 �H2 �H2 �H2 �H2 �H2 �H2 �H2 �H2 �H2 I2 I2 $I2 (I2 ,I2 0I2 8I2 TI2 \I2 `I2 dI2 hI2 lI2 tI2 �I2 �I2 �I2 �I2 �I2 �I2 �I2 �I2 �I2 �I2 �I2 �I2 �I2 �I2 J2 J2 J2 J2 J2 J2 (J2 DJ2 LJ2 PJ2 TJ2 XJ2 \J2 dJ2 �J2 �J2 �J2 �J2 �J2 �J2 �J2 �J2 �J2 �J2 �J2 �J2 �J2 �J2 �J2 K2 K2 K2 K2 K2 K2 4K2 <K2 @K2 DK2 HK2 LK2 TK2 pK2 xK2 |K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 �K2 L2 L2 $L2 ,L2 0L2 4L2 8L2 <L2 DL2 `L2 hL2 lL2 pL2 tL2 xL2 �L2 �L2 �L2 �L2 �L2 �L2 �L2 �L2 �L2 �L2 �L2 �L2 �L2 �L2 �L2 M2 M2 M2 $M2 (M2 ,M2 4M2 PM2 XM2 \M2 `M2 dM2 hM2 pM2 �M2 �M2 �M2 �M2 �M2 �M2 �M2 �M2 �M2 �M2 �M2 �M2 �M2 �M2 N2 N2 N2 N2 N2 N2 $N2 @N2 HN2 LN2 PN2 TN2 XN2 `N2 |N2 �N2 �N2 �N2 �N2 �N2 �N2 �N2 �N2 �N2 �N2 �N2 �N2 �N2 �N2 �N2 O2 O2 O2 O2 O2 0O2 8O2 <O2 @O2 DO2 HO2 PO2 lO2 tO2 xO2 |O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 �O2 P2 P2 (P2 ,P2 0P2 4P2 8P2 @P2 \P2 dP2 hP2 lP2 pP2 tP2 |P2 �P2 �P2 �P2 �P2 �P2 �P2 �P2 �P2 �P2 �P2 �P2 �P2 �P2 �P2 Q2 Q2 Q2 Q2 $Q2 (Q2 0Q2 LQ2 TQ2 XQ2 \Q2 `Q2 dQ2 lQ2 �Q2 �Q2 �Q2 �Q2 �Q2 �Q2 �Q2 �Q2 �Q2 �Q2 �Q2 �Q2 �Q2 �Q2 R2 R2 R2 R2 R2 R2 R2 <R2 DR2 HR2 LR2 PR2 TR2 \R2 xR2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 �R2 S2 S2 S2 S2 ,S2 4S2 8S2 <S2 @S2 DS2 LS2 hS2 pS2 tS2 xS2 |S2 �S2 �S2 �S2 �S2 �S2 �S2 �S2 �S2 �S2 �S2 �S2 �S2 �S2 �S2 �S2 T2 T2 $T2 (T2 ,T2 0T2 4T2 <T2 XT2 `T2 dT2 hT2 lT2 pT2 xT2 �T2 �T2 �T2 �T2 �T2 �T2 �T2 �T2 �T2 �T2 �T2 �T2 �T2 �T2 U2 U2 U2 U2 U2 $U2 ,U2 HU2 PU2 TU2 XU2 \U2 `U2 hU2 �U2 �U2 �U2 �U2 �U2 �U2 �U2 �U2 �U2 �U2 �U2 �U2 �U2 �U2 �U2 V2 V2 V2 V2 V2 V2 8V2 @V2 DV2 HV2 LV2 PV2 XV2 tV2 |V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 �V2 W2 W2 W2 (W2 0W2 4W2 8W2 <W2 @W2 HW2 dW2 lW2 pW2 tW2 xW2 |W2 �W2 �W2 �W2 �W2 �W2 �W2 �W2 �W2 �W2 �W2 �W2 �W2 �W2 �W2 �W2 X2 X2 $X2 (X2 ,X2 0X2 8X2 TX2 \X2 `X2 dX2 hX2 lX2 tX2 �X2 �X2 �X2 �X2 �X2 �X2 �X2 �X2 �X2 �X2 �X2 �X2 �X2 �X2 Y2 Y2 Y2 Y2 Y2 Y2 (Y2 DY2 LY2 PY2 TY2 XY2 \Y2 dY2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 �Y2 Z2 Z2 Z2 Z2 Z2 Z2 4Z2 <Z2 @Z2 DZ2 HZ2 LZ2 TZ2 pZ2 xZ2 |Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 �Z2 [2 [2 $[2 ,[2 0[2 4[2 8[2 <[2 D[2 `[2 h[2 l[2 p[2 t[2 x[2 �[2 �[2 �[2 �[2 �[2 �[2 �[2 �[2 �[2 �[2 �[2 �[2 �[2 �[2 �[2 \2 \2 \2 $\2 (\2 ,\2 4\2 P\2 X\2 \\2 `\2 d\2 h\2 p\2 �\2 �\2 �\2 �\2 �\2 �\2 �\2 �\2 �\2 �\2 �\2 �\2 �\2 �\2 ]2 ]2 ]2 ]2 ]2 ]2 $]2 @]2 H]2 L]2 P]2 T]2 X]2 `]2 |]2 �]2 �]2 �]2 �]2 �]2 �]2 �]2 �]2 �]2 �]2 �]2 ^2 ^2 ^2 0^2 8^2 <^2 @^2 D^2 l^2 t^2 x^2 |^2 �^2 �^2 �^2 �^2 �^2 �^2 �^2 �^2 �^2 �^2 �^2 _2 (_2 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� � D D CPU_CLK_UNHALTED_CORE CPU_CLK_UNHALTED_REF FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE EVENT_1AH EVENT_4EH EVENT_65H EVENT_92H EVENT_A3H EVENT_DDH SOFTWARE_JAVA_BYTECODE COHERENT_LINEFILL_HITC STREX_PASSED EVENT_138H EVENT_160H EVENT_193H EVENT_198H EVENT_1CDH EVENT_1F5H EVENT_200H EVENT_208H EVENT_23AH EVENT_25FH EVENT_263H EVENT_26EH EVENT_279H EVENT_28AH EVENT_2B9H EVENT_2C4H EVENT_2CDH EVENT_305H EVENT_309H EVENT_32FH EVENT_373H EVENT_397H EVENT_3C1H EVENT_3DAH EVENT_3E9H EVENT_3FBH TTBR_WRITE_RETIRED LD_SPEC LDST_SPEC DMB_SPEC dn_rxreq_dvmop_other_filtered cxha_snptrk_occ cxla_tx_tlp_link0 cxla_avg_tx_tlp_sz_dws cxla_avg_tx_tlp_sz_ccix_msg VFPU_INSTR_WAIT_CYCLES VSCR_SAT_SET L1_DATA_PUSHES L3_STORE_HITS EXTERNAL_PUSHES PREFETCH_ENGINE_FULL MARKED_GROUP_DISPATCH GCT_EMPTY FPU_MARKED_INSTR_COMPLETED GROUP_DISPATCH_REJECT STASH_L2_HITS STASH_BUSY_3 L2_CACHE_UPDATES INSTR_LFB_WENT_HIGH_PRIORITY mask= cs ds pmu: %s
perpkg: %s
metric_group: %s
LLC_MISS_RHITM period {"type": "dropnotify"}
GenuineIntel-6-3F v20 GenuineIntel-6-4D Pipeline;Mem IpMispredict IpTB Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting L1D_Cache_Fill_BW 64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time L2HPKI_All Mem;MemoryTLB Mem;MemoryTLB_SMT CPU_Utilization CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate] INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u (cstate_core@c7\-residency@ / msr@tsc@) * 100 Transactions accessing L2 pipe This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU mem_load_uops_l3_miss_retired.remote_fwd This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load Supports address when precise (Precise event) mem_load_uops_retired.l2_hit This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement Supports address when precise (Precise event) offcore_requests.demand_data_rd This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 floating point move_elimination.simd_eliminated event=0x58,period=1000003,umask=0x2 Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path idq.mite_all_uops event=0x79,period=2000003,umask=0x10 This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions);
c. Instruction Decode Queue (IDQ) delivers four uops hle_retired.aborted_misc3 hle_retired.aborted_misc4 event=0xcd,period=20011,umask=0x1,ldlat=0x10 Unhalted core cycles when thread is in rings 1, 2, or 3 This event counts both taken and not taken speculative and retired branch instructions event=0x88,period=200003,umask=0xc1 br_inst_exec.all_direct_jmp This event counts both taken and not taken mispredicted indirect branches excluding calls and returns This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns cycle_activity.cycles_no_execute ild_stall.lcp ld_blocks.store_forward event=0x3,period=100003,umask=0x2 ld_blocks_partial.address_alias event=0xa2,period=2000003,umask=0x8 Number of uops executed on the core uops_executed.core_cycles_ge_2 uops_executed_port.port_3 llc_references.pcie_ns_partial_write PCIe read current. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox unc_h_requests.reads event=0x21,umask=0x40 event=0x4,umask=0x3 event=0x4,umask=0xC Cycles where DRAM ranks are in power down (CKE) mode. Unit: uncore_imc unc_m_power_critical_throttle_cycles unc_m_pre_count.rd uncore_pcu freq_max_os_cycles % event=0x85,period=100003,umask=0x8 page_walker_loads.dtlb_l3 Average latency of all requests to external memory (in Uncore cycles) This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020091 offcore_response.all_pf_code_rd.supplier_none.snoop_none Counts all prefetch data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0090 offcore_response.all_pf_data_rd.l3_hit.snoop_not_needed offcore_response.all_pf_data_rd.supplier_none.snoop_hit_no_fwd offcore_response.all_pf_data_rd.supplier_none.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0122 offcore_response.all_rfo.supplier_none.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0001 offcore_response.pf_l2_data_rd.any_response offcore_response.pf_l2_rfo.supplier_none.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020200 offcore_response.pf_l3_data_rd.l3_hit.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000091 offcore_response.all_pf_data_rd.l3_miss.snoop_miss offcore_response.all_pf_rfo.l3_miss.snoop_none offcore_response.corewb.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000001 offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwd offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hit_no_fwd Conditional branch instructions retired (Precise event) event=0x3c,period=100003,umask=0x1 event=0x34,umask=0x8f Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram event=0,umask=0x4 Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data. Unit: uncore_qpi l2_ld.self.demand.s_state event=0x26,period=200000,umask=0x40 l2_lines_out.self.prefetch event=0x2b,period=200000,umask=0x48 l2_m_lines_in.self l2_m_lines_out.self.prefetch l2_reject_busq.self.prefetch.e_state Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions event=0xcf,period=2000000,umask=0x0 SIMD micro-ops retired (excluding stores) (Must be precise) decode_stall.pfb_empty misalign_mem_ref.rmw_split prefetch.sw_l2 bus_data_rcv.self event=0x63,period=200000,umask=0xe0 bus_trans_pwr.self event=0x9,period=200000,umask=0x20 event=0x77,period=200000,umask=0x1 Hardware interrupts received Number of segment register loads data_tlb_misses.dtlb_miss_st Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims L2 cache request misses Loads retired that hit WCB (Precise event capable) Supports address when precise (Must be precise) Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000008 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache Counts BACLEARS on return instructions Cycles hardware interrupts are masked br_misp_retired.ind_call event=0xcd,period=2000003 Counts core cycles if either divide unit is busy event=0xc3,period=200003,umask=0x1 event=0xd0,period=200003,umask=0x13 Memory uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) mem_uops_retired.dtlb_miss_stores event=0x5,period=200003,umask=0x2 Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000003010 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000400 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache offcore_response.streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter event=0x8,period=200003,umask=0x10 Counts the number of store RFO requests that miss the L2 cache All retired store uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61, HSM63 offcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwd Number of transitions from SSE to AVX-256 when penalty applicable Spec update: HSD56, HSM57 Counts cycles the IDQ is empty Spec update: HSD135 This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance Randomly selected loads with latency value being above 4 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400091 arith.divider_uops All (macro) branch instructions retired (Must be precise) event=0xc4,period=100003,umask=0x2 Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: HSD140 (Must be precise) event=0x34,umask=0x41 unc_cbo_xsnp_response.hit_eviction Number of ITLB page walker loads that hit in the L3 Spec update: HSD25 offcore_response.demand_rfo.llc_hit.hit_other_core_no_fwd event=0x28,period=200003,umask=0x4 Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready (Precise event) All retired store uops. (Precise Event) Retired load uops that split across a cacheline boundary. (Precise Event) event=0x60,cmask=1,period=2000003,umask=0x2 Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles Offcore outstanding Demand Data Read transactions in uncore queue Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0001 number of AVX-256 Computational FP double precision uops issued this cycle number of GSSE-256 Computational FP single precision uops issued this cycle Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0 Cycles per core when uops are dispatched to port 1 Cycles per thread when load or STA uops are dispatched to port 2 unc_cbo_xsnp_response.hitm unc_cbo_xsnp_response.xcore_filter LLC lookup request that access cache and found line in E-state. Unit: uncore_cbox Filter on processor core initiated cacheable read requests. Unit: uncore_cbox event=0x8,period=100003,umask=0x88 event=0x8,period=100003,umask=0x82 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c03f7 Counts all prefetch (that bring data to L2) code reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20010 event=0xb,edge=1 This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state Retired load uops with locked access (Precise event) Loads with latency value being above 4 (Must be precise) event=0x89,period=200003,umask=0x90 ld_blocks_partial.all_sta_block partial_rat_stalls.flags_merge_uop_cycles Uops dispatched per thread event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010044 Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800183091 Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.any_read.l2_hit_near_tile offcore_response.any_rfo.l2_hit_near_tile offcore_response.bus_locks.l2_hit_near_tile event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080400 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000400 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000004 offcore_response.partial_reads.l2_hit_near_tile event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180080 offcore_response.partial_writes.l2_hit_near_tile Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.pf_l1_data_rd.l2_hit_near_tile_e_f Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.pf_l2_code_rd.outstanding Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080203091 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x01010032f7 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000022 offcore_response.pf_l1_data_rd.ddr_near Counts the number of core cycles when no micro-ops are allocated and the ROB is full Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS) unc_m_cas_count.wr event=0x4,period=200003,umask=0x8 l1d_cache_ld.e_state l1d_cache_lock_fb_hit L1 writebacks to L2 in E state event=0xf2,period=100000,umask=0x2 l2_rqsts.ld_hit mem_inst_retired.latency_above_threshold_256 Memory instructions retired above 4 clocks (Precise Event) event=0xb,period=2000,umask=0x10,ldlat=0x40 event=0xb,period=2000000,umask=0x1 Instructions retired which contains a store (Precise Event) mem_uncore_retired.remote_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x10FF Offcore RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3808 offcore_response.data_ifetch.io_csr_mmio event=0xb7,period=100000,umask=0x1,offcore_rsp=0x133 Offcore demand data requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3804 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3802 offcore_response.other.llc_hit_no_other_core offcore_response.other.remote_cache offcore_response.pf_data_rd.llc_hit_other_core_hitm Offcore prefetch data reads satisfied by a remote cache Offcore prefetch RFO requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF70 All offcore prefetch requests offcore_response.prefetch.remote_cache_hitm event=0xcc,period=2000000,umask=0x2 simd_int_64.packed_logical event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4077 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4002 offcore_response.other.any_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2080 Offcore prefetch data requests satisfied by the local DRAM load_dispatch.any Branch prediction unit missed call or return event=0x88,period=200000,umask=0x2 Indirect non call branches executed br_inst_exec.taken event=0x1e,period=2000000,umask=0x1 Retired MMX instructions (Precise Event) Load operations conflicting with software prefetches MXCSR rename stall cycles event=0xd1,cmask=1,inv=1,period=2000000,umask=0x1 event=0xb1,period=2000000,umask=0x40 event=0x8,period=200000,umask=0x2 mem_store_retired.dtlb_miss event=0x24,period=200003,umask=0xd8 mem_inst_retired.split_stores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C0004 offcore_response.demand_code_rd.l3_hit_s.snoop_miss offcore_response.demand_code_rd.l3_hit_s.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0040001 offcore_response.demand_data_rd.l3_hit_m.snoop_hitm offcore_response.demand_rfo.l3_hit_m.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040002 offcore_response.demand_rfo.l3_hit_s.snoop_hit_no_fwd offcore_response.demand_rfo.l4_hit_local_l4.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40020002 offcore_response.other.l3_hit_m.any_snoop Counts the number of cache line split locks sent to the uncore Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event) Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity icache_64b.iftag_stall Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer Spec update: SKL089 event=0x60,period=2000003,umask=0x10 offcore_response.demand_rfo.l3_miss_local_dram.snoop_hitm offcore_response.demand_rfo.l3_miss_local_dram.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C408000 exe_activity.4_ports_util Cycles total of 4 uops are executed on all ports and Reservation Station was not empty Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2 Total pipeline cost of branch related instructions (used for program control-flow including function calls) Number of Instructions per non-speculative DSB miss Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) This event counts the number of load ops retired that miss in the L2 (Precise event) Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000008 offcore_response.pf_l2_code_rd.l2_miss.hit_other_core_no_fwd event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000020 Counts the number of mispredicted JCC branch instructions retired (Precise event) mem_load_uops_misc_retired.llc_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0240 Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_l2_rfo.llc_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0020 Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400240 offcore_response.data_in_socket.llc_miss_local.any_llc_hit event=0xb0,period=100000,umask=0x1 REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x10ff event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5077 REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_DATA and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f70 offcore_response.any_data.any_dram_and_remote_fwd offcore_response.demand_data_rd.any_dram_and_remote_fwd event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3004 offcore_response.demand_ifetch.other_local_dram REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD offcore_response.pf_data_rd.any_dram_and_remote_fwd event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3070 event=0xb3,cmask=1,period=2000000,umask=0x1 offcore_requests.uncached_mem Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd Counts all demand & prefetch RFOs that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0004 offcore_response.pf_l2_data_rd.l3_hit.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs that have any response type event=0xc7,period=2000003,umask=0x80 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00490 Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram offcore_response.demand_code_rd.l3_miss.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000010 offcore_response.pf_l2_rfo.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00100 CORE_POWER.LVL2_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) IO_Read_BW unc_cha_clockticks Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha event=0x50,umask=0x03 uncore_iio PCI Express bandwidth reading at IIO, part 2. Unit: uncore_iio PCI Express bandwidth writing at IIO. Unit: uncore_iio event=0x5f,umask=0x01 unc_iio_comp_buf_occupancy.cmpd.part1 Read request for 4 bytes made by the CPU to IIO Part3. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x04 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part1 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x02 Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part1 Counts when messages were sent direct to core (bypassing the CHA) unc_m2m_direct2upi_taken Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to S (Shared) unc_m2m_txc_bl_inserts.all BL Egress (to CMS) Allocations; All. Unit: uncore_m2m BL Egress (to CMS) Allocations; All unc_upi_txl_flits.data ocr.all_data_rd.l3_hit_e.snoop_none OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE ocr.all_data_rd.l3_hit_s.hitm_other_core OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE ocr.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE ocr.all_pf_rfo.l3_hit_s.snoop_miss ocr.all_reads.l3_hit_e.hit_other_core_no_fwd OCR.ALL_READS.L3_HIT_E.SNOOP_MISS ocr.all_reads.l3_hit_m.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8001007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080122 ocr.all_rfo.l3_hit_e.hit_other_core_no_fwd ocr.all_rfo.l3_hit_e.no_snoop_needed ocr.all_rfo.l3_hit_f.snoop_miss OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE ocr.demand_code_rd.l3_hit_e.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200004 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0001 ocr.demand_data_rd.l3_hit_e.hit_other_core_fwd ocr.demand_data_rd.l3_hit_s.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200002 ocr.other.l3_hit_e.any_snoop ocr.other.l3_hit_f.hit_other_core_no_fwd ocr.other.l3_hit_s.snoop_none ocr.pf_l1d_and_sw.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0400 ocr.pf_l2_data_rd.l3_hit.any_snoop ocr.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200010 ocr.pf_l2_data_rd.l3_hit_m.hitm_other_core ocr.pf_l2_rfo.l3_hit.hit_other_core_fwd ocr.pf_l2_rfo.l3_hit_f.any_snoop ocr.pf_l3_data_rd.l3_hit_e.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_e.no_snoop_needed offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_fwd offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107F7 offcore_response.all_reads.pmm_hit_local_pmm.snoop_not_needed offcore_response.all_rfo.l3_hit_e.any_snoop offcore_response.all_rfo.l3_hit_s.snoop_none offcore_response.all_rfo.pmm_hit_local_pmm.snoop_not_needed This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020004 offcore_response.demand_code_rd.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP offcore_response.demand_rfo.l3_hit_f.snoop_none offcore_response.demand_rfo.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020400 offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020080 offcore_response.pf_l3_rfo.l3_hit_f.snoop_miss offcore_response.pf_l3_rfo.l3_hit_s.no_snoop_needed 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) MEM_PMM_Read_Latency OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_miss.snoop_miss ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000120 ocr.all_pf_rfo.l3_miss_local_dram.any_snoop ocr.all_pf_rfo.l3_miss_local_dram.no_snoop_needed ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C0007F7 OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4100007F7 ocr.all_rfo.l3_miss.no_snoop_needed OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C008000 Counts any other requests OCR.OTHER.L3_MISS.SNOOP_NONE ocr.other.l3_miss_local_dram.no_snoop_needed Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000400 ocr.pf_l1d_and_sw.l3_miss.snoop_none Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000010 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss ocr.pf_l2_rfo.l3_miss.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000080 ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000100 offcore_response.all_pf_data_rd.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.pf_l1d_and_sw.l3_miss.no_snoop_needed offcore_response.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core ocr.all_data_rd.supplier_none.snoop_miss OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.demand_code_rd.any_response ocr.demand_code_rd.pmm_hit_local_pmm.snoop_none Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS event=0xe0,umask=0x1 event=0xd3,umask=0x4 Read requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m event=0x2c,umask=0x02 Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) Counts retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C2380 event=0x60,period=1000003,umask=0x1 Counts the number of PREFETCHW instructions executed idq.mite_cycles_any ocr.demand_code_rd.l3_miss ocr.hwpf_l2_data_rd.dram ocr.hwpf_l2_data_rd.local_dram Counts streaming stores that have any type of response Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events event=0xa6,cmask=2,period=1000003,umask=0x40 event=0xd,period=1000003,umask=0x10 Counts the retirement slots used each cycle Page walks completed due to a demand data store to a 2M/4M page Actual Average Latency for L1 data-cache miss demand loads (in core cycles) CacheMisses This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD Supports address when precise (Precise event) ocr.demand_data_rd.remote_cache.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F003C0477 C1 residency percent per core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC08000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000800 Hit snoop reply with data, line kept in Shared state Hit snoop reply without sending the data, line kept in Shared state Counts demand data reads that were supplied by PMM ocr.demand_rfo.snc_pmm ocr.reads_to_core.dram DRAM Precharge commands. : Precharge due to write. Unit: uncore_imc event=0x4,umask=0x3f event=0x45,umask=0x01 unc_m_dram_refresh.panic Remote write requests sent to the CHA's home agent. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref event=0x35,umask=0xC887FE01 unc_iio_data_req_of_cpu.cmpd.part1 event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x80 unc_iio_data_req_by_cpu.mem_write.part5 unc_iio_txn_req_by_cpu.mem_write.part4 unc_iio_txn_req_by_cpu.mem_read.part5 unc_iio_comp_buf_inserts.cmpd.part5 PCIe Completion Buffer Occupancy of completions with data : Part 5. Unit: uncore_iio unc_i_faf_full Clockticks of the mesh to UPI (M3UPI). Unit: uncore_m3upi TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory. Unit: uncore_cha Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition Counts the number of cycles a core is stalled due to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM) event=0x34,period=200003,umask=0x4 event=0x34,period=200003,umask=0x40 event=0xd1,period=200003,umask=0x4 Counts the number of memory uops retired that were splits Supports address when precise (Precise event) Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed ocr.uc_rd.l3_hit.snoop_miss Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache ocr.prefetches.l3_miss Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10044 ocr.corewb_m.any_response Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM event=0x74,period=1000003,umask=0x20 Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls unc_cha_tor_inserts.ia_miss_drd_opt event=0x36,umask=0xC827FF01 TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB Number of Instructions per non-speculative Branch Misprediction (JEClear). Unit: cpu_core Number of Instructions per non-speculative DSB miss. Unit: cpu_core TOPDOWN_BE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE) Cycles Per Instruction. Unit: cpu_atom Load_Splits FPDiv_Uop_Ratio Estimated Pause cost. In percent. Unit: cpu_atom event=0x4,period=20003,umask=0x2 mem_uops_retired.store_latency event=0x25,period=100003,umask=0x1f Demand Data Read miss L2, no rejects. Unit: cpu_core For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1. Unit: cpu_core TBD (Precise event). Unit: cpu_core Cycles where a code fetch is stalled due to L1 instruction cache miss. Unit: cpu_core memory_activity.stalls_l3_miss xq.full_cycles Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event). Unit: cpu_atom event=0xc3,period=20003,umask=0x6f Counts the number of uops that are from complex flows issued by the micro-sequencer (MS) (Precise event). Unit: cpu_atom event=0xb0,cmask=1,period=1000003,umask=0x8 All mispredicted branch instructions retired (Precise event). Unit: cpu_core This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event). Unit: cpu_core TMA slots where no uops were being issued due to lack of back-end resources. Unit: cpu_core event=0xae,period=2000003,umask=0x1 Incoming VC0 read request. Unit: uncore_imc Counts all L2 requests.[This event is alias to L2_REQUEST.ALL] event=0xb7,period=2000003,umask=0x2 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FFC0002 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket cpu_clk_unhalted.c02 event=0x3,umask=0x0000000002 IRP Clockticks. Unit: uncore_irp unc_iio_data_req_of_cpu.peer_write.part6 event=0x50,umask=0x0000000001 unc_upi_txl_flits.slot0 event=0x30,umask=0x0000000001 event=0x30,umask=0x0000000002 RxQ Occupancy - All Packets : Slot 1. Unit: uncore_upi RxQ Occupancy - All Packets : Slot 2. Unit: uncore_upi event=0xc0,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000001 Data requested by the CPU : Core writing to Cards MMIO space. Unit: uncore_iio event=0x1a,umask=0x07 event=0x56,umask=0x000000000a TOR Inserts : All Snoops from Remote. Unit: uncore_cha TOR Inserts; CRd Pref from local IA. Unit: uncore_cha event=0x36,umask=0x00c001fd01 TOR Occupancy : PRQ - IOSF. Unit: uncore_cha event=0x36,umask=0x00c897ff01 event=0x35,umask=0x00C8978601 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0x00c8970601 TOR Occupancy : ItoMs issued by iA Cores that Missed LLC. Unit: uncore_cha event=0x36,umask=0x00c86f8a01 unc_cha_tor_occupancy.io_wbmtoi TOR Occupancy : CLFlushes issued by IO Devices. Unit: uncore_cha IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core l2_request_g1.all_no_prefetch Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2 event=0xcb,umask=0x02 Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0 event=0x1c7,umask=0x38 Total number multi-pipe uOps assigned to pipe 1 Total number of fp uOps on pipe 2 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 Double precision divide/square root FLOPS Single-precision add/subtract FLOPS ls_tablewalker.dc_type0 all_tlbs_flushed event=0x94,umask=0xff bp_l1_tlb_fetch_hit.if1g x87 bottom-executing uOps retired. The number of serializing Ops retired Number of retired CPUID instructions event=0x43,umask=0x04 ex_ret_uncond_brnch_instr ls_any_fills_from_sys.alternate_memories event=0x44,umask=0x80 Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stream (fetch additional sequential lines into L1 cache) L3 cache requests for all coherent accesses. Unit: amd_l3 event=0xac,umask=0x08 ex_no_retire.load_not_complete ex_ret_ucode_ops Write data beats (64 bytes) for local processor at Coherent Station (CS) 2 Write data beats (64 bytes) for local processor at Coherent Station (CS) 10 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3 local_socket_inf0_inbound_data_beats_ccm2 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 2 event=0x4de,umask=0x7ff Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 5 event=0x59f,umask=0x7ff Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 3 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 7 event=0x45f,umask=0xbfe Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 1 local_socket_outbound_data_beats_link0 fp_ops_retired_by_width.mmx_uops_retired event=0x8,umask=0x10 fp_ops_retired_by_type.scalar_mac event=0xa,umask=0x04 fp_ops_retired_by_type.scalar_cmp event=0xb,umask=0x10 sse_avx_ops_retired.sse_avx_mov Retired 128-bit packed floating-point add ops event=0xc,umask=0x06 event=0xc,umask=0x0b Retired 256-bit packed floating-point divide ops event=0xc,umask=0xd0 packed_int_op_type.int256_sub Retired 256-bit packed integer pack ops event=0xd,umask=0xe0 Retired packed integer ops of all types Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages resyncs_or_nc_redirects event=0xaa,umask=0x04 Number of ops dispatched to the floating-point unit frontend_bound_latency Fraction of dispatched ops that were flushed due to branch mispredicts l2_cache_accesses_from_l1_ic_misses L1 data TLB misses Remote socket upstream DMA write data d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk) uncore_imc.cache_hits NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED PMNC_SW_INCR EVENT_05H EVENT_25H EVENT_52H EVENT_6FH EVENT_72H EVENT_81H EVENT_AFH EVENT_C9H EVENT_D8H EVENT_DAH CHAIN LD_RETIRED EVENT_106H EVENT_121H EVENT_123H EVENT_144H EVENT_15BH EVENT_1DBH EVENT_20DH EVENT_211H EVENT_21CH EVENT_22AH EVENT_252H EVENT_258H EVENT_274H EVENT_299H EVENT_2E7H EVENT_2F8H EVENT_300H EVENT_311H EVENT_35CH EVENT_361H EVENT_362H EVENT_365H EVENT_384H L1D_CACHE_REFILL_LD L1D_TLB_WR hnf_mc_reqs hnf_pocq_atomic_addrhaz rni_rxdat_flits rni_txdat_flits rni_rdb_ord cxra_snp_bcasts cxra_req_chains clkdiv2_ranks_in_sref CYCLES_THREE_INSTR_DISPATCHED BRANCHES_COMPLETED L1_DATA_SNOOP_HIT_ON_MODIFIED VTQ_LINE_FETCH_HIT FP_STORE_CAUSES_STALL_IN_LSU LSU_CSQ_FORWARDING L1_DATA_LOAD_ACCESS_MISS L1_DATA_CACHE_CASTOUTS_TO_L2 FPR_ISSUE_STALLED FPR_ISSUE_QUEUE_ENTRIES L3_DATA_CACHE_MISSES PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH MARKED_INSTR_FINISH_ANY_UNIT CYCLES_ISSUE_STALLED GUARDED_LOADS_TRANSLATED LOAD_MISS_DLFB_FULL LOAD_GUARDED_MISS ILFB_FETCH_MISS_CYCLES hs cancelled IAF STANDALONE event: %s
LLC-REFERENCE GenuineIntel-6-36 GenuineIntel-6-A7 This category represents fraction of slots where the processor's Frontend undersupplies its Backend INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD Cycles Per Instruction (per Logical Processor) FLOPc_SMT INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES SMT Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate) L1MPKI Power L1D miss oustandings duration in cycles l2_rqsts.all_demand_references l2_rqsts.rfo_miss This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Supports address when precise. Spec update: BDM100 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) offcore_requests.all_data_rd event=0xb0,period=100003,umask=0x8 offcore_requests_buffer.sq_full Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction event=0xc7,period=2000003,umask=0x8 other_assists.avx_to_sse Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches Cycles MITE is delivering 4 Uops event=0x79,cmask=1,period=2000003,umask=0x8 This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy Number of times the TSX watchdog signaled an HLE abort Number of times an HLE execution aborted due to incompatible memory type Number of times HLE caused a fault mem_trans_retired.load_latency_gt_16 Loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) misalign_mem_ref.loads Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts) Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort event=0x5d,period=2000003,umask=0x10 event=0x54,period=2000003,umask=0x8 Taken speculative and retired direct near calls This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired (Precise event) All mispredicted macro branch instructions retired br_misp_retired.near_taken Count XClk pulses when this thread is unhalted and the other thread is halted This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4 Cycles with no micro-ops executed from any thread on physical core Cycles where at least 2 uops were executed per-thread Cycles per core when uops are exectuted in port 4 This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) uncore_cbox event=0x35,umask=0x3,filter_opc=0x187,filter_nc=1 PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox event=0x35,umask=0x1,filter_opc=0x18d event=0x1,umask=0x1 event=0x1,umask=0x8 Shared line forwarded from remote cache. Unit: uncore_ha power_critical_throttle_cycles % unc_p_power_state_occupancy.cores_c3 event=0x74 (UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100. Store miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 Number of ITLB page walker hits in the L2 Spec update: BDM69, BDM98 DTLB flush attempts of the thread-specific entries MEM_Parallel_Requests All retired load uops Supports address when precise (Precise event) All retired store uops Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020091 offcore_response.all_pf_code_rd.l3_hit.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0120 offcore_response.demand_code_rd.l3_hit.snoop_miss offcore_response.demand_data_rd.l3_hit.any_snoop offcore_response.demand_rfo.l3_hit.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020010 offcore_response.pf_l2_data_rd.supplier_none.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0020 offcore_response.pf_l2_rfo.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0080 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0120 offcore_response.corewb.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_not_needed offcore_response.demand_rfo.l3_miss_local_dram.any_snoop offcore_response.other.l3_miss.snoop_none offcore_response.pf_l2_code_rd.l3_hit.snoop_non_dram offcore_response.pf_l2_code_rd.l3_miss.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000040 offcore_response.pf_l2_code_rd.supplier_none.snoop_non_dram offcore_response.pf_l2_rfo.l3_miss.snoop_miss offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_non_dram offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_none This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight (Precise event) A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core unc_arb_trk_occupancy.all event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0244 offcore_response.demand_rfo.llc_miss.remote_hitm unc_q_clockticks All data requests from the L1 data cache l2_data_rqsts.self.i_state l2_ld.self.demand.mesi event=0x30,period=200000,umask=0x4f event=0xcb,period=10000,umask=0x2 simd_uop_type_exec.mul.ar event=0xb3,period=2000000,umask=0x81 event=0xb3,period=2000000,umask=0x8 BACLEARS asserted macro_insts.non_cisc_decoded Nonzero segbase load 1 bubble misalign_mem_ref.ld_split.ar Memory references that cross an 8-byte boundary misalign_mem_ref.st_split.ar bus_bnr_drv.this_agent bus_hitm_drv.this_agent bus_request_outstanding.all_agents cycles_int_masked.cycles_int_masked event=0x7e,period=200000,umask=0x40 br_inst_retired.mispred event=0xc4,period=2000000,umask=0x4 Retired taken branch instructions event=0x89,period=200000,umask=0x2 Mispredicted return branches mul.ar reissue.any Number of page-walks executed event=0x51,period=200003,umask=0x1 Counts load uops retired that hit the L1 data cache Supports address when precise (Must be precise) Counts load uops retired that miss the L1 data cache Supports address when precise (Must be precise) offcore_response.any_data_rd.l2_hit event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000003010 Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module offcore_response.corewb.l2_miss.any event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040004 Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_needed event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400002000 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache machine_clears.fp_assist Floating point divide uops retired. (Precise Event Capable) (Must be precise) event=0xe7,period=200003,umask=0x1 event=0xcb,period=203,umask=0x1 event=0xc4,period=200003,umask=0x7e br_inst_retired.non_return_ind Reference cycles when core is not halted. This event uses a programmable general purpose performance counter Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010020 Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Page walk completed due to a demand data store to a 2M or 4M page event=0x4f,period=200003,umask=0x10 Retired load uops with locked access Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) Number of SIMD move elimination candidate uops that were not eliminated Counts cycles MITE is delivered at least one uop. Set Cmask = 1 Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles offcore_response.all_code_rd.l3_miss.any_response offcore_response.all_data_rd.l3_miss.local_dram offcore_response.demand_rfo.l3_miss.local_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00020 Number of times an RTM execution successfully committed Mispredicted macro branch instructions retired (Must be precise) Execution stalls due to L1 data cache misses Resource-related stall cycles Spec update: HSD135 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x063F800091 event=0xf2,period=100003,umask=0x8 Requests from the L2 hardware prefetchers that miss L2 cache RFOs that access cache lines in any state L2 or LLC HW prefetches that access L2 cache Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations Sample stores and collect precise store operation via PEBS record. PMC3 only (Must be precise) page_walks.llc_miss Cycles with pending L2 miss loads. Set AnyThread to count per core int_misc.recovery_stalls_count event=0xd,cmask=1,edge=1,period=2000003,umask=0x3 Cycles weighted by number of requests pending in Coherency Tracker. Unit: uncore_arb Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC. Unit: uncore_arb A snoop hits a non-modified line in some processor core Filter on processor core initiated cacheable write requests Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests. Unit: uncore_cbox Data forwarded from remote cache mem_load_uops_llc_miss_retired.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0080 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20091 Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode.data_read. Unit: uncore_cbox LLC misses for ItoM writes (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.miss_opcode.itom_write. Unit: uncore_cbox Read requests to home agent. Unit: uncore_ha Number of data flits transmitted . Unit: uncore_qpi event=0xe unc_p_freq_ge_1200mhz_transitions event=0xc,edge=1,filter_band1=20 This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier Miss in last-level (L3) cache. Excludes Unknown data-source Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization hw_pre_req.dl1_miss This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180044 Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_read.l2_hit_this_tile_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800408000 Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.demand_code_rd.l2_hit_far_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180004 offcore_response.demand_code_rd.l2_hit_this_tile_m Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000080 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000080 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800182000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400040 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state offcore_response.pf_software.l2_hit_this_tile_m Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180200 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080200 Counts any request that accounts for data responses from DRAM Far offcore_response.bus_locks.ddr_near offcore_response.demand_code_rd.ddr_near Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800040 Counts the total number of instructions retired Counts the number of micro-ops retired This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress Counts the total I-side page walks that are completed Counts the total page walks that are completed (I-side and D-side) l2_lines_in.s_state L2 lines evicted by a prefetch request event=0x27,period=100000,umask=0x1 l2_write.rfo.m_state event=0xcb,period=40000,umask=0x4 offcore_response.any_data.llc_hit_no_other_core offcore_response.any_data.local_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1811 Offcore requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x822 offcore_response.corewb.any_cache_dram Offcore code or data read requests satisfied by the LLC and not found in a sibling core offcore_response.demand_data_rd.llc_hit_other_core_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x801 Offcore demand code reads satisfied by the IO, CSR, MMIO unit offcore_response.demand_ifetch.local_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x704 Offcore demand code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x280 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F40 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x470 SSE FP packed Uops simd_int_128.packed_mpy 128 bit SIMD integer shift operations 128 bit SIMD integer unpack operations offcore_response.any_rfo.local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6080 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2030 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6070 event=0x4,period=200000,umask=0x7 event=0x14,cmask=1,edge=1,inv=1,period=2000000,umask=0x1 bpu_clears.early event=0x88,period=200000,umask=0x7f br_inst_exec.direct Indirect call branches executed event=0x87,period=2000000,umask=0x4 Length Change Prefix stall cycles event=0xd2,period=2000000,umask=0x2 Scoreboard stall cycles Resource related stall cycles Store buffer stall cycles uops_executed.core_active_cycles_no_port5 event=0xc2,cmask=16,inv=1,period=2000000,umask=0x1 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40040004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40020004 offcore_response.demand_data_rd.l3_hit_e.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0100002 offcore_response.demand_rfo.supplier_none.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400028000 event=0xc6,period=100007,umask=0x1,frontend=0x12 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event) Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000400001 event=0xd,period=2000003,umask=0x80 Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end event=0xb1,period=2000003,umask=0x10 100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) Loads hit L2 (Precise event) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000008008 Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache This event counts all instruction fetches from the instruction cache Counts the number of cycles when no uops are allocated for any reason Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) (Precise event) All retired store uops. (Precise Event - PEBS) (Precise event) offcore_response.all_pf_code_rd.llc_hit.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0240 REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l2_code_rd.llc_hit.snoop_miss REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE Counts all prefetch code reads that miss the LLC and the data returned from dram Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram offcore_response.demand_ifetch.llc_miss_local.dram Counts demand data writes (RFOs) that miss the LLC and the data returned from dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400080 offcore_requests_outstanding.demand.read_data REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.any_request.all_local_dram_and_remote_cache_hit REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5003 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5001 REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff70 offcore_response.data_ifetch.any_dram_and_remote_fwd REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM offcore_response.other.other_local_dram Snoop data requests dtlb_load_misses.walk_cycles ITLB miss large page walks event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2704 mem_load_l3_miss_retired.local_dram mem_load_l3_miss_retired.remote_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0490 OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram offcore_response.all_pf_data_rd.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00490 Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000122 offcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache offcore_response.pf_l3_data_rd.l3_miss.any_snoop offcore_response.pf_l3_data_rd.l3_miss.remote_hit_forward offcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) L2_Evictions_NonSilent_PKI Power_License1_Utilization_SMT Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode event=0x81 unc_iio_data_req_of_cpu.mem_read.part1 PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0. Unit: uncore_iio event=0x54,umask=0x01 Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*) Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA unc_cha_imc_writes_count.full event=0x37,umask=0x02 Ingress (from CMS) Allocations; IRQ. Unit: uncore_cha Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_data_req_by_cpu.peer_write.part1 unc_iio_data_req_of_cpu.peer_read.part0 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x08 Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_read.part1 Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU. Unit: uncore_iio Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x02 Number of reads that a message sent direct2 Intel UPI was overridden. Unit: uncore_m2m event=0x2d,umask=0x2 Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads unc_upi_rxl_bypassed.slot2 unc_upi_txl_flits.non_data Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches. Precise event Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080491 OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080490 OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP ocr.all_pf_data_rd.l3_hit_m.any_snoop ocr.all_pf_data_rd.l3_hit_s.snoop_miss OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP ocr.all_pf_rfo.l3_hit.no_snoop_needed ocr.all_pf_rfo.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200120 ocr.all_pf_rfo.l3_hit_s.snoop_none ocr.all_reads.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C07F7 ocr.all_reads.l3_hit.snoop_miss ocr.all_reads.l3_hit_e.no_snoop_needed ocr.all_rfo.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080122 ocr.all_rfo.l3_hit_f.no_snoop_needed ocr.demand_code_rd.l3_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200004 ocr.demand_data_rd.l3_hit_e.hit_other_core_no_fwd ocr.demand_data_rd.l3_hit_f.no_snoop_needed ocr.demand_rfo.l3_hit_m.hit_other_core_no_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE ocr.other.l3_hit.hit_other_core_fwd ocr.other.l3_hit_e.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800088000 Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD ocr.other.l3_hit_m.snoop_miss ocr.other.l3_hit_s.hit_other_core_no_fwd ocr.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd ocr.pf_l1d_and_sw.l3_hit.snoop_miss Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit_f.any_snoop Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE ocr.pf_l2_data_rd.l3_hit_f.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080020 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100020 ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit.snoop_none ocr.pf_l3_rfo.l3_hit_f.snoop_miss Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.all_data_rd.l3_hit_m.hit_other_core_fwd offcore_response.all_data_rd.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP offcore_response.all_pf_data_rd.l3_hit_s.hitm_other_core offcore_response.all_pf_data_rd.supplier_none.hitm_other_core offcore_response.all_pf_data_rd.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE offcore_response.all_reads.l3_hit.any_snoop offcore_response.all_reads.l3_hit.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP offcore_response.all_reads.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit_e.snoop_miss offcore_response.all_rfo.l3_hit_e.snoop_none offcore_response.all_rfo.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS offcore_response.all_rfo.l3_hit_s.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.demand_rfo.l3_hit_f.hit_other_core_no_fwd offcore_response.other.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020400 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd offcore_response.pf_l3_data_rd.l3_hit_m.snoop_miss offcore_response.pf_l3_data_rd.l3_hit_s.hitm_other_core offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400100 clx metrics 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) ) Average 3DXP Memory Bandwidth Use for Writes [GB / sec] event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000491 OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.all_reads.l3_miss_remote_hop1_dram.snoop_miss ocr.all_rfo.l3_miss.snoop_none OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.demand_code_rd.l3_miss.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000004 ocr.demand_code_rd.l3_miss_local_dram.any_snoop ocr.demand_code_rd.l3_miss_local_dram.hitm_other_core Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM ocr.other.l3_miss_local_dram.any_snoop Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.pf_l1d_and_sw.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000400 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000010 ocr.pf_l3_data_rd.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000100 offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.demand_data_rd.l3_miss.hit_other_core_no_fwd offcore_response.demand_rfo.l3_miss.hitm_other_core offcore_response.other.l3_miss.remote_hit_forward This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.pf_l2_rfo.l3_miss_local_dram.hitm_other_core offcore_response.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.all_pf_rfo.supplier_none.hit_other_core_no_fwd OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED ocr.demand_code_rd.supplier_none.any_snoop ocr.demand_code_rd.supplier_none.hit_other_core_no_fwd ocr.other.any_response ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed Intel Optane DC persistent memory bandwidth read (MB/sec). Unit: uncore_imc Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory. Unit: uncore_imc Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all. Unit: uncore_imc Retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0004 ocr.demand_data_rd.l3_hit.snoop_not_needed ocr.hwpf_l2_rfo.l3_hit.any event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0020 Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled 100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS) 100 * (( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD) + (10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED Number of times an RTM execution aborted All mispredicted branch instructions retired (Precise event) event=0xa3,cmask=20,period=1000003,umask=0x14 Number of uops executed on port 5 uops_dispatched.port_6 uops_dispatched.port_7_8 Uops that RAT issues to RS uops_retired.slots Page walks completed due to a demand data load to a 2M/4M page Page walks completed due to a demand data load to a 4K page Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address ocr.prefetches.l3_hit 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / cha_0@event\=0x0@ event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400004 Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally Counts demand data reads that were supplied by PMM attached to another socket ocr.demand_rfo.local_pmm Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket unc_cha_llc_victims.all unc_cha_tor_inserts.ia_hit TOR Inserts : All requests from IO Devices. Unit: uncore_cha event=0x35,umask=0xC8177E01 event=0x35,umask=0xC8C7FF01 event=0x35,umask=0xCC57FF01 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC. Unit: uncore_cha event=0x35,umask=0xC8178A01 event=0x35,umask=0xc867fe01 TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC. Unit: uncore_cha Number Transactions requested of the CPU : Card writing to DRAM. Unit: uncore_iio event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x01 unc_iio_data_req_of_cpu.cmpd.part7 event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x04 unc_m2m_cms_clockticks TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis Counts the number of retired split store uops Supports address when precise (Precise event) ocr.all_code_rd.l3_hit Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0010 Counts the number of misaligned store uops that are 4K page splits (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000010 Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM ocr.hwpf_l2_code_rd.local_dram Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response btclear.any Counts the total number of consumed retirement slots (Precise event) TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC. Unit: uncore_cha TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 PCIe Completion Buffer Occupancy : Part 0-7 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault Counts the number of Extended Page Directory Entry hits event=0x4f,period=2000003,umask=0x8 Counts the number Extended Page Directory Pointer Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches cycles / CPU_CLK_UNHALTED.REF_TSC Fill Buffer (FB) true hits per kilo instructions for retired demand loads. Unit: cpu_core Fraction of cycles where both hardware Logical Processors were active. Unit: cpu_core Counts the number of load ops retired that hit in the L2 cache Supports address when precise (Precise event). Unit: cpu_atom event=0xd0,period=1000003,umask=0x6 Retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event). Unit: cpu_core Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. Unit: cpu_atom DSB-to-MITE switch true penalty cycles. Unit: cpu_core Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x602006 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00002 This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS (Precise event). Unit: cpu_atom ld_blocks.address_alias Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls). Unit: cpu_atom Total execution stalls. Unit: cpu_core int_vec_retired.vnni_256 unc_m_vc1_requests_rd Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM. Unit: uncore_imc Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS] All L2 requests.[This event is alias to L2_REQUEST.ALL] event=0xd3,period=1000003,umask=0x2 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808000004 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1030004477 event=0xcf,period=100003,umask=0x10 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C000002 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F33004477 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket event=0x5,umask=0x00000000cf event=0xe0,umask=0x0000000001 Precharge due to read, write, underfill, or PGT. Unit: uncore_imc DRAM Precharge commands. : Prechages from Page Table. Unit: uncore_imc Number Transactions requested of the CPU : Card writing to another Card (same or different stack). Unit: uncore_iio event=0x35,umask=0x00c816fe01 TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha All Null Flits. Unit: uncore_upi unc_upi_rxl_flits.llctrl Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode. Unit: uncore_upi Matches on Receive path of a UPI Port : Non-Coherent Standard. Unit: uncore_upi Direct packet attempts : D2C. Unit: uncore_upi event=0x32,umask=0x0000000001 event=0xc0,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000001 event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000080 event=0x21,umask=0x0304 unc_m2m_prefcam_demand_drops.ch1_xpt event=0x34,umask=0x00001c19ff TOR Inserts; RFO misses from local IA. Unit: uncore_cha TOR Inserts : All from Local iA and IO. Unit: uncore_cha TOR Inserts : Match the Opcode in b[29:19] of the extended umask field. Unit: uncore_cha TOR Occupancy : All. Unit: uncore_cha event=0x36,umask=0x0000000080 unc_cha_tor_occupancy.mmcfg unc_cha_tor_occupancy.ia_llcprefrfo TOR Occupancy; DRd from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_rfo_local TOR Inserts; LLCPrefData hits from local IA. Unit: uncore_cha event=0x36,umask=0x00cccffd01 TOR Occupancy; LLCPrefCode from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref_local_pmm TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely. Unit: uncore_cha event=0x35,umask=0x00C8678601 event=0x35,umask=0x00C86E8A01 unc_cha_tor_inserts.ia_miss_local_wcil_ddr TOR Inserts : WbMtoIs issued by IO Devices. Unit: uncore_cha unc_cha_tor_occupancy.ia_clflushopt TOR Occupancy : SpecItoMs issued by iA Cores. Unit: uncore_cha TOR Occupancy : ItoMs issued by iA Cores that Hit LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_itom event=0x36,umask=0x00c8668a01 TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC. Unit: uncore_cha event=0x8a The number of 64 byte instruction cache line fulfilled from system memory or another cache l2_request_g1.change_to_x Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types) event=0x6,umask=0x01 Retired Instructions event=0xc2 ex_tagged_ibs_ops.ibs_tagged_ops The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply Ops This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimized The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits SSE bottom-executing uOps retired ls_stlf ls_dc_accesses event=0x41,umask=0x02 event=0x46,umask=0x01 Misaligned loads Execution-Time Branch Misprediction Ratio (Non-Speculative) event=0x64,umask=0x70 Average L3 Read Miss Latency (in core clocks) sse_avx_stalls bp_l1_tlb_miss_l2_tlb_miss.if4k Retired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8 event=0x2c ls_refills_from_sys.ls_mabresp_rmt_cache event=0x43,umask=0x02 event=0x5a,umask=0x10 event=0x78 de_dis_dispatch_token_stalls0.sc_agu_dispatch_stall Instruction Cache Refills from System. The number of 64 byte instruction cache line fulfilled from system memory or another cache event=0x85,umask=0x08 event=0x28f,umask=0x03 x87 bottom-executing ops retired. The number of serializing Ops retired ls_any_fills_from_sys.mem_io_remote Any Data Cache Fills by Data Source. From CCX Cache in different Node L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Floating point register file resource stall. Applies to all FP ops that have a destination register ls_dmnd_fills_from_sys.dram_io_near Software prefetch data cache fills from local L2 cache event=0x64,umask=0xf8 Core to L2 cache requests (not including L2 prefetch) for data cache access l2_pf_miss_l2_l3.l1_stride l3_xi_sampled_latency.far_cache Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node. Unit: amd_l3 event=0xad,umask=0x04 event=0xad,umask=0x10 Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.) local_processor_read_data_beats_cs11 remote_processor_write_data_beats_cs1 event=0x21f,umask=0xbff Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2 local_socket_inf0_inbound_data_beats_ccm7 event=0x5de,umask=0x7fe event=0x55f,umask=0x7fe Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 3 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 1 event=0x59e,umask=0xbfe Retired SSE and AVX floating-point divide and square root ops event=0x5,umask=0x0f Retired x87 floating-point ops Retired SSE and AVX integer multiply-accumulate ops event=0xb,umask=0x50 Retired SSE and AVX integer MOV ops Retired 128-bit packed floating-point multiply ops event=0xc,umask=0x70 event=0xc,umask=0x90 packed_int_op_type.int128_clm umc_cas_cmd.rd bp_l1_tlb_miss_l2_tlb_miss.all de_op_queue_empty PipelineL1 bad_speculation d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots) L2 cache accesses from L1 data cache misses (including prefetch) l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all DRAM write data for local processor event=0xe0,umask=0x00 UNC_CBO_HYPHEN Total read hits Total cache misses. Unit: uncore_imc_free_running sys_ddr_pmu.write_cycles CPU_CYCLES WRITE_BUF_FULL EVENT_1FH EVENT_30H EVENT_43H EVENT_66H EVENT_8FH EVENT_BCH EVENT_CDH EVENT_FAH EXC_RETURN EVENT_104H EVENT_10FH EVENT_116H EVENT_117H EVENT_122H EVENT_136H EVENT_170H EVENT_173H EVENT_19CH EVENT_1ACH EVENT_20BH EVENT_227H EVENT_24BH EVENT_25AH EVENT_289H EVENT_2FDH EVENT_392H EVENT_3B0H EVENT_3BEH INST_SPEC EXC_PABORT L1D_TLB hni_rrt_wr_alloc hni_txdat_stall sbsx_cmo_req sbsx_cmo_req_trkr_occ_cnt_ovfl rnd_rdb_unord cxra_dat_pcrd_stalls_lnk2 cxla_tx_cxs_link2 L1_INSTR_CACHE_MISSES SC_INSTR_COMPLETED L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD FP_ALL_FPSCR_RENAMES_BUSY SNOOP_VALID L2_VALID_REQUEST BUS_READS_NOT_RETRIED TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB INSTR_L1_CACHE_FETCHES FPU_INPUT_DATA_STALLS fs dram-controller-interface-bypass command INTEL_COREI7 ARMV7_CORTEX_A7 ARMV8_CORTEX_A76 PMUDEBUG GenuineIntel BR_INST_RETIRED.ALL_BRANCHES UNC_ data fabric GenuineIntel-6-2D GenuineIntel-6-1A IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stage Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed) ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb ) Kernel_CPI MEM_Read_Latency (cstate_pkg@c7\-residency@ / msr@tsc@) * 100 cache This event counts the total number of L2 code requests l2_rqsts.demand_data_rd_miss Cycles when L1D is locked Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event) Supports address when precise. Spec update: BDE70 mem_load_uops_retired.l3_miss mem_uops_retired.stlb_miss_stores Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 event=0x60,period=2000003,umask=0x1 event=0xc7,period=2000003,umask=0x4 This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information event=0xab,period=2000003,umask=0x2 This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ event=0x79,period=2000003,umask=0x30 br_inst_exec.taken_direct_jump This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired (Precise event) Mispredicted indirect branches excluding calls and returns event=0xc0,period=2000003,umask=0x2 FP operations retired. X87 FP operations that have no exceptions: Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear False dependencies in MOB due to partial compare event=0xc3,period=100003,umask=0x4 Cycles per core when uops are dispatched to port 2 unc_h_requests.writes_remote (UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCKTICKS) * 100. unc_p_freq_trans_cycles event=0x85,period=100003,umask=0x1 event=0x85,period=100003,umask=0x2 Number of DTLB page walker hits in Memory Spec update: BDM69, BDM98 Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise (Precise event) This event counts load uops with locked access retired to the architected path Supports address when precise. Spec update: BDM35 (Precise event) This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) offcore_response.all_data_rd.supplier_none.snoop_none offcore_response.all_data_rd.supplier_none.snoop_not_needed offcore_response.all_pf_data_rd.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0008 offcore_response.corewb.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0040 Counts all prefetch (that bring data to LLC only) RFOs have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020100 Counts randomly selected loads with latency value being above 512 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) offcore_response.all_pf_code_rd.l3_miss.snoop_miss offcore_response.all_pf_code_rd.supplier_none.snoop_non_dram offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000002 offcore_response.other.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000020 offcore_response.pf_l3_code_rd.l3_miss.snoop_none offcore_response.pf_l3_code_rd.supplier_none.snoop_non_dram offcore_response.pf_l3_data_rd.l3_miss.snoop_miss offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss Number of times RTM abort was triggered (Precise event) Retirement slots used (Precise event) L3 Lookup read request that access cache and found line in M-state event=0x34,umask=0x88 L3 Lookup read request that access cache and found line in any MESI-state. Unit: uncore_cbox unc_arb_trk_requests.writes event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C07F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0604000091 event=0x21,period=200000,umask=0x40 l2_reject_busq.self.prefetch.s_state l2_st.self.m_state SIMD packed micro-ops retired SIMD packed micro-ops executed event=0xb3,period=2000000,umask=0x82 event=0xb3,period=2000000,umask=0x88 event=0x10,period=2000000,umask=0x82 FXCH uops retired (Must be precise) Icache hit event=0xc4,period=2000000,umask=0xf event=0xc5,period=200000,umask=0x0 Retired branch instructions that were predicted not-taken event=0x88,period=2000000,umask=0x41 event=0x89,period=200000,umask=0x8 Self-Modifying Code detected Micro-ops retired ITLB flushes event=0xd1,period=200003,umask=0x8 Memory uops retired (Precise event capable) Supports address when precise (Must be precise) Counts the number of memory uops retired that is either a loads or a store or both Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x82 Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.any_pf_data_rd.l2_miss.any Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000001 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required offcore_response.partial_streaming_stores.l2_miss.hit_other_core_no_fwd event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200002000 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) BACLEARs asserted for conditional branch fetch_stall.all Counts near CALL branch instructions retired (Must be precise) uops_retired.idiv Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch offcore_response.any_data_rd.any_response offcore_response.any_rfo.any_response Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Floating point divide uops retired (Precise Event Capable) (Must be precise) machine_clears.page_fault dtlb_load_misses.walk_completed_1gb Page walk completed due to a demand data store to a 1GB page event=0xd0,period=100003,umask=0x21 Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61, HSM63 Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61, HSM63 Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Note that a whole rep string only counts AVX_INST.ALL once Number of X87 FP assists due to input values Cycles with pending L2 miss loads. Set Cmask=2 to count cycle Spec update: HSD78, HSM63, HSM80 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions Spec update: HSD140, HSD143 This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently This events counts the cycles where at least one uop was executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 Cycles per core when uops are executed in port 1 event=0xff Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses Code miss in all TLB levels causes a page walk that completes. (2M/4M) Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB event=0xbc,period=2000003,umask=0x88 Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: HSM30 (Precise event) offcore_response.pf_llc_data_rd.llc_miss.any_response event=0xf2,period=100003,umask=0xa event=0x24,period=200003,umask=0xc0 Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts 256-bit packed single-precision floating-point instructions event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400004 Execution stalls due to L2 cache misses Number of instructions retired. General Counter - architectural event Cycles stalled due to no store buffers available (not including draining form sync) event=0xa1,period=2000003,umask=0x30 event=0x22,umask=0x04 unc_cbo_xsnp_response.external_filter event=0x34,umask=0x02 Counts load operations that missed 1st level DTLB but hit the 2nd level Misses in all ITLB levels that cause page walks event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67fc00001 PCIe non-snoop reads. Derived from unc_c_tor_inserts.opcode.pcie_read. Unit: uncore_cbox Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode.llc_data_read. Unit: uncore_cbox event=0x36,umask=0x8A event=0x10 (UNC_P_FREQ_GE_2000MHZ_CYCLES / UNC_P_CLOCKTICKS) * 100. This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded agu_bypass_cancel.count br_misp_exec.all_direct_near_call br_misp_retired.not_taken event=0x59,period=2000003,umask=0x80 resource_stalls2.all_prf_control unc_c_tor_occupancy.miss_all Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.any_pf_l2.l2_hit_near_tile offcore_response.any_read.l2_hit_this_tile_m Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180002 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010100 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000082000 offcore_response.pf_l1_data_rd.l2_hit_this_tile_m offcore_response.pf_l2_code_rd.l2_hit_far_tile event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080020 Counts Software Prefetches that accounts for any response offcore_response.pf_software.l2_hit_far_tile Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010001000 Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response offcore_response.any_request.mcdram offcore_response.bus_locks.mcdram_near Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far) Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local offcore_response.demand_rfo.ddr_near Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800080 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080201000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800200 Counts the number of near RET branch instructions retired (Precise event) br_misp_retired.rel_call Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store Supports address when precise (Precise event) This event counts the number of micro-ops retired that were supplied from MSROM Cycles L1D and L2 locked L1D snoop eviction of cache lines in M state l1d_cache_ld.mesi l1d_cache_lock.hit L1 data cache load locks in M state l1d_cache_lock.s_state event=0x28,period=100000,umask=0x8 L1 writebacks to L2 in S state event=0x26,period=200000,umask=0xf l2_data_rqsts.prefetch.e_state L2 load hits L2 prefetch hits l2_rqsts.rfos l2_transactions.fill Longest latency cache reference Memory instructions retired above 128 clocks (Precise Event) event=0xb,period=500,umask=0x10,ldlat=0x100 Memory instructions retired above 8192 clocks (Precise Event) Load instructions retired remote cache HIT data source (Precise Event) event=0xb0,period=100000,umask=0x40 offcore_response.any_ifetch.llc_hit_no_other_core Offcore code reads that HITM in a remote cache offcore_response.any_request.llc_hit_other_core_hitm Offcore RFO requests satisfied by the LLC and HITM in a sibling core offcore_response.data_ifetch.llc_hit_no_other_core offcore_response.data_in.any_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF33 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x433 Offcore demand code reads satisfied by the LLC offcore_response.pf_data.io_csr_mmio offcore_response.pf_data.llc_hit_no_other_core Offcore prefetch code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1820 MMX Uops Computational floating-point operations executed Transitions from Floating Point to MMX instructions 128 bit SIMD integer shuffle/move operations SIMD integer 64 bit shift operations event=0xd0,period=2000000,umask=0x1 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6011 Offcore demand data requests satisfied by a remote DRAM offcore_response.pf_data.remote_dram event=0x80,period=2000000,umask=0x3 All loads dispatched seg_rename_stalls Cycles no Uops issued on ports 0-4 (core count) Counts L2 cache misses when fetching instructions Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache event=0x24,period=200003,umask=0x38 event=0xd4,period=100007,umask=0x4 Retired load instructions missed L3 cache as data sources Supports address when precise (Precise event) Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200048000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100408000 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ Cycles with less than 2 uops delivered by the front-end hle_retired.aborted_unfriendly event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C400002 offcore_response.other.l3_hit_e.snoop_non_dram This event counts not taken branch instructions retired Spec update: SKL091 event=0xa6,period=2000003,umask=0x8 event=0xa6,period=2000003,umask=0x10 Counts self-modifying code (SMC) detected, which causes a machine clear Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3 1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed This event counts the total number of L2 cache references and the number of L2 cache misses respectively Cross core or cross module hitm (Precise event) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000022 Counts the number of baclears The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears FAR counts the number of far branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS) (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10433 offcore_response.pf_l2_rfo.llc_hit.hitm_other_core offcore_response.pf_l2_rfo.llc_hit.snoop_miss offcore_response.any_request.llc_miss_local.dram Cycles offcore reads busy REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x50ff event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff77 REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5050 REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3040 Cycles snoop data requests queued event=0x49,period=200000,umask=0x80 Offcore uncached memory accesses event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5833 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0004 offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd fp_arith_inst_retired.512b_packed_single event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000004 Counts all demand code reads that miss the L3 and the data is returned from local dram Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram offcore_response.pf_l2_data_rd.l3_miss.remote_hit_forward Counts all prefetch (that bring data to L2) RFOs that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00080 event=0x28,period=200003,umask=0x20 IpArith_AVX512 1000 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.THREAD MEM_DRAM_Read_Latency IO_Write_BW Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC Uncore cache clock ticks. Unit: uncore_cha Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 Multi-socket cacheline Directory state lookups; Snoop Not Needed. Unit: uncore_cha Local requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha unc_cha_rxc_occupancy.irq unc_cha_snoop_resp.rspsfwd unc_iio_comp_buf_inserts.cmpd.part0 event=0xc2,ch_mask=0x04,fc_mask=0x4,umask=0x03 Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0. Unit: uncore_iio event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x02 event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x04 event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x08 event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x01 PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh event=0x28 event=0x26 Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to S (Shared) Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to I (Invalid) Reads to iMC issued. Unit: uncore_m2m Null FLITs transmitted from any slot. Unit: uncore_upi OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200491 ocr.all_pf_data_rd.l3_hit.any_snoop OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040490 ocr.all_pf_data_rd.l3_hit_s.hitm_other_core ocr.all_pf_rfo.l3_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0120 ocr.all_pf_rfo.l3_hit_e.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C07F7 ocr.all_reads.l3_hit_f.snoop_none ocr.all_reads.l3_hit_m.no_snoop_needed ocr.all_reads.l3_hit_s.snoop_none OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED ocr.demand_code_rd.l3_hit_f.no_snoop_needed ocr.demand_code_rd.l3_hit_s.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200001 Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE ocr.demand_rfo.l3_hit_f.any_snoop ocr.demand_rfo.l3_hit_m.hitm_other_core Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP ocr.other.l3_hit.hit_other_core_no_fwd Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD ocr.other.l3_hit_f.snoop_miss ocr.pf_l1d_and_sw.l3_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080010 ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200020 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0080 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED ocr.pf_l3_rfo.l3_hit_e.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200100 offcore_response.all_data_rd.l3_hit_e.any_snoop offcore_response.all_data_rd.l3_hit_f.snoop_miss This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.all_data_rd.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE offcore_response.all_data_rd.pmm_hit_local_pmm.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020491 offcore_response.all_pf_data_rd.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.demand_data_rd.l3_hit_e.hitm_other_core offcore_response.demand_data_rd.l3_hit_e.no_snoop_needed offcore_response.demand_rfo.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE offcore_response.other.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_fwd offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE offcore_response.pf_l2_rfo.supplier_none.hitm_other_core offcore_response.pf_l2_rfo.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd offcore_response.pf_l3_data_rd.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache) Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction. Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000490 ocr.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100007F7 ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_none ocr.demand_code_rd.l3_miss.hit_other_core_no_fwd ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd ocr.demand_data_rd.l3_miss.remote_hit_forward event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000002 ocr.demand_rfo.l3_miss_local_dram.any_snoop ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core ocr.pf_l2_data_rd.l3_miss.any_snoop Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000020 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000020 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS ocr.pf_l3_rfo.l3_miss.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.all_reads.l3_miss.hit_other_core_no_fwd offcore_response.all_reads.l3_miss.remote_hitm This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE ocr.all_pf_data_rd.supplier_none.any_snoop ocr.pf_l2_rfo.pmm_hit_local_pmm.any_snoop ocr.pf_l2_rfo.supplier_none.hit_other_core_fwd Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD unc_m_pmm_bandwidth.read 6.103515625E-5MB/sec unc_m_pmm_cmd1.ufill_rd Tag Hit; Read Hit from NearMem, Dirty Line event=0xd0,period=1000003,umask=0x81 Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not ocr.demand_code_rd.l3_hit.snoop_hit_no_fwd Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not ocr.hwpf_l2_rfo.l3_hit.snoop_miss Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0800 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x520006 event=0xc6,period=100007,umask=0x1,frontend=0x504006 C8 residency percent per package C8_Pkg_Residency Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions event=0x14,cmask=1,period=1000003,umask=0x9 Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted Counts the number of times a load got blocked due to false dependencies due to partial compare on address Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector) TMA slots available for an unhalted logical processor. General counter - architectural event Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8 uops_executed.cycles_ge_1 Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle 1 / IPC BrMispredicts Branches Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities ocr.hwpf_l3.l3_hit core_snoop_response.i_fwd_fe unc_m_dram_refresh.high event=0xea,umask=0x08 unc_cha_requests.writes_remote TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC. Unit: uncore_cha event=0x35,umask=0xCC43FF04 TOR Occupancy : CRDs issued by iA Cores. Unit: uncore_cha event=0x35,umask=0xC8877E01 event=0x35,umask=0xCD43FE04 unc_cha_tor_inserts.ia_llcprefdata TOR Inserts : LLCPrefData issued by iA Cores. Unit: uncore_cha unc_iio_data_req_of_cpu.cmpd.part3 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request. Unit: uncore_iio unc_iio_txn_req_of_cpu.cmpd.part1 event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x04 unc_iio_data_req_of_cpu.mem_write.part6 unc_iio_txn_req_by_cpu.mem_read.part4 Coherent Ops : WbMtoI. Unit: uncore_irp Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0040 Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded Counts the number of requests to the instruction cache for one or more bytes of a cache line event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184008000 c0_stalls.load_l2_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400000010000 Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event) event=0x3,period=1000003,umask=0x10 Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized topdown_fe_bound.predecode Half clockticks for IMC TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_ucrdf TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 ept.epdpe_hit event=0x85,period=200003,umask=0xe Fraction of branches that are unconditional (direct or indirect) jumps. Unit: cpu_core Average per-core data fill bandwidth to the L3 cache [GB / sec]. Unit: cpu_core Unit: cpu_atom 100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS IDiv_Uop_Ratio 100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT 100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / ( MEM_BOUND_STALLS.IFETCH ) Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM). Unit: cpu_atom Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise). Unit: cpu_atom mem_uops_retired.load_latency_gt_4 Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses. Unit: cpu_atom All retired memory instructions Supports address when precise (Precise event). Unit: cpu_core event=0x21,period=100003,umask=0x1 Number of PREFETCHT0 instructions executed. Unit: cpu_core Uops delivered to Instruction Decode Queue (IDQ) from MITE path. Unit: cpu_core ld_head.any_at_ret event=0x5,period=1000003,umask=0xf4 Number of occurrences where a microcode assist is invoked by hardware. Unit: cpu_core core_power.license_1 Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready (Precise event). Unit: cpu_atom event=0xc0,period=2000003,umask=0x8 Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path. Unit: cpu_core event=0xad,period=1000003,umask=0x40,frontend=0x7 Uops executed on ports 4 and 9. Unit: cpu_core uops_retired.heavy event=0x3 event=0xd1,period=1000003,umask=0x80 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x8003C4477 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x90002380 Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) INT_MISC.MBA_STALLS Uops executed on ports 5 and 11 Number of uops dispatch to execution ports 7 and 8 Counts cycles where at least one uop has retired UOPS_RETIRED.HEAVY event=0x1,umask=0x0000000001 unc_m_pmm_rpq_occupancy.all_sch1 PMM Read Pending Queue inserts. Unit: uncore_imc event=0xe4,umask=0x03 event=0x5,umask=0x00000000c8 event=0x3,umask=0x0000000040 unc_iio_data_req_of_cpu.peer_write.part5 TOR Inserts for RdCur from local IO. Unit: uncore_cha event=0x2,umask=0x0000000008 unc_upi_rxl_flits.idle RxQ Flit Buffer Allocations : Slot 0. Unit: uncore_upi FAF - request insert from TC. Unit: uncore_irp Read request for 4 bytes made by IIO Part3 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000080 event=0x33,umask=0x0000000001 event=0x5d,umask=0x0000000005 unc_m3upi_d2u_sent unc_m3upi_d2c_sent unc_cha_llc_lookup.remote_snp TOR Inserts; RFO hits from local IO. Unit: uncore_cha TOR Inserts; RFO prefetch misses from local IA. Unit: uncore_cha event=0x35,umask=0x00cc57ff01 event=0x36,umask=0x00c807fe01 TOR Occupancy : MMCFG Access. Unit: uncore_cha TOR Occupancy : Just Remote Targets. Unit: uncore_cha event=0x36,umask=0x00c8877e01 TOR Occupancy; RdCur and FsRdCur misses from local IO. Unit: uncore_cha TOR Occupancy; RdCur and FsRdCur from local IO. Unit: uncore_cha TOR Occupancy; LLCPrefCode hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c8168601 event=0x35,umask=0x00C8968A01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_remote_ddr TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha TOR Occupancy : WCiLF issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_local_wcilf_pmm TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC. Unit: uncore_cha Dynamic Indirect Predictions bp_l1_tlb_miss_l2_miss Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty Miscellaneous events covered in more detail by l2_request_g1 (PMCx060) l2_request_g2.ls_rd_sized_nc All L2 Cache Requests (Breakdown 2 - Rare). Bus locks l2_request_g2.bus_locks_responses All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response Retired Uops The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts) Div Cycles Busy count remote_outbound_data_controller_1 remote_outbound_data_controller_3 DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0 Multiply Ops This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPS event=0x46,umask=0x08 Total Page Table Walks DC Type 0 event=0xaf,umask=0x04 Floating Point Dispatch Faults. YMM spill fault event=0x25,umask=0x04 ls_sw_pf_dc_fill.ls_mabresp_rmt_cache event=0x5a,umask=0x40 de_dis_dispatch_token_stalls1.store_queue_token_stall Decode Redirects bp_l1_tlb_miss_l2_tlb_hit event=0x44,umask=0x04 de_dis_dispatch_token_stalls2.retire_token_stall L1 Data Cache Fills: From Memory macro_ops_dispatched ls_sw_pf_dc_fills.near_cache l2_pf_hit_l2.l2_stream L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache) Instruction cache accesses of all types event=0xac,umask=0x02 Average sampled latency when data is sourced from DRAM in a different NUMA node. Unit: amd_l3 l3_xi_sampled_latency.ext_near event=0xad,umask=0x20 L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node. Unit: amd_l3 ex_no_retire.other ex_no_retire.all local_processor_write_data_beats_cs3 event=0x29f,umask=0x7ff Read data beats (64 bytes) for remote processor at Coherent Station (CS) 7 remote_processor_write_data_beats_cs11 remote_socket_upstream_read_beats_iom0 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3 event=0x81f,umask=0xbff local_socket_inf1_outbound_data_beats_ccm2 event=0x45e,umask=0xbfe remote_socket_inf0_inbound_data_beats_ccm5 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 2 fp_ops_retired_by_type.vector_mac fp_ops_retired_by_type.vector_sqrt sse_avx_ops_retired.mmx_sub sse_avx_ops_retired.mmx_pack Retired SSE and AVX integer add ops sse_avx_ops_retired.sse_avx_cmp fp_pack_ops_retired.fp128_sub fp_pack_ops_retired.fp256_sub Retired packed floating-point ops of all types Retired 128-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0x0f event=0xd,umask=0x10 packed_int_op_type.int256_mac packed_int_op_type.int256_other Number of PRECHARGE commands sent for reads umc_pchg_cmd.wr Store-to-load-forward (STLF) hits 64B misaligned (cacheline crossing) loads backend_bound_memory PipelineL2;retiring_group L2 instruction TLB misses and instruction page walks Remote socket outbound data from the CPU (e.g. write data) d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk) umc_cas_cmd_rate Ratio of memory controller CAS commands for reads d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all) DC_ACCESS IC_RETURN_STACK_OVERFLOW NB_MEMORY_CONTROLLER_TURNAROUND PMUEXTIN_EVT EVENT_10H EVENT_15H EVENT_35H EVENT_88H EVENT_9FH EVENT_E1H EVENT_EAH NEON_INSTRS_RENAMED L1D_CACHE_REFILL INST_RETIRED L1I_CACHE EVENT_100H EVENT_129H EVENT_142H EVENT_145H EVENT_151H EVENT_156H EVENT_178H EVENT_199H EVENT_19BH EVENT_1B4H EVENT_1E3H EVENT_1EAH EVENT_1F1H EVENT_215H EVENT_259H EVENT_266H EVENT_29CH EVENT_2AAH EVENT_2C5H EVENT_2CAH EVENT_2D6H EVENT_2D7H EVENT_31EH EVENT_34EH EVENT_376H EVENT_3B5H L1D_TLB_REFILL_ST L2D_CACHE_REFILL_ST EXC_TRAP_IRQ L2D_TLB_REFILL_WR hni_rrt_wr_occ_cnt_ovfl hni_awready_no_awvalid rni_rdb_replay cxha_snppcrd_lnk2_stall cxra_dat_pcrd_stalls_lnk0 cxla_avg_latency_process_rx_tlp cxla_avg_latency_form_tx_tlp clkdiv2_hazard_resolution PMON_SIG BRANCH_LINK_STACK_CORRECTLY_RESOLVED PREFETCH_ENGINE_REQUEST STOP_COMPLETION DISPATCH_SUCCESS SNOOP_PUSHES STASH_REQUESTS scalar-sse-sse2 probe-hit-dirty-no-memory-cancel + INTEL_XSCALE PPC_970 AuthenticAMD UNHALTED_CORE_CYCLES uncore ERROR: unrecognized event type: %d
}
GenuineIntel-6-55-[56789ABCDEF] GenuineIntel-6-86 This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN TmaL1 CORE_CLKS IpBranch Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate) L2 cache true misses per kilo instruction for retired demand loads Turbo_Utilization (cstate_core@c6\-residency@ / msr@tsc@) * 100 C3 residency percent per package C7 residency percent per package L2 cache lines in S state filling L2 L2 code requests l2_rqsts.code_rd_hit Demand Data Read requests that hit L2 cache event=0x24,period=200003,umask=0x3f l2_trans.demand_data_rd lock_cycles.cache_lock_duration longest_lat_cache.miss Retired load uop whose Data Source was: forwarded from remote cache (Precise Event) Supports address when precise. Spec update: BDE70 Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) Supports address when precise. Spec update: BDM35 (Precise event) move_elimination.simd_not_eliminated Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: BDM30 icache.hit event=0x80,period=2000003,umask=0x1 Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses Cycles MITE is delivering any Uop event=0xc8,period=2000003,umask=0x4 event=0x5,period=2000003,umask=0x2 rtm_retired.aborted_misc5 RTM region detected inside HLE event=0x88,period=200003,umask=0x41 event=0x88,period=200003,umask=0x88 br_misp_exec.all_branches Taken speculative and retired mispredicted indirect branches excluding calls and returns cpu_clk_unhalted.ref_xclk_any Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem) This event increments by 1 for every cycle where there was no execute for this thread cycle_activity.stalls_mem_any event=0xc3,cmask=1,edge=1,period=100003,umask=0x1 event=0xc3,period=100003,umask=0x20 event=0x58,period=1000003,umask=0x4 This event counts resource-related stall cycles. Reasons for stalls can be as follows:
- *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)
- *any* u-arch structure got empty (like INT/SIMD FreeLists)
- FPU control word (FPCW), MXCSR
and others. This counts cycles that the pipeline backend blocked uop delivery from the front end event=0xa1,period=2000003,umask=0x20 uops_executed.core uops_executed_port.port_5_core event=0xc2,cmask=1,inv=1,period=2000003,umask=0x1 Cycles with less than 10 actually retired uops Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode. Unit: uncore_cbox unc_h_requests.writes Conflict requests (requests for same address from multiple agents simultaneously). Unit: uncore_ha unc_h_snoop_resp.rspifwd event=0x43 event=0x8,period=2000003,umask=0x40 event=0x8,period=2000003,umask=0x20 event=0x8,period=100003,umask=0xe 64 * ( arb@event\=0x81\,umask\=0x1@ + arb@event\=0x84\,umask\=0x1@ ) / 1000000 / duration_time / 1000 Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: BDM100 (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0091 offcore_response.all_data_rd.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020120 offcore_response.corewb.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020004 offcore_response.demand_data_rd.l3_hit.snoop_hitm offcore_response.other.supplier_none.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0040 offcore_response.pf_l3_data_rd.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020080 offcore_response.pf_l3_rfo.l3_hit.any_snoop offcore_response.pf_l3_rfo.supplier_none.any_snoop offcore_response.all_data_rd.l3_miss.snoop_miss offcore_response.all_data_rd.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_none offcore_response.pf_l3_code_rd.l3_hit.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0200 offcore_response.pf_l3_code_rd.l3_miss.snoop_hit_no_fwd offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0100 unc_cbo_xsnp_response.miss_eviction L3 Lookup write request that access cache and found line in MESI-state. Unit: uncore_cbox Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70 (Precise event) Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_data_rd.llc_miss.remote_dram offcore_response.all_data_rd.llc_miss.remote_hitm offcore_response.all_rfo.llc_miss.local_dram event=0x40,period=200000,umask=0x48 event=0x27,period=200000,umask=0x50 event=0xca,period=2000000,umask=0x1 simd_uops_exec.s Bus cycles when data is sent on the bus bus_lock_clocks.self Burst (full cache-line) bus transactions bus_trans_io.all_agents event=0x6f,period=200000,umask=0x40 External snoops event=0x77,period=200000,umask=0x28 snoop_stall_drv.self br_inst_type_retired.ind_call event=0x3,period=200000,umask=0x81 Load uops retired that hit L1 data cache (Precise event capable) Supports address when precise (Must be precise) Locked load uops retired (Precise event capable) Supports address when precise (Must be precise) Counts data reads (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200003010 offcore_response.any_request.any_response Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines that miss the L2 cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_hit event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000041000 Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) baclears.cond event=0xc3,period=200003,umask=0x2 All machine clears Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors dl1.replacement event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040400 Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem offcore_response.streaming_stores.outstanding Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received event=0x8,period=200003,umask=0x2 STLB flushes Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) offcore_response.all_data_rd.l3_hit.hit_other_core_no_fwd Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l3_data_rd.l3_hit.any_response Counts all demand code reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00100 Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event) This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data) Number of uops delivered by the LSD Cycles with no micro-ops executed from any thread on physical core Spec update: HSD30, HSM31 L3 Lookup external snoop request that access cache and found line in M-state. Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in M-state A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core. Unit: uncore_cbox event=0xd3,period=100003,umask=0x4 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400244 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x06004007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x063F8007F7 offcore_response.demand_code_rd.llc_miss.any_response Not rejected writebacks from L1D to L2 cache lines in M state event=0x24,period=200003,umask=0x10 RFOs that miss cache lines offcore_response.split_lock_uc_lock.any_response simd_fp_256.packed_single Counts all demand & prefetch data reads that miss the LLC and the data returned from dram uops_dispatched_port.port_3_core uops_dispatched_port.port_4_core Cycles per core when uops are dispatched to port 5 Counts total number of uops to be executed per-core each cycle unc_cbo_xsnp_response.miss Filter on cross-core snoops initiated by this Cbox due to processor core memory request event=0x22,umask=0x80 Filter on cross-core snoops initiated by this Cbox due to LLC eviction. Unit: uncore_cbox Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc203f7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400010 PCIe read current. Derived from unc_c_tor_inserts.opcode.pcie_read_current. Unit: uncore_cbox PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.opcode.pcie_full_write. Unit: uncore_cbox Number of non data (control) flits transmitted . Unit: uncore_qpi unc_p_freq_band0_cycles Counts the number of cycles that the uncore was running at a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu event=0xd,period=2000003,umask=0x40 event=0x1,umask=0xc event=0x80 event=0x4,period=200003,umask=0x40 Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.any_data_rd.l2_hit_this_tile_s event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400070 Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state offcore_response.bus_locks.l2_hit_far_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080400 offcore_response.bus_locks.l2_hit_this_tile_f offcore_response.bus_locks.l2_hit_this_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080004 offcore_response.demand_code_rd.l2_hit_near_tile_m offcore_response.demand_data_rd.l2_hit_this_tile_m offcore_response.demand_rfo.l2_hit_this_tile_s offcore_response.partial_reads.l2_hit_near_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.pf_l1_data_rd.l2_hit_far_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000200 Counts the number of floating operations retired that required microcode assists offcore_response.any_pf_l2.ddr_near Counts any Prefetch requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400400 Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100401000 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far) offcore_response.uc_code_reads.mcdram Counts the number of branch instructions retired that were conditional jumps (Precise event) event=0xc5,period=200003,umask=0xf9 This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress event=0x5,edge=1,period=100003,umask=0x1 event=0x51,period=2000000,umask=0x4 l1d.m_repl event=0x28,period=100000,umask=0xf L2 data demand loads in I state (misses) event=0x26,period=200000,umask=0x2 l2_rqsts.ifetch_miss event=0x24,period=200000,umask=0xff event=0x24,period=200000,umask=0x8 L2 prefetch transactions event=0x27,period=100000,umask=0xf event=0x27,period=100000,umask=0x2 Memory instructions retired above 32768 clocks (Precise Event) event=0xf,period=10000,umask=0x10 Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) event=0xb7,period=100000,umask=0x1,offcore_rsp=0x411 Offcore requests satisfied by the IO, CSR, MMIO unit Offcore requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x47FF event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1022 Offcore code or data read requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4733 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3801 offcore_response.demand_ifetch.remote_cache_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF02 offcore_response.demand_rfo.llc_hit_other_core_hit Offcore other requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x430 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4730 Offcore prefetch data reads satisfied by any cache or DRAM Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF40 Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit offcore_response.pf_rfo.remote_cache_dram event=0xcc,period=2000000,umask=0x3 128 bit SIMD integer arithmetic operations event=0x12,period=200000,umask=0x8 event=0xfd,period=200000,umask=0x10 offcore_response.any_rfo.any_llc_miss event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2022 Offcore RFO requests satisfied by a remote DRAM offcore_response.corewb.local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2003 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4001 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6030 offcore_response.pf_data.any_llc_miss Offcore prefetch data requests satisfied by a remote DRAM All Store buffer stall cycles Thread responded HITM to snoop event=0x14,period=2000000,umask=0x2 event=0xd2,period=2000000,umask=0x1 rat_stalls.registers event=0xa2,period=2000000,umask=0x20 event=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x3f Uops retired (Precise Event) event=0x49,period=200000,umask=0x1 event=0xf1,period=100003,umask=0x1f l2_lines_out.silent Counts retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) Counts retired load instructions with at least one uop that hit in the L3 cache Supports address when precise (Precise event) offcore_response.demand_code_rd.l3_hit_m.snoop_none offcore_response.demand_data_rd.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C8000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100028000 Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events frontend_retired.dsb_miss Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event) icache_16b.ifdata_stall event=0x83,period=200003,umask=0x4 offcore_response.demand_code_rd.l3_miss.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C408000 Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations event=0xa6,period=2000003,umask=0x2 A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled Spec update: SKL091, SKL044 (Must be precise) Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector) Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6 Memory_Latency_SMT Memory_Data_TLBs_SMT Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type This event counts the number of load ops retired that had UTLB miss This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) (Precise event) Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_l2_code_rd.llc_hit.no_snoop_needed offcore_response.pf_l2_rfo.llc_miss.dram offcore_response.pf_l_data_rd.llc_miss_local.dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5011 REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE offcore_response.corewb.all_local_dram_and_remote_cache_hit REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5040 REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.demand_data.any_dram_and_remote_fwd REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf804 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3080 snoopq_requests_outstanding.invalidate_not_empty event=0x49,period=2000000,umask=0x4 Extended Page Table walk cycles itlb_misses.large_walk_completed event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2711 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2708 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5870 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6050 Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0400 OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd offcore_response.all_pf_rfo.l3_miss.remote_hitm Counts demand data reads that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800001 offcore_response.pf_l2_rfo.l3_miss.remote_hit_forward Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000100 Core cycles the out-of-order engine was throttled due to a pending power level request MMIO reads. Unit: uncore_cha event=0x50,umask=0x02 PCI Express bandwidth reading at IIO, part 0. Unit: uncore_iio unc_cha_dir_lookup.no_snp event=0xa5,umask=0x02 unc_cha_imc_reads_count.normal unc_cha_rxc_inserts.irq unc_iio_comp_buf_inserts.cmpd.part3 PCIe Completion Buffer occupancy of completions with data: Part 3 event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x04 Write request of 4 bytes made to IIO Part0 by the CPU. Unit: uncore_iio unc_iio_txn_req_by_cpu.mem_write.part3 unc_iio_txn_req_by_cpu.peer_write.part1 RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline. Unit: uncore_irp unc_i_transactions.wr_pref Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused) Partial Non-Isochronous writes to the iMC. Unit: uncore_m2m AD Ingress (from CMS) Occupancy. Unit: uncore_m2m unc_m2m_rxc_bl_occupancy unc_m2m_txc_ad_inserts event=0x15,umask=0x03 Data Response packets that go direct to core. Unit: uncore_upi FLITs received which bypassed the Slot0 Recieve Buffer. Unit: uncore_upi ocr.all_data_rd.l3_hit_e.hit_other_core_fwd ocr.all_data_rd.l3_hit_e.snoop_miss ocr.all_data_rd.l3_hit_f.any_snoop ocr.all_data_rd.l3_hit_f.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040491 ocr.all_data_rd.l3_hit_s.no_snoop_needed OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE ocr.all_pf_data_rd.l3_hit_m.hit_other_core_fwd ocr.all_pf_rfo.l3_hit_f.hit_other_core_fwd OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd ocr.all_pf_rfo.l3_hit_s.any_snoop ocr.all_pf_rfo.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100120 OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100120 ocr.all_reads.l3_hit.hitm_other_core OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0004 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_hit_m.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080001 ocr.demand_data_rd.l3_hit_f.hit_other_core_no_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE ocr.demand_rfo.l3_hit_e.hit_other_core_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD ocr.other.l3_hit_e.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100400 ocr.pf_l1d_and_sw.l3_hit_s.no_snoop_needed Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200010 ocr.pf_l2_data_rd.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100010 ocr.pf_l2_rfo.l3_hit.any_snoop ocr.pf_l2_rfo.l3_hit.hit_other_core_no_fwd ocr.pf_l2_rfo.l3_hit.snoop_none ocr.pf_l2_rfo.l3_hit_f.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_hit_m.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040020 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_hit_s.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040100 offcore_response.all_data_rd.l3_hit_f.hit_other_core_no_fwd offcore_response.all_data_rd.supplier_none.hit_other_core_no_fwd offcore_response.all_pf_data_rd.l3_hit_e.hitm_other_core offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_fwd offcore_response.all_pf_data_rd.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020490 offcore_response.all_pf_rfo.l3_hit_e.snoop_none offcore_response.all_pf_rfo.l3_hit_f.snoop_miss offcore_response.all_reads.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.all_rfo.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020122 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP offcore_response.demand_code_rd.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_hit_m.hit_other_core_no_fwd offcore_response.demand_data_rd.supplier_none.hit_other_core_no_fwd offcore_response.demand_rfo.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020010 This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020080 This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000491 OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000490 OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC0007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4040007F7 OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.demand_code_rd.l3_miss.remote_hit_forward event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000004 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000004 Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000001 ocr.demand_rfo.l3_miss.any_snoop Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000400 ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000020 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000020 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE ocr.pf_l3_data_rd.l3_miss_local_dram.hitm_other_core ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000100 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.all_reads.l3_miss_local_dram.no_snoop_needed offcore_response.all_rfo.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.demand_rfo.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.other.l3_miss_remote_hop1_dram.any_snoop offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.other.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS ocr.all_pf_rfo.supplier_none.no_snoop_needed Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE ocr.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop ocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xe3 All commands for Intel Optane DC persistent memory. Unit: uncore_imc unc_m2m_imc_reads.to_pmm l1d_pend_miss.l2_stall SW prefetch requests that hit L2 cache ocr.demand_rfo.l3_hit.any Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent ocr.hwpf_l1d_and_swpf.l3_hit.snoop_not_needed Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required ocr.other.l3_hit.snoop_sent Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle event=0xc8,period=100003,umask=0x2 event=0xc9,period=100003,umask=0x2 ocr.demand_data_rd.dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000002 Counts all branch instructions retired (Precise event) Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall Cycles when RAT does not issue Uops to RS for the thread event=0xe,period=100003,umask=0x2 Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB) exe_activity.bound_on_loads UOPS_EXECUTED.THREAD / ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) MemoryBW Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3 This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD Supports address when precise (Precise event) Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket ocr.reads_to_core.l3_hit.snoop_hit_with_fwd ocr.streaming_wr.l3_hit Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket Cycles with outstanding code read requests pending ( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / cha_0@event\=0x0@ ) Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM ocr.demand_rfo.remote_pmm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10070 Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response event=0x20,umask=0x01 CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH. Unit: uncore_cha Lines Victimized : All Lines Victimized. Unit: uncore_cha TOR Inserts : All requests from iA Cores that Hit the LLC. Unit: uncore_cha TOR Inserts : RFOs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_crd_pref unc_cha_tor_inserts.io_itom TOR Inserts : DRd_Prefs issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_rfo_remote event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x01 event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x01 FAF allocation -- sent to ADQ. Unit: uncore_irp Responses to snoops of any type that hit M line in the IIO cache. Unit: uncore_irp CMS Clockticks. Unit: uncore_m2m event=0x38,umask=0x1C80 uncore_ubox event=0x35,umask=0xCD42FF04 Counts the total number of L2 Cache accesses. Counts on a per core basis event=0x24,period=200003,umask=0x2 Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache mem_bound_stalls.store_buffer_full event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0044 Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded ocr.hwpf_l2_rfo.l3_hit This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT Counts the number of core cycles during which interrupts are masked (disabled) ocr.all_code_rd.local_dram Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM Counts streaming stores which modify a full 64 byte cacheline that have any type of response Counts all hardware and software prefetches that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10477 ocr.uc_wr.any_response Counts uncached memory writes that have any type of response Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path (Precise event) topdown_fe_bound.cisc Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory event=0x35,umask=0xC001FE01,config1=0x41833 CMS Clockticks TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0x8,period=200003,umask=0x20 Counts the number Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches event=0x4f,period=2000003,umask=0x4 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault cpu_core Fraction of branches that are CALL or RET. Unit: cpu_core Fraction of cycles spent in the Operating System (OS) Kernel mode. Unit: cpu_core BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY Cycle cost per L2 hit. Unit: cpu_atom 100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / ( MEM_BOUND_STALLS.IFETCH ) 1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY Counts the number of cycles that uops are blocked due to a load buffer full condition. Unit: cpu_atom mem_uops_retired.load_latency_gt_256 l1d_pend_miss.l2_stalls Retired load instructions with L3 cache hits as data sources Supports address when precise (Precise event). Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x8003C0001 Retired Instructions who experienced Instruction L1 Cache true miss (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x600806 Cycles MITE is delivering optimal number of Uops. Unit: cpu_core Cycles when uops are being delivered to IDQ while MS is busy. Unit: cpu_core Cycles while L1 cache miss demand load is outstanding. Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles Supports address when precise (Must be precise). Unit: cpu_core Counts demand data reads that were not supplied by the L3 cache. Unit: cpu_core Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS). Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes. Unit: cpu_atom Conditional branch instructions retired (Precise event). Unit: cpu_core cpu_clk_unhalted.pause Counts number of cycles no uops were dispatched to be executed on this thread. Unit: cpu_core unc_m_vc0_requests_wr incoming write request page status is Page Hit. Unit: uncore_imc PRE command sent to DRAM for a read/write request. Unit: uncore_imc event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F803C0001 ARITH.FPDIV_ACTIVE FP_ARITH_DISPATCHED.PORT_0 FP_ARITH_INST_RETIRED2.128B_PACKED_HALF event=0x2a,period=100003,umask=0x1,offcore_rsp=0x703000001 INT_VEC_RETIRED.128BIT event=0x10,umask=0x0000000002 unc_m_cas_count.wr_nonpre event=0x50,umask=0x0000000002 event=0x2,umask=0x0000000001 unc_upi_rxl_basic_hdr_match.ncs_opc event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000004 event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000004 UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS. Unit: uncore_iio unc_m2m_prefcam_inserts.xpt_allch event=0x58,umask=0x0000000005 : UPI - All Channels. Unit: uncore_m2m event=0x53,umask=0x0000000002 event=0x54,umask=0x0000000001 event=0x35,umask=0x00c001fd01 TOR Inserts; All from local IO. Unit: uncore_cha TOR Inserts : IPQ. Unit: uncore_cha event=0x35,umask=0x00c000ff01 event=0x35,umask=0x00C000FF05 TOR Inserts : Just NonCoherent. Unit: uncore_cha TOR Inserts; CRd Pref misses from local IA. Unit: uncore_cha event=0x35,umask=0x00cc47ff01 TOR Inserts;SpecItoM from Local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_llcprefrfo event=0x36 TOR Occupancy : MMIO Access. Unit: uncore_cha unc_cha_tor_occupancy.isoc TOR Occupancy; DRd Opt Pref hits from local IA. Unit: uncore_cha TOR Occupancy; DRd Pref from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_drdpte TOR Inserts; RdCur and FsRdCur hits from local IO. Unit: uncore_cha event=0x35,umask=0x00cccffe01 unc_cha_tor_occupancy.ia_miss_llcprefcode unc_cha_tor_inserts.ia_miss_itom event=0x35,umask=0x00CC47FE01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely. Unit: uncore_cha event=0x36,umask=0x00c8c7ff01 event=0x36,umask=0x00c86f8601 event=0x8b bp_snp_re_sync l2_wcb_req.zero_byte_store xi_sys_fill_latency event=0xc5 Retired Far Control Transfers event=0x1cf,umask=0x04 Tagged IBS Ops. Number of Ops tagged by IBS The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3 fp_ret_sse_avx_ops.dp_div_flops LS MAB allocates by type - stores L1 DTLB Reload of a page of 2M size event=0x47 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailable all_dc_accesses all_l2_cache_accesses Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group) bp_l1_tlb_fetch_hit.if4k event=0x85,umask=0xff bp_l1_tlb_miss_l2_tlb_miss.if2m event=0x85,umask=0x02 Retired Conditional Branch Instructions Mispredicted Number of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes Number of accesses to the dcache for load/store references Demand Data Cache Fills by Data Source. Local L2 hit Software Prefetch Instructions Dispatched (Speculative) Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote) event=0x59,umask=0x08 event=0xaa,umask=0x01 de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall All Instruction Cache Accesses. Counts various IC tag related hit and miss events ex_ret_ind_brch_instr event=0x41,umask=0x7f Any Data Cache Fills by Data Source. From cache of different CCX in same node The number of 4KB misaligned (i.e., page crossing) loads ls_tlb_flush.all_tlb_flushes Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Load Queue resource stall. Applies to all ops with load semantics Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction Retired indirect branch instructions Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache) L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) l2_pf_miss_l2_l3.l2_stride event=0xad,umask=0x3f ex_no_retire.empty event=0x120,umask=0x1 ex_ret_ucode_instr event=0x29f,umask=0x7fe event=0x29f,umask=0xbff event=0x55e,umask=0x7fe event=0x45e,umask=0x7ff Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 4 event=0x45e,umask=0xbff event=0x55e,umask=0xbff remote_socket_inf1_outbound_data_beats_ccm1 event=0xb5f,umask=0xf3e Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 4 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 6 event=0x8,umask=0x08 Retired packed 128-bit floating-point ops fp_ops_retired_by_width.pack_512_uops_retired fp_ops_retired_by_type.vector_sub event=0xb,umask=0xa0 event=0xb,umask=0xb0 Retired 128-bit packed integer MOV ops packed_int_op_type.int256_shuffle packed_int_op_type.int256_pack Floating-point dispatch faults for x87 fills fp_disp_faults.all Number of CAS commands sent for writes umc_data_slot_clks.rd Fraction of dispatched ops that were flushed due to pipeline restarts (resyncs) Fraction of dispatch slots that remained unused because of stalls due to the memory subsystem l2_cache_accesses_from_l1_dc_misses L2 cache misses from L2 cache hardware prefetcher l2_cache_hits_from_l1_dc_miss bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all Macro-ops dispatched local_processor_write_data_beats_cs0 + local_processor_write_data_beats_cs1 + local_processor_write_data_beats_cs2 + local_processor_write_data_beats_cs3 + local_processor_write_data_beats_cs4 + local_processor_write_data_beats_cs5 + local_processor_write_data_beats_cs6 + local_processor_write_data_beats_cs7 + local_processor_write_data_beats_cs8 + local_processor_write_data_beats_cs9 + local_processor_write_data_beats_cs10 + local_processor_write_data_beats_cs11 remote_processor_read_data_beats_cs0 + remote_processor_read_data_beats_cs1 + remote_processor_read_data_beats_cs2 + remote_processor_read_data_beats_cs3 + remote_processor_read_data_beats_cs4 + remote_processor_read_data_beats_cs5 + remote_processor_read_data_beats_cs6 + remote_processor_read_data_beats_cs7 + remote_processor_read_data_beats_cs8 + remote_processor_read_data_beats_cs9 + remote_processor_read_data_beats_cs10 + remote_processor_read_data_beats_cs11 ccn read-cycles event. Unit: uncore_sys_ccn_pmu hwpmc DC_L1_DTLB_MISS_AND_L2_DTLB_MISS DC_ONE_BIT_ECC_ERROR IC_MISS FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE FR_TAKEN_HARDWARE_INTERRUPTS NB_HT_BUS0_BANDWIDTH NB_HT_BUS2_BANDWIDTH L2_STORE_BUFFERABLE L1_CACHE_PAGECOL_ALIAS L2_CACHE_NEON_MEM_ACCESS EVENT_33H EVENT_51H EVENT_54H EVENT_86H EVENT_89H EVENT_9AH EVENT_ACH EVENT_BAH EVENT_EDH SW_INCR EVENT_10AH EVENT_11AH EVENT_1A0H EVENT_1B2H EVENT_1D0H EVENT_1F4H EVENT_23EH EVENT_251H EVENT_271H EVENT_27FH EVENT_28FH EVENT_293H EVENT_2BDH EVENT_2F6H EVENT_30EH EVENT_31BH EVENT_34AH EVENT_364H EVENT_366H EVENT_36BH EVENT_37BH EVENT_398H EVENT_3A4H EVENT_3A7H EVENT_3E8H MEM_ACCESS_LD BUS_ACCESS_NORMAL BR_RETIRED L2D_TLB_RD hnf_brd_snoops_sent hnf_seq_hit xp_partial_dat_flit sbsx_rd_req_trkr_occ_cnt_ovfl rnd_wrcancel_sent rni_s2_wdata_beats clkdiv2_allocate PMON_EXCEPT VFPU_INSTR_COMPLETED VPU_INSTR_WAIT_CYCLES DSS_INSTR_COMPLETED DST_STREAM_0_CACHE_LINE_FETCHES LSU_STORE_QUEUE_INDEX_ALIAS L2_CACHE_HITS FPU_COMPLETION_STALL L2_CACHE_DIRTY_UPDATES DVT3_DETECTED STWCX_FAILURES es load misses PPC_7450 ARMV8_CORTEX_A53 {"type": "initialize" %s, "version": "0x%08x", "arch": "0x%08x", "cpuid": "%s", "tsc_freq": "%jd", "sec": "%jd", "nsec": "%jd"}
%s, "oldpid": "%d", "newpid": "%d"}
IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD) This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU CPU_CLK_UNHALTED.THREAD Branches;Fed;PGO INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST 1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY Mem;CacheMisses;Offcore CPU_CLK_UNHALTED.REF_TSC / msr@tsc@ (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time C2 residency percent per package This event counts the total number of requests from the L2 hardware prefetchers event=0xd0,period=2000003,umask=0x81 event=0xca,cmask=1,period=100003,umask=0x1e event=0xc1,period=100003,umask=0x10 event=0x79,cmask=4,period=2000003,umask=0x18 event=0x79,cmask=1,period=2000003,umask=0x24 This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ Instruction Decode Queue (IDQ) empty cycles hle_retired.start Loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) Loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above four Spec update: BDM100, BDM35 (Must be precise) rtm_retired.aborted_misc1 event=0xc9,period=2000003,umask=0x20 This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3 This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired (Precise event) Taken branch instructions retired. (Precise Event - PEBS) (Precise event) Not taken branch instructions retired br_misp_exec.taken_return_near event=0xc5,period=400009,umask=0x4 cpu_clk_thread_unhalted.one_thread_active cpu_clk_unhalted.ref_xclk event=0xa3,cmask=5,period=2000003,umask=0x5 event=0xa3,cmask=6,period=2000003,umask=0x6 Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request ld_blocks.no_sr This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end event=0xa1,period=2000003,umask=0x2 event=0xa1,period=2000003,umask=0x10 event=0xa1,any=1,period=2000003,umask=0x20 uops_executed_port.port_6 uops_issued.any Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS) Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox unc_h_snoop_resp.rsp_fwd_wb event=0x85 unc_p_power_state_occupancy.cores_c6 Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) Spec update: BDM69 event=0x49,period=100003,umask=0x10 This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches event=0x85,period=100003,umask=0xe Number of DTLB page walker hits in the L1+FB Spec update: BDM69, BDM98 Number of ITLB page walker hits in the L1+FB Spec update: BDM69, BDM98 offcore_response.all_pf_code_rd.l3_hit.any_snoop offcore_response.all_pf_data_rd.l3_hit.snoop_hitm offcore_response.all_pf_rfo.l3_hit.snoop_hitm offcore_response.all_rfo.supplier_none.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0008 offcore_response.corewb.supplier_none.snoop_hit_no_fwd offcore_response.corewb.supplier_none.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of times HLE abort was triggered (Precise event) Counts randomly selected loads with latency value being above four Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) offcore_response.all_data_rd.l3_miss_local_dram.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000090 offcore_response.all_pf_data_rd.l3_miss.snoop_none offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_non_dram offcore_response.all_rfo.l3_miss.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000008 offcore_response.corewb.l3_miss_local_dram.snoop_non_dram offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000004 offcore_response.demand_code_rd.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000004 offcore_response.demand_data_rd.l3_hit.snoop_non_dram offcore_response.demand_rfo.l3_miss.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000028000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000080 Number of near branch instructions retired that were mispredicted and taken (Precise event) event=0x34,umask=0x1f event=0x34,umask=0x16 Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc. Unit: uncore_arb Counts all demand & prefetch data reads miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x063BC00091 Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache l1d_cache.repl event=0x28,period=200000,umask=0x4f l2_lines_in.self.any l2_lock.self.i_state l2_rqsts.self.any.i_state event=0x2e,period=200000,umask=0x4f misalign_mem_ref.bubble event=0x6d,period=200000,umask=0xe0 ext_snoop.this_agent.any event=0x88,period=2000000,umask=0x10 br_inst_type_retired.ind event=0x88,period=2000000,umask=0x4 Micro-op reissues for any cause (At Retirement) DTLB misses due to load operations Retired loads that miss the DTLB (precise event) (Precise event) Stores uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x04000032b7 Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000022 Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_code_rd.l2_miss.any Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_hit event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000002 offcore_response.partial_streaming_stores.l2_miss.hitm_other_core event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200004000 offcore_response.pf_l1_data_rd.l2_miss.any offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_needed offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwd event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000020 Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns Decode restrictions due to predicting wrong instruction length fetch_stall.itlb_fill_pending_cycles Retired branch instructions (Precise event capable) (Must be precise) Retired near indirect call instructions (Precise event capable) (Must be precise) Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken (Must be precise) Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted (Must be precise) issue_slots_not_consumed.any Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted (Must be precise) event=0xc2,period=2000003 Counts the number of integer divide uops retired (Must be precise) Counts store uops retired that caused a DTLB miss Supports address when precise (Must be precise) Counts bus lock and split lock requests hit the L2 cache Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.full_streaming_stores.any_response Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data dtlb_store_misses.walk_pending Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise. Spec update: HSM30 (Precise event) Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: HSD76, HSD29, HSM30 (Precise event) Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61, HSM63 Counts prefetch (that bring data to L2) data reads hit in the L3 Number of X87 FP assists due to output values Number of SIMD move elimination candidate uops that were eliminated Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE Spec update: HSD135 ( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) offcore_response.pf_l2_code_rd.l3_miss.any_response event=0xc4,period=100003,umask=0x40 Misses in all TLB levels that cause a page walk of any page size Store misses in all DTLB levels that cause page walks Store miss in all TLB levels causes a page walk that completes. (1G) event=0xbc,period=2000003,umask=0x44 offcore_response.pf_l2_code_rd.llc_miss.any_response event=0x28,period=200003,umask=0x8 l2_lines_out.pf_dirty mem_load_uops_llc_hit_retired.xsnp_hitm Retired load uops which data sources were hits in LLC without snoops required (Precise event) Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle Number of assists associated with 256-bit AVX store operations Instruction cache, streaming buffer and victim cache misses Number of any page walk that had a miss in LLC Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) Cycles per core when uops are dispatched to port 4 Number of flags-merge uops allocated. Such uops adds delay unc_arb_trk_requests.evictions LLC lookup request that access cache and found line in M-state. Unit: uncore_cbox itlb_misses.large_page_walk_completed offcore_response.pf_l2_data_rd.llc_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f820004 offcore_response.pf_l2_data_rd.llc_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc00010 (UNC_P_FREQ_GE_3000MHZ_CYCLES / UNC_P_CLOCKTICKS) * 100. l1d_blocks.bank_conflict_cycles event=0xbf,cmask=1,period=100003,umask=0x5 dsb_fill.all_cancel Valid instructions written to IQ per cycle event=0xc5,period=100007,umask=0x2 event=0x59,period=2000003,umask=0x40 Cycles with at least one slow LEA uop being allocated event=0x4,period=100007,umask=0x4 Counts Demand code reads and prefetch code read requests that accounts for any response offcore_response.any_code_rd.l2_hit_this_tile_m Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts any request that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400022 offcore_response.demand_data_rd.l2_hit_far_tile_e_f offcore_response.demand_data_rd.l2_hit_far_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000002 Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080100 offcore_response.partial_writes.l2_hit_this_tile_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002002000 Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state event=0xc2,period=200003,umask=0x20 Counts all instruction fetches that hit the instruction cache offcore_response.any_data_rd.ddr_far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101003091 offcore_response.any_data_rd.mcdram_far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200070 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600022 Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local Counts L1 data HW prefetches that accounts for data responses from DRAM Local Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far) Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full recycleq.st_splits Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry L1 data cache lines allocated l1d_cache_st.s_state L1D hardware prefetch misses L1D hardware prefetch requests L2 data prefetches in M state event=0xf1,period=100000,umask=0x4 All L2 demand store RFOs that hit the cache event=0x2e,period=100000,umask=0x41 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F44 Offcore code reads satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFFFF Offcore requests satisfied by the LLC and HIT in a sibling core offcore_response.any_request.remote_cache_hit Offcore requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x708 offcore_response.corewb.remote_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3833 Offcore other requests satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3830 offcore_response.pf_data.remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1810 offcore_response.pf_ifetch.llc_hit_no_other_core Offcore prefetch code reads that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1870 fp_assist.input Offcore code reads satisfied by a remote DRAM offcore_response.demand_data.any_llc_miss event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6002 offcore_response.pf_rfo.remote_dram event=0x13,period=2000000,umask=0x2 event=0xd4,period=2000000,umask=0x1 arith.cycles_div_busy BACLEAR asserted with bad target address baclear_force_iq event=0xe8,period=2000000,umask=0x1 br_inst_exec.return_near event=0x89,period=20000,umask=0x7f cpu_clk_unhalted.ref_p Execution pipeline restart due to Memory ordering conflicts event=0xc7,period=200000,umask=0x1 uops_executed.port0 event=0x8,period=200000,umask=0x20 Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event) Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0080004 offcore_response.demand_rfo.l4_hit_local_l4.any_snoop offcore_response.demand_rfo.l4_hit_local_l4.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C8000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80048000 offcore_response.other.l3_hit_m.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40048000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000408000 offcore_response.other.l4_hit_local_l4.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40408000 Number of cache line split locks sent to uncore Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event) Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3 Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles Supports address when precise (Must be precise) Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC400004 offcore_response.demand_rfo.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x44000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C408000 tx_mem.abort_capacity event=0xa6,period=2000003,umask=0x4 Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products 1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) 100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) Instruction_Fetch_BW_SMT ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES Store misses in all TLB levels causes a page walk that completes. (All page sizes) Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.) Counts the number of request that were not accepted into the L2Q because the L2Q is FULL Counts the number of request from the L2 that were not accepted into the XQ Counts any rfo reads (demand & prefetch) that have any response type Counts demand and DCU prefetch RFOs that miss L2 Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received Counts RFO requests generated by L2 prefetchers that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680004800 Loads missed DTLB (Precise event) REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0100 offcore_response.pf_l_ifetch.any_response offcore_response.pf_llc_data_rd.llc_miss.dram offcore_requests_outstanding.any.read_not_empty offcore_response.any_data.local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7ff REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE offcore_response.corewb.llc_hit_other_core_hit REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff04 REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f80 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x150 REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM misalign_mem_ref.store REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS REQUEST = OTHER and RESPONSE = ANY_LLC_MISS DTLB load miss page walk cycles dtlb_misses.large_walk_completed ITLB miss page walk cycles event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5822 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5803 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0491 Counts prefetch (that bring data to L2) data reads that hit in the L3 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00491 Counts all prefetch data reads that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800490 offcore_response.demand_data_rd.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000002 offcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forward event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00400 Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not unc_m_cas_count.wr_wmm Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed Multi-socket cacheline Directory state lookups; Snoop Needed. Unit: uncore_cha FaST wire asserted; Horizontal. Unit: uncore_cha Lines Victimized; Lines in M state. Unit: uncore_cha Number of times that an RFO hit in S state. Unit: uncore_cha Snoop filter capacity evictions for S-state entries. Unit: uncore_cha unc_cha_snoop_resp.rspi event=0xc2,ch_mask=0x02,fc_mask=0x4,umask=0x03 unc_iio_comp_buf_occupancy.cmpd.part0 PCIe Completion Buffer occupancy of completions with data: Part 2 unc_iio_data_req_by_cpu.peer_write.part3 Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.mem_write.part0 Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part2 Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio event=0x19 Occupancy of the IRP FAF queue. Unit: uncore_irp BL Ingress (from CMS) Occupancy event=0x31,umask=0x1 event=0x41 ocr.all_data_rd.l3_hit.any_snoop OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ocr.all_data_rd.l3_hit_f.hit_other_core_no_fwd OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_hit_f.snoop_none ocr.all_data_rd.l3_hit_m.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100491 OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP ocr.all_pf_data_rd.l3_hit_e.no_snoop_needed ocr.all_pf_data_rd.l3_hit_e.snoop_none OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS ocr.all_pf_rfo.l3_hit_m.snoop_miss ocr.all_reads.l3_hit_m.snoop_miss ocr.all_rfo.l3_hit.hit_other_core_fwd ocr.all_rfo.l3_hit.snoop_hit_with_fwd OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED ocr.demand_code_rd.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100004 Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE ocr.demand_data_rd.l3_hit_m.no_snoop_needed ocr.demand_rfo.l3_hit.no_snoop_needed ocr.demand_rfo.l3_hit_e.any_snoop Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0400 ocr.pf_l1d_and_sw.l3_hit_f.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040400 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP ocr.pf_l2_data_rd.l3_hit.no_snoop_needed Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_s.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080080 ocr.pf_l3_data_rd.l3_hit_f.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040080 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200100 ocr.pf_l3_rfo.l3_hit_s.snoop_miss offcore_response.all_data_rd.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020491 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_e.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_s.snoop_miss offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000207F7 offcore_response.all_rfo.l3_hit_e.hit_other_core_fwd offcore_response.all_rfo.l3_hit_f.snoop_miss This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE offcore_response.demand_code_rd.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE offcore_response.demand_data_rd.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_miss offcore_response.pf_l1d_and_sw.l3_hit_m.any_snoop This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_fwd offcore_response.pf_l2_rfo.l3_hit_m.snoop_miss offcore_response.pf_l3_data_rd.l3_hit_e.no_snoop_needed offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020100 Intel AVX-512 computational 512-bit packed BFloat16 instructions retired OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000122 ocr.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000002 ocr.other.l3_miss.no_snoop_needed ocr.other.l3_miss.remote_hit_forward ocr.other.l3_miss_local_dram.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000400 ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000020 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000100 offcore_response.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none offcore_response.all_reads.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED offcore_response.demand_code_rd.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP offcore_response.other.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.all_data_rd.any_response ocr.all_pf_rfo.supplier_none.hit_other_core_fwd ocr.all_rfo.any_response Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD ocr.demand_rfo.supplier_none.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.pf_l2_rfo.any_response event=0xe7 event=0xd0,period=1000003,umask=0x82 Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores Supports address when precise (Precise event) Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required ocr.hwpf_l1d_and_swpf.l3_hit.any Retired instructions after front-end starvation of at least 1 cycle (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x501006 idq.ms_cycles_any event=0x79,cmask=1,edge=1,period=100003,umask=0x30 C9 residency percent per package ocr.hwpf_l1d_and_swpf.l3_miss event=0xc9,period=100003,umask=0x4 ocr.other.dram Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Precise event) False dependencies due to partial compare on address event=0x5e,cmask=1,edge=1,inv=1,period=100003,umask=0x1 event=0x8,period=100003,umask=0x4 Branches;FetchBW;PGO MemoryBound;MemoryBW Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data ocr.demand_rfo.snc_cache.hit_with_fwd Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x830000477 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x94002380 Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster ocr.demand_data_rd.snc_dram Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode ocr.reads_to_core.local_socket_dram Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket All DRAM write CAS commands issued. Unit: uncore_imc unc_m_pre_count.pgt Remote read requests sent to the CHA's home agent. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit TOR Occupancy : RFOs issued by iA Cores that Missed the LLC. Unit: uncore_cha event=0x36,umask=0xC001FF04 TOR Inserts : LLCPrefRFO issued by iA Cores. Unit: uncore_cha TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha TOR Inserts : CLFlushes issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_local_pmm TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha PCIe Completion Buffer Occupancy of completions with data : Part 7. Unit: uncore_iio unc_m2m_tag_hit.nm_rd_hit_clean unc_m2p_cms_clockticks event=0x24,period=200003 l2_request.miss mem_bound_stalls.ifetch_l2_hit Counts the number of retired split loads uops Supports address when precise (Precise event) Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache ocr.hwpf_l2_code_rd.l3_hit.snoop_hit_with_fwd Counts streaming stores that were not supplied by the L3 cache event=0x63,edge=1,period=200003 This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000477 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline event=0x35,umask=0xC827FF01 TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0x35,umask=0xC877DE01 TOR Inserts : WiLs issued by iA Cores that Missed LLC. Unit: uncore_cha TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts : All Inserts Inbound (p2p + faf + cset) Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle CPU_CLK_UNHALTED.CORE Address_Alias_Blocks Percentage of all uops which are ucode ops. Unit: cpu_atom MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT event=0xd0,period=1000003,umask=0x5,ldlat=0x100 L2 cache misses when fetching instructions. Unit: cpu_core Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. Unit: cpu_core offcore_requests.data_rd event=0x20,cmask=1,period=1000003,umask=0x8 fp_arith_dispatched.port_5 Retired Instructions who experienced a critical DSB miss (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x620006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core ld_head.other_at_ret Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check (Precise event). Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized. Unit: cpu_atom number of branch instructions retired that were mispredicted and taken. Non PEBS (Precise event). Unit: cpu_core TMA slots available for an unhalted logical processor. General counter - architectural event. Unit: cpu_core Uops executed on ports 5 and 11. Unit: cpu_core Cycles where at least 4 uops were executed per-thread. Unit: cpu_core Counts the number of uops to be executed per-thread each cycle. Unit: cpu_core uops_retired.cycles unc_m_dram_page_miss_rd Page walks completed due to a demand data load to a 1G page. Unit: cpu_core Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO event=0x2a,period=100003,umask=0x1,offcore_rsp=0xFBFF80822 rs_empty.cycles event=0xe4,umask=0x0000000001 unc_m_pre_count.wr_pch0 IIO Clockticks. Unit: uncore_iio event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000002 TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode. Unit: uncore_upi RxQ Occupancy - All Packets : Slot 0. Unit: uncore_upi Data requested of the CPU : Card reading from DRAM. Unit: uncore_iio event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000001 event=0xc1,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000001 event=0x33,umask=0x0000000002 event=0x50,umask=0x0000000010 TOR Inserts; DRd from local IA. Unit: uncore_cha event=0x35,umask=0x00c827ff01 TOR Occupancy; All Snoops from Remote. Unit: uncore_cha TOR Occupancy; CRd hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.evict event=0x36,umask=0x00c8a7fd01 unc_cha_tor_occupancy.io_hit_rfo unc_cha_tor_occupancy.ia_miss_rfo_pref_remote event=0x35,umask=0x00cccffd01 TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0x00c8168601 TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0x00cc47fe01 TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC. Unit: uncore_cha TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely. Unit: uncore_cha IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core event=0x60,umask=0x08 Miscellaneous events covered in more detail by l2_request_g2 (PMCx061) L3 cache misses. Unit: amd_l3 All L3 Miss Request Types. Ignores SliceMask and ThreadMask. Unit: amd_l3 ex_tagged_ibs_ops.ibs_tagged_ops_ret event=0x1d0 event=0x107,umask=0x38 Total number of fp uOps on pipe 0 All Ops The number of serializing Ops retired. x87 bottom-executing uOps retired The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer event=0x28a,umask=0x02 L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch) l3_misses LS MAB Allocates by Type. DC prefetcher L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB All TLB Flushes event=0xae,umask=0x20 de_dis_dispatch_token_stalls1.int_sched_misc_token_stall event=0xae,umask=0x01 Counts retired Fused Instructions Demand Data Cache Fills by Data Source. From CCX Cache in different Node Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP scheduler resource stall. Applies to ops that use the FP scheduler Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Taken branch buffer resource stall Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Store Queue resource stall. Applies to all ops with store semantics (xi_sys_fill_latency * 16) / xi_ccx_sdp_req1 L1 Data Cache Fills: From Remote Node L1 Data Cache Fills: From within same CCX L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) event=0x71,umask=0x02 L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) event=0xad,umask=0x02 L3 cache fill requests sourced from all data sources. Unit: amd_l3 SMIs received Write data beats (64 bytes) for local processor at Coherent Station (CS) 3 remote_processor_read_data_beats_cs6 remote_processor_write_data_beats_cs4 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0 event=0x85f,umask=0xbff event=0x41e,umask=0x7fe event=0x51e,umask=0x7fe local_socket_inf1_inbound_data_beats_ccm7 local_socket_inf0_outbound_data_beats_ccm2 remote_socket_inf1_inbound_data_beats_ccm7 remote_socket_inf0_outbound_data_beats_ccm5 fp_ops_retired_by_width.all fp_ops_retired_by_type.vector_logical event=0xb,umask=0x0c Retired SSE and AVX integer subtract ops Retired SSE and AVX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) Retired 256-bit packed floating-point add ops event=0xc,umask=0x40 fp_pack_ops_retired.all Retired 256-bit packed integer compare ops Floating-point dispatch faults of all types Number of CAS commands sent Number of memory load-store operations dispatched to the load-store unit frontend_bound L1 demand data cache fills from within the same CCX l1_demand_data_cache_fills_from_far_cache L1 demand data cache fills from DRAM or MMIO in a different NUMA node Memory controller CAS command rate Attributable Level 3 cache access, read Total read hits. Unit: hisi_sccl,l3c sys_ccn_pmu.read_cycles IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP FR_RETIRED_UOPS FR_NUMBER_OF_BREAKPOINTS_FOR_DR1 EVENT_80H EVENT_8EH EVENT_97H EVENT_98H EVENT_9EH EVENT_B0H EVENT_B9H INTEGER_CORE_CLOCK_ENABLED EVENT_102H EVENT_127H EVENT_14EH EVENT_16DH EVENT_176H EVENT_1FFH EVENT_204H EVENT_207H EVENT_236H EVENT_277H EVENT_27DH EVENT_292H EVENT_296H EVENT_2ACH EVENT_2EAH EVENT_32EH EVENT_334H EVENT_36EH EVENT_3AAH EVENT_3C0H EVENT_3C4H EVENT_3CCH EVENT_3E7H EVENT_3F5H EVENT_3FCH VFP_SPEC STALL_BACKEND dn_rxreq_bpi_dvmop hnf_dir_snoops_sent hni_rrt_rd_occ_cnt_ovfl hni_rrt_rd_alloc xp_txflit_valid cxha_rdb_occ clkdiv2_cycle_count clkdiv2_ranks_in_pwr_down VIU2_INSTR_WAIT_CYCLES THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES BTIC_MISS TLBSYNC_INSTR_COMPLETED GROUP_DISPATCH MARKED_GROUP_ISSUED REJECT_COMPLETION_STALL_ERAT_MISS PM_EVENT_CYCLES CYCLES_MU_SCHED_STALLED MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED INTERRUPTS_TAKEN gs page-conflict memory-controller-lo-pri-bypass branches dc-misses READ INTEL_IVYBRIDGE_XEON STOPPED LLC_MISSES cpu_clk_unhalted.thread RESOURCE_STALLS.ANY frontend_retired.l1i_miss ch_mask l3_thread_mask {"type": "closelog"}
{"type": "procexit" {"type": "map_out" core GenuineIntel-6-9A Flops;InsType IpArith_Scalar_SP This event counts the number of WB requests that hit L2 cache L2 cache hits when fetching instructions, code reads L2 cache misses when fetching instructions This event counts L1D writebacks that access L2 cache mem_load_uops_l3_miss_retired.local_dram This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 fp_arith_inst_retired.scalar_single fp_assist.any event=0x58,period=1000003,umask=0x8 Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled event=0xc8,period=2000003,umask=0x80 event=0xc9,period=2000003,umask=0x8 event=0xc9,period=2000003,umask=0x1 Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty event=0x54,period=2000003,umask=0x40 other lock_cycles.split_lock_uc_lock_duration event=0x14,period=2000003,umask=0x1 br_inst_exec.nontaken_conditional Far branch instructions retired Spec update: BDW98 Cycles while L1 cache miss demand load is outstanding Not software-prefetch load dispatches that hit FB allocated for hardware prefetch machine_clears.cycles event=0xa1,period=2000003,umask=0x80 Cycles at least 4 micro-op is executed from any thread on physical core uops_executed_port.port_2 event=0xc2,cmask=10,inv=1,period=2000003,umask=0x1 event=0x35,umask=0x3,filter_opc=0x1c8,filter_tid=0x3e event=0x49,period=100003,umask=0x1 dtlb_store_misses.walk_duration Misses at all ITLB levels that cause page walks Spec update: BDM69 event=0x24,period=200003,umask=0xc4 Counts all demand & prefetch data reads have any response type offcore_response.all_pf_data_rd.l3_hit.snoop_miss offcore_response.all_pf_data_rd.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020090 offcore_response.all_pf_rfo.supplier_none.snoop_none offcore_response.demand_code_rd.l3_hit.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0004 Counts demand data reads have any response type offcore_response.demand_data_rd.l3_hit.snoop_none offcore_response.demand_data_rd.l3_hit.snoop_not_needed offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwd offcore_response.other.supplier_none.any_snoop offcore_response.other.supplier_none.snoop_hit_no_fwd offcore_response.pf_l2_data_rd.l3_hit.any_snoop offcore_response.pf_l2_data_rd.l3_hit.snoop_none offcore_response.pf_l3_code_rd.any_response offcore_response.pf_l3_code_rd.l3_hit.snoop_miss offcore_response.pf_l3_code_rd.supplier_none.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0080 offcore_response.pf_l3_data_rd.supplier_none.any_snoop offcore_response.pf_l3_data_rd.supplier_none.snoop_none Randomly selected loads with latency value being above 32 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000240 offcore_response.all_pf_data_rd.l3_miss.snoop_hit_no_fwd offcore_response.all_pf_rfo.l3_miss.snoop_miss offcore_response.all_pf_rfo.l3_miss.snoop_not_needed offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000002 offcore_response.pf_l3_rfo.supplier_none.snoop_non_dram offcore_response.all_code_rd.llc_hit.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 Counts all requests miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00002 (UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100. event=0x40,period=2000000,umask=0xa3 event=0x29,period=200000,umask=0x5f L2 cache lines evicted event=0x30,period=200000,umask=0x5f event=0x30,period=200000,umask=0x52 l2_rqsts.self.prefetch.i_state event=0x11,period=10000,umask=0x81 event=0x11,period=10000,umask=0x1 event=0xb1,period=2000000,umask=0x80 x87_comp_ops_exe.any.s misalign_mem_ref.st_bubble Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed bus_trans_inval.self bus_trans_mem.self event=0x6a,period=200000,umask=0xe0 RFO bus transactions bus_trans_wb.all_agents event=0x6,period=200000,umask=0x80 event=0xc4,period=2000000,umask=0x1 br_inst_type_retired.ret event=0xd1,period=200003,umask=0x2 Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs Supports address when precise (Must be precise) mem_uops_retired.all Load uops retired (Precise event capable) Supports address when precise (Must be precise) Counts the number of store uops retired Supports address when precise (Must be precise) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600003010 offcore_response.any_rfo.l2_hit Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hit_other_core_no_fwd offcore_response.sw_prefetch.l2_miss.hitm_other_core event=0xe6,period=200003,umask=0x1 event=0x80,period=200003,umask=0x3 ms_decoded.ms_entry Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time (Must be precise) Loads blocked because address has 4k partial address false dependence (Precise event capable) (Must be precise) Uops requested but not-delivered to the back-end per cycle event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000132b7 Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem Counts bus lock and split lock requests have any transaction responses from the uncore subsystem Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.outstanding Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.any_response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000002000 Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks event=0x48,period=2000003,umask=0x2 Counts any demand and L1 HW prefetch data load requests to L2 Spec update: HSD78, HSM80 All L2 requests Spec update: HSD78, HSM80 Retired store uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Counts all prefetch (that bring data to LLC only) data reads hit in the L3 Randomly selected loads with latency value being above 32 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400001 Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address Far branch instructions retired Number of far branches retired Number of near taken branches retired (Precise event) This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state Cycles with pending L2 cache miss loads Spec update: HSD78, HSM63, HSM80 Counts total number of uops to be executed per-core each cycle Spec update: HSD30, HSM31 L3 Lookup external snoop request that access cache and found line in E or S-state. Unit: uncore_cbox page_walker_loads.itlb_memory Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: HSD29, HSM30 (Precise event) offcore_response.pf_l2_code_rd.llc_hit.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x083FC00091 Not rejected writebacks from L1D to L2 cache lines in any state l2_rqsts.pf_miss Retired store uops that split across a cacheline boundary. (Precise Event) Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010002 Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s Cycles per thread when uops are dispatched to port 4 unc_cbo_cache_lookup.s event=0x34,umask=0x10 event=0x34,umask=0x80 Completed page walks in ITLB due to STLB load misses for large pages event=0xd3,period=100007,umask=0xc event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0080 offcore_response.all_code_rd.llc_miss.remote_dram Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there offcore_response.demand_data_rd.llc_miss.remote_hit_forward LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.uncacheable. Unit: uncore_cbox event=0x35,umask=0x1,filter_opc=0x195 llc_references.itom_write Write requests to home agent. Unit: uncore_ha (UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100. Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of times that the uncore transitioned to a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu event=0x51,period=2000003,umask=0x2 Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache Retired load uops that miss the STLB (Precise event) Speculative and retired mispredicted direct near calls event=0xc1,period=100003,umask=0x2 Resource stalls due to load or store buffers all being in use resource_stalls.ooo_rsrc Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu This event counts the number of load micro-ops retired event=0x4,period=200003,umask=0x2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800088000 Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180022 Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000080 offcore_response.partial_writes.l2_hit_this_tile_s Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.pf_l2_code_rd.l2_hit_near_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000020 offcore_response.pf_software.l2_hit_near_tile_m This event counts the number of times that the pipeline stalled due to FP operations needing assists Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local offcore_response.any_pf_l2.ddr_far offcore_response.any_read.ddr event=0xb7,period=100007,umask=0x1,offcore_rsp=0x01806032f7 offcore_response.bus_locks.mcdram Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400001 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600002 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000020 offcore_response.pf_l2_rfo.mcdram_far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200020 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080801000 offcore_response.uc_code_reads.ddr_far Counts the number of mispredicted branch instructions retired that were conditional jumps (Precise event) This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps no_alloc_cycles.all event=0xca,period=200003,umask=0x7f event=0xca,period=200003,umask=0x90 Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once uncore_edc_eclk event=0x51,period=2000000,umask=0x2 L1 data cacheable reads and writes event=0x40,period=2000000,umask=0x1 event=0x40,period=2000000,umask=0xf event=0x41,period=2000000,umask=0x2 event=0x4e,period=200000,umask=0x2 l1d_prefetch.requests L2 lines allocated in the E state L2 prefetch misses l2_write.lock.m_state offcore_response.any_ifetch.any_cache_dram offcore_response.any_ifetch.llc_hit_other_core_hitm offcore_response.any_ifetch.remote_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7FFF offcore_response.any_rfo.io_csr_mmio event=0xb7,period=100000,umask=0x1,offcore_rsp=0x408 Offcore writebacks to a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3877 offcore_response.data_in.remote_cache_hit offcore_response.demand_data_rd.remote_cache_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x404 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1004 offcore_response.demand_rfo.llc_hit_no_other_core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x202 offcore_response.demand_rfo.remote_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x780 offcore_response.pf_data.any_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x410 offcore_response.pf_ifetch.io_csr_mmio event=0xb7,period=100000,umask=0x1,offcore_rsp=0x120 event=0xf7,period=20000,umask=0x1 event=0xfd,period=200000,umask=0x40 offcore_response.data_ifetch.remote_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4033 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF802 Offcore prefetch data reads satisfied by the local DRAM Offcore prefetch code reads that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4020 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2020 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4070 event=0xb8,period=100000,umask=0x2 br_inst_exec.cond Reference cycles when thread is not halted (fixed counter) event=0x3c,period=100000,umask=0x1 Total CPU cycles Instructions retired (fixed counter) event=0xc0,period=2000000,umask=0x1 resource_stalls.load event=0xb1,any=1,period=2000000,umask=0x80 event=0xb1,any=1,period=2000000,umask=0x10 ITLB miss page walks mem_inst_retired.all_stores Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source Supports address when precise (Precise event) offcore_response.demand_code_rd.l3_hit.spl_hit offcore_response.demand_code_rd.l3_hit_m.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C0001 offcore_response.demand_data_rd.l3_hit_e.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040001 offcore_response.demand_data_rd.l3_hit_s.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C0002 offcore_response.demand_rfo.l3_hit_m.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100108000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0408000 offcore_response.other.l4_hit_local_l4.snoop_not_needed event=0xc6,period=100007,umask=0x1,frontend=0x200206 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ Cycles while L3 cache miss demand load is outstanding offcore_requests_outstanding.l3_miss_demand_data_rd offcore_response.demand_code_rd.l3_hit_m.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C400001 offcore_response.demand_data_rd.l3_miss_local_dram.spl_hit offcore_response.demand_rfo.l3_miss_local_dram.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000108000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84008000 Counts all (macro) branch instructions retired Spec update: SKL091 cpu_clk_unhalted.ring0_trans inst_retired.nop Number of uops delivered to the back-end by the LSD(Loop Stream Detector) Increments whenever there is an update to the LBR array event=0xc2,cmask=1,inv=1,period=2000003,umask=0x2 100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs) Fed;FetchBW;Frontend Fed;FetchBW;Frontend_SMT (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) DSB_Misses_Cost Loads that miss the DTLB and hit the STLB Counts demand reads of partial cache lines (including UC and WC) that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680002000 event=0xca,period=200003,umask=0x3f Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation I-side page-walks event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0240 Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400040 Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram offcore_response.pf_llc_rfo.llc_miss.dram offcore_requests.any.read offcore_requests_outstanding.demand.read_code event=0x60,period=2000000,umask=0x1 event=0x60,cmask=1,period=2000000,umask=0x4 REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1ff REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff02 REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM offcore_response.pf_data_rd.all_local_dram_and_remote_cache_hit REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS offcore_response.data_in.any_dram_and_remote_fwd REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD offcore_response.pf_data.any_dram_and_remote_fwd event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf820 REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5802 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2770 Retired loads that hit remote socket in modified state (Precise Event) event=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1f Counts all demand & prefetch data reads that have any response type offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0020 Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_data_rd.l3_miss.remote_hit_forward offcore_response.all_pf_rfo.l3_miss.remote_hit_forward offcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts prefetch (that bring data to L2) data reads that miss in the L3 Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram event=0x28,period=200003,umask=0x7 Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) 1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY cha@event\=0x36\,umask\=0x21\,config\=0x40433@ / cha@event\=0x36\,umask\=0x21\,config\=0x40433\,thresh\=1@ All DRAM CAS Commands issued. Unit: uncore_imc Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory write requests from local home agent. Unit: uncore_cha unc_iio_data_req_of_cpu.mem_write.part2 unc_cha_requests.invitoe_local Local requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha event=0x13,umask=0x01 unc_cha_sf_eviction.m_state event=0x5c,umask=0x08 PCIe Completion Buffer Inserts of completions with data: Part 1 PCIe Completion Buffer occupancy of completions with data: Part 0-3 event=0xd5,fc_mask=0x04,umask=0x01 event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x08 Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit. Unit: uncore_iio event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x08 Write request of up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio Cycles when direct to core mode (which bypasses the CHA) was disabled. Unit: uncore_m2m Cycles when direct to Intel UPI was disabled. Unit: uncore_m2m unc_m2m_directory_update.i2a event=0x37,umask=0x4 unc_m2m_imc_writes.ni unc_m2m_rxc_bl_inserts Cycles the Rx of the Intel UPI is in L0p power mode. Unit: uncore_upi Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency unc_upi_rxl_flits.non_data ocr.all_data_rd.l3_hit.snoop_hit_with_fwd OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200491 OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0490 ocr.all_pf_data_rd.l3_hit_f.hitm_other_core ocr.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_hit_s.any_snoop OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100120 OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS ocr.all_reads.l3_hit.no_snoop_needed OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200122 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE ocr.demand_data_rd.l3_hit.hit_other_core_fwd ocr.demand_rfo.l3_hit_s.hitm_other_core Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED ocr.other.l3_hit_s.snoop_miss Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080010 ocr.pf_l2_rfo.l3_hit.hitm_other_core ocr.pf_l2_rfo.l3_hit_e.snoop_none ocr.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080100 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP ocr.pf_l3_rfo.l3_hit_m.any_snoop ocr.pf_l3_rfo.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_not_needed offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd offcore_response.all_pf_data_rd.l3_hit_e.snoop_miss offcore_response.all_pf_data_rd.l3_hit_s.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020490 offcore_response.all_pf_rfo.l3_hit_f.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400120 offcore_response.all_reads.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F804007F7 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE offcore_response.all_rfo.l3_hit_e.hitm_other_core offcore_response.all_rfo.l3_hit_e.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020122 offcore_response.demand_code_rd.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.demand_rfo.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80408000 This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020020 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS offcore_response.pf_l3_rfo.l3_hit_s.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) ( ( 64 * imc@event\=0xe3@ / 1000000000 ) / duration_time ) ocr.all_data_rd.l3_miss.snoop_miss OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000491 OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss ocr.all_reads.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x900007F7 ocr.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.demand_code_rd.l3_miss_local_dram.snoop_miss ocr.demand_data_rd.l3_miss_local_dram.hitm_other_core Counts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_CORE Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000400 ocr.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_needed ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000020 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000020 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.all_data_rd.l3_miss_remote_hop1_dram.any_snoop offcore_response.all_pf_data_rd.l3_miss.hit_other_core_no_fwd offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.other.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_miss offcore_response.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS OCR.ALL_DATA_RD.ANY_RESPONSE have any response type OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED ocr.all_reads.any_response OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.demand_data_rd.pmm_hit_local_pmm.snoop_none ocr.demand_data_rd.supplier_none.hitm_other_core Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD ocr.demand_data_rd.supplier_none.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED ocr.pf_l2_rfo.supplier_none.snoop_none Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP ocr.pf_l3_rfo.supplier_none.snoop_miss unc_m_pmm_rpq_inserts Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_pmm_bandwidth.write Intel Optane DC persistent memory bandwidth write (MB/sec). Unit: uncore_imc All commands for Intel Optane DC persistent memory event=0xd3,umask=0x1 Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0002 ocr.demand_rfo.l3_hit.snoop_hit_no_fwd Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request ocr.streaming_wr.l3_hit.any Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) idq.dsb_cycles_any C10 residency percent per package event=0xc9,period=100003,umask=0x8 Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty event=0xc5,period=50021,umask=0x80 Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect (Precise event) event=0xc0,cmask=1,inv=1,period=1000003,umask=0x1 Counts end of periods where the Reservation Station (RS) was empty Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction uops_dispatched.port_0 Number of uops executed on port 6 1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED Cache lines that are evicted by L2 cache when triggered by an L2 cache fill event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1030000001 ocr.reads_to_core.remote_cache.snoop_hit_with_fwd ocr.demand_data_rd.l3_miss_local Counts demand data reads that were supplied by DRAM attached to another socket Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FFC0477 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x70C000477 2LM Tag Check : Write Hit in Near Memory Cache. Unit: uncore_imc event=0x36,umask=0xC001FE01 TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC. Unit: uncore_cha event=0x35,umask=0xC887FD01 TOR Inserts : CRDs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_crd TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.io_hit_itomcachenear Number requests PCIe makes of the main die : All. Unit: uncore_iio event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x01 unc_iio_txn_req_of_cpu.mem_read.part7 PCIe Completion Buffer Inserts of completions with data: Part 0-7. Unit: uncore_iio Tag Hit : Clean NearMem Read Hit. Unit: uncore_m2m uncore_m2pcie mem_bound_stalls.load mem_bound_stalls.load_llc_hit Counts the total number of load uops retired Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x201F803C0000 event=0xe6,period=200003,umask=0x2 Counts all code reads that were not supplied by the L3 cache ocr.full_streaming_wr.l3_miss_local event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000477 c0_stalls.load_dram_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000000010000 ocr.reads_to_core.outstanding Counts the number of unhalted core clock cycles. (Fixed event) Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears event=0x71,period=1000003,umask=0x8d Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wcilf TOR Inserts : WCiLF issued by iA Cores that Missed the LLC. Unit: uncore_cha Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 Counts the number of page walks completed due to store DTLB misses to a 1G page event=0x4f,period=2000003,umask=0x1 Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will results in a DTLB write from STLB Fraction of branches that are taken conditionals. Unit: cpu_core cpu_atom Percent of instruction miss cost that hit in the L2. Unit: cpu_atom Inst_Miss_Cost_L3Hit_Percent Counts the number of cycles that uops are blocked due to an RSV full condition. Unit: cpu_atom mem_uops_retired.load_latency_gt_512 Counts the number of stores uops retired. Counts with or without PEBS enabled (Precise event). Unit: cpu_atom Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires. Unit: cpu_atom Counts streaming stores that have any type of response. Unit: cpu_core Counts the number of machines clears due to memory renaming. Unit: cpu_atom event=0x75,period=200003,umask=0x2 Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops. Unit: cpu_atom Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls. Unit: cpu_atom int_vec_retired.shuffles event=0x3,period=100003,umask=0x4 Number of clocks. Unit: uncore_imc MEM_STORE_RETIRED.L2_HIT fp_arith_inst_retired2.complex_scalar_half event=0xcf,period=100003,umask=0x2 FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10004 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708000004 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104004477 Number of uops dispatch to execution ports 2, 3 and 10 unc_m_pmm_wpq_occupancy.all_sch1 DRAM Precharge commands. : Precharge due to (?). Unit: uncore_imc DRAM RD_CAS and WR_CAS Commands. Unit: uncore_imc unc_m_pre_count.wr_pch1 event=0x35,umask=0x00c817fe01 TOR Inserts for ItoM from local IO. Unit: uncore_cha event=0x36,umask=0x00c8177e01 RxQ Flit Buffer Allocations : Slot 1. Unit: uncore_upi event=0xc0,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000001 event=0x18,umask=0x03 event=0x20,umask=0x04 unc_m2m_tracker_occupancy.ch1 unc_m2m_prefcam_demand_drops.ch1_upi Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket. Unit: uncore_cha unc_cha_tor_inserts.loc_io event=0x35,umask=0x00c827fe01 TOR Occupancy; DRd hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_llcprefrfo event=0x36,umask=0x0000000010 unc_cha_tor_occupancy.rrq unc_cha_tor_occupancy.hit TOR Occupancy : Just ISOC. Unit: uncore_cha TOR Occupancy; RFO Pref hits from local IA. Unit: uncore_cha event=0x36,umask=0x00c8f3fe04 unc_cha_tor_inserts.ia_miss_remote_wcilf_ddr event=0x35,umask=0x00C86F8601 event=0x35,umask=0x00C86F0601 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_wcil l2_request_g2.group1 event=0x64,umask=0x01 L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3 Retired Taken Branch Instructions Mispredicted SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) Total number multi-pipe uOps assigned to pipe 3 fpu_pipe_assignment.dual0 event=0,umask=0x08 event=0x4,umask=0x04 The number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits event=0x5,umask=0x04 L1 DTLB Reload of a page of 32K size event=0x46,umask=0x03 OC Mode Switch. IC to OC mode switch l3_cache Micro-ops Retired nps1_die_to_dram Multiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.div_flops Floating Point Dispatch Faults. x87 fill fault ls_st_commit_cancel2.st_commit_cancel_wcb_full Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP scheduler resource stall. Applies to ops that use the FP scheduler event=0xae,umask=0x02 event=0xcc The number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatch ls_dmnd_fills_from_sys.mem_io_remote ls_dmnd_fills_from_sys.ext_cache_local Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the core Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Insufficient Retire Queue tokens available Retired unconditional indirect branch instructions mispredicted event=0x5a,umask=0xdf L2 cache requests: data cache shared reads event=0x60,umask=0xff Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2 event=0x70,umask=0x20 L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache cache of all types l3_lookup_state.l3_hit event=0xac,umask=0x01 l3_xi_sampled_latency.ext_far L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node. Unit: amd_l3 ex_no_retire.thread_not_selected Write data beats (64 bytes) for local processor at Coherent Station (CS) 11 event=0x15f,umask=0xbfe remote_processor_read_data_beats_cs10 remote_socket_upstream_read_beats_iom3 local_socket_inf0_outbound_data_beats_ccm0 event=0x49e,umask=0xbfe event=0x51e,umask=0xbfe event=0x59f,umask=0xbfe Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 4 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 6 event=0x3,umask=0x1f Retired x87 bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing event=0xa,umask=0x03 Retired vector floating-point logical ops fp_ops_retired_by_type.all Retired 128-bit packed floating-point compare ops event=0xc,umask=0x0d fp_pack_ops_retired.fp256_add event=0xc,umask=0x60 Retired 128-bit packed integer SHA ops Retired 256-bit packed integer shift ops Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages Fraction of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth) frontend_bound_bandwidth retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops) local_socket_inbound_data_to_cpu remote_socket_inf0_outbound_data_beats_ccm0 + remote_socket_inf1_outbound_data_beats_ccm0 + remote_socket_inf0_outbound_data_beats_ccm1 + remote_socket_inf1_outbound_data_beats_ccm1 + remote_socket_inf0_outbound_data_beats_ccm2 + remote_socket_inf1_outbound_data_beats_ccm2 + remote_socket_inf0_outbound_data_beats_ccm3 + remote_socket_inf1_outbound_data_beats_ccm3 + remote_socket_inf0_outbound_data_beats_ccm4 + remote_socket_inf1_outbound_data_beats_ccm4 + remote_socket_inf0_outbound_data_beats_ccm5 + remote_socket_inf1_outbound_data_beats_ccm5 + remote_socket_inf0_outbound_data_beats_ccm6 + remote_socket_inf1_outbound_data_beats_ccm6 + remote_socket_inf0_outbound_data_beats_ccm7 + remote_socket_inf1_outbound_data_beats_ccm7 d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all) (umc_cas_cmd.all * 64) / 1e6 / duration_time DDRC write commands. Unit: hisi_sccl,ddrc uncore_imc_free_running RET_STACK_MISPREDICT EVENT_12H EVENT_14H EVENT_23H EVENT_39H EVENT_61H EVENT_6BH EVENT_79H EVENT_A1H EVENT_D1H EVENT_E9H JAZELLE_BACKWARD_BRANCH ISSUE_IS_EMPTY MAIN_EXECUTION_UNIT_PIPE CID_WRITE_RETIRED MEMORY_ERROR ST_RETIRED EVENT_147H EVENT_1B1H EVENT_1B6H EVENT_1B9H EVENT_203H EVENT_217H EVENT_218H EVENT_229H EVENT_250H EVENT_2A1H EVENT_2A3H EVENT_2C6H EVENT_2C8H EVENT_2FAH EVENT_312H EVENT_33FH EVENT_36AH EVENT_37AH EVENT_389H EVENT_3A3H EVENT_3E3H EVENT_3F0H BR_RETURN_SPEC L2D_CACHE_ALLOCATE L3_CACHE_RD hnf_sfbi_brd_snp_sent hnf_stash_data_pull hni_arready_no_arvalid rni_wrcancel_sent cxra_req_pcrd_stalls_lnk2 cxra_ext_dat_stall clkdiv2_bk_fsm_tracker clk_request MTVSCR_INSTR_COMPLETED MTVRSAVE_INSTR_COMPLETED LOAD_MISS_ALIAS L1_DATA_TOUCH_HIT L1_DATA_STORE_HIT LSU_LMQ_INDEX_ALIAS DISPATCHES_TO_FPR_ISSUE_QUEUE L1_DATA_TOUCH_MISS SWITCHES_BETWEEN_PRIV_USER VR_ISSUE_QUEUE_DISPATCHES L2_DATA_CACHE_MISSES PREFETCH_ENGINE_COLLISION_VS_STORE GCT_EMPTY_BY_SRQ_FULL MARKED_STORE_WITH_INTR FXU0_BUSY_FXU1_IDLE DATA_MMU_TLB4K_RELOADS BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS DVT7_DETECTED FPU_FPSCR_FULL_STALL SYSTEM ARMV7_CORTEX_A17 DELETED pmc_pmu_event_get_by_idx metric_name: %s
LLC-MISS-RHITM GenuineIntel-6-5F GenuineIntel-6-57 v2 NO_NMI_WATCHDOG Instructions Per Cycle across hyper-threads (per physical core) Instructions per Branch (lower number means higher occurrence rate) DSB_Coverage 64 * L1D.REPLACEMENT / 1000000000 / duration_time Mem;CacheMisses Socket actual clocks when any core is active on that socket event=0x48,period=2000003,umask=0x1 l2_rqsts.all_demand_data_rd event=0x24,period=200003,umask=0x42 event=0xd2,period=100003,umask=0x8 Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) event=0xd0,period=100007,umask=0x21 Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0xc7,period=2000004,umask=0x3c event=0xc7,period=2000003,umask=0x2 This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid idq.all_mite_cycles_4_uops Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path idq.ms_dsb_cycles idq.ms_dsb_uops idq_uops_not_delivered.cycles_le_3_uop_deliv.core Number of times HLE abort was triggered (PEBS) (Precise event) Number of times a disallowed operation caused an HLE abort event=0xc8,period=2000003,umask=0x1 machine_clears.memory_ordering Counts the number of machine clears due to memory order conflicts cpl_cycles.ring123 event=0x63,period=2000003,umask=0x1 number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired cycle_activity.stalls_l1d_miss cycle_activity.stalls_l1d_pending This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread event=0xa8,period=2000003,umask=0x1 This event counts both thread-specific (TS) and all-thread (AT) nukes Cycles when Reservation Station (RS) is empty for the thread Cycles per thread when uops are executed in port 4 event=0xb1,period=2000003,umask=0x2 uops_executed.cycles_ge_2_uops_exec event=0xb1,cmask=2,period=2000003,umask=0x1 uops_executed_port.port_6_core uops_executed_port.port_7 uops_issued.slow_lea Retirement slots used. (Precise Event - PEBS) (Precise event) This event counts cycles without actually retired uops unc_c_clockticks uncore memory uncore_imc event=0x8,period=100003,umask=0x1 virtual memory dtlb_store_misses.stlb_hit Store misses that miss the DTLB and hit the STLB (2M) Store miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 itlb_misses.stlb_hit_2m event=0xbc,period=2000003,umask=0x18 bdw metrics Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020091 offcore_response.all_pf_rfo.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0004 offcore_response.pf_l2_code_rd.l3_hit.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020040 offcore_response.pf_l2_code_rd.supplier_none.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020010 Counts all prefetch (that bring data to L2) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0020 offcore_response.pf_l3_code_rd.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0100 offcore_response.all_data_rd.l3_hit.snoop_non_dram offcore_response.all_rfo.l3_miss_local_dram.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C8000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0040 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000010 offcore_response.pf_l3_data_rd.l3_miss.snoop_none offcore_response.pf_l3_data_rd.l3_miss.snoop_not_needed offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hit_no_fwd event=0x3c,any=1,period=100003,umask=0x1 unc_cbo_cache_lookup.any_es L3 Lookup write request that access cache and found line in E or S-state. Unit: uncore_cbox Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic. Unit: uncore_arb Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0x14 l2_ifetch.self.i_state l2_lines_in.self.prefetch l2_st.self.mesi simd_inst_retired.packed_single SIMD packed arithmetic micro-ops retired event=0xb3,period=2000000,umask=0x90 event=0x7a,period=200000,umask=0x0 All bus transactions bus_trans_any.self event=0xc6,period=2000000,umask=0x1 event=0x77,period=200000,umask=0x22 snoop_stall_drv.all_agents Number of thermal trips Good store forwards event=0xc,period=200000,umask=0x1 Requests rejected by the L2Q event=0xd1,period=200003,umask=0x1 Load uops retired that missed L2 (Precise event capable) Supports address when precise (Must be precise) Counts load uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) offcore_response.any_pf_data_rd.l2_miss.hitm_other_core event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000022 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040008 Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module offcore_response.demand_data_rd.l2_miss.any Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040002 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.hitm_other_core Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache offcore_response.pf_l2_rfo.l2_miss.hitm_other_core Cycles the FP divide unit is busy Counts when a memory load of a uop spans a page boundary (a split) is retired (Must be precise) Cycles code-fetch stalled due to an outstanding ITLB miss br_misp_retired.non_return_ind br_misp_retired.return Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue Duration of I-side pagewalks in cycles Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received offcore_response.any_read.outstanding Counts requests to the uncore subsystem hit the L2 cache Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xc3,period=20003,umask=0x20 ept.walk_pending Any MLC or L3 HW prefetch accessing L2, including rejects Demand Data Read requests sent to uncore Spec update: HSD78, HSM80 Cycles with any input/output SSE* or FP assists icache.ifetch_stall Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled Spec update: HSD135 Cycles with less than 3 uops delivered by the front end Spec update: HSD135 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00091 Counts all demand code reads miss the L3 and the data is returned from local dram Cycles in which the L1D and L2 are locked, due to a UC lock or split lock This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling Cycles with pending memory loads Cycles where at least 1 uop was executed per-thread Spec update: HSD144, HSD30, HSM31 event=0xc2,any=1,cmask=1,inv=1,period=2000003,umask=0x1 An external snoop hits a non-modified line in some processor core. Unit: uncore_cbox page_walker_loads.ept_dtlb_memory event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0091 Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Decode Stream Buffer (DSB)-to-MITE switches dsb_fill.exceed_dsb_lines ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD event=0xcd,period=2000003,umask=0x2 offcore_response.all_code_rd.llc_miss.dram event=0xbe,period=100003,umask=0x1 Cycles with pending memory loads. Set AnyThread to count per core event=0x85,period=100003,umask=0x80 Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response offcore_response.demand_code_rd.llc_miss.remote_dram offcore_response.demand_code_rd.llc_miss.remote_hitm Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram llc_references.pcie_partial_read event=0xd Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu event=0xc Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu event=0x7 event=0x51,period=2000003,umask=0x8 Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports Data from remote DRAM either Snoop not needed or Snoop Miss (RspI) offcore_requests_outstanding.demand_data_rd_c6 event=0x9c,cmask=4,inv=1,period=2000003,umask=0x1 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x187FC20077 event=0x5e,cmask=1,edge=1,inv=1,period=2000003,umask=0x1 Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu l2_requests.reference Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400070 offcore_response.any_pf_l2.outstanding offcore_response.any_read.l2_hit_near_tile_m Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state Counts Demand cacheable data writes that accounts for any response offcore_response.partial_writes.l2_hit_far_tile offcore_response.partial_writes.l2_hit_near_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000100 Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400020 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010200 This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt offcore_response.any_code_rd.ddr_near Counts any Read request that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200400 offcore_response.demand_data_rd.ddr Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far) Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far) offcore_response.partial_reads.mcdram_near offcore_response.pf_l2_rfo.ddr_near Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local offcore_response.pf_software.ddr_near Counts the number of near CALL branch instructions retired (Precise event) Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP (Precise event) This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides event=0x3,period=200003,umask=0x80 recycleq.lock event=0x63,period=2000000,umask=0x2 l1d_cache_ld.s_state L1D prefetch load lock accepted in fill buffer event=0xf2,period=100000,umask=0x4 event=0xf2,period=100000,umask=0x8 event=0x24,period=200000,umask=0x80 L2 demand store RFOs in S state event=0xb,period=5,umask=0x10,ldlat=0x4000 Memory instructions retired above 4096 clocks (Precise Event) Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event) offcore_requests_sq_full offcore_response.any_data.remote_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7FF All offcore RFO requests offcore_response.corewb.remote_cache_hit All offcore code or data read requests Offcore code or data read requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF03 Offcore demand data requests satisfied by a remote cache offcore_response.demand_data_rd.any_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4701 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1801 offcore_response.demand_rfo.remote_cache_hitm All offcore other requests Offcore other requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF10 offcore_response.pf_data_rd.llc_hit_no_other_core offcore_response.pf_ifetch.llc_hit_other_core_hitm Offcore prefetch code reads satisfied by the LLC Offcore prefetch code reads that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1020 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x270 offcore_response.prefetch.local_cache_dram Loads delayed with at-Retirement block code two_uop_insts_decoded Offcore demand code reads satisfied by any DRAM event=0x80,period=2000000,umask=0x1 L1I Instruction fetches snoop_response.hitm Unconditional branches executed event=0x89,period=2000,umask=0x10 lsd.inactive uops_decoded.ms_cycles_active uops_executed.core_stall_count_no_port5 event=0xb1,period=2000000,umask=0x2 uops_executed.port234_core Uops issued event=0xc2,period=2000000,umask=0x4 uop_unfusion DTLB second level hit ITLB miss offcore_response.demand_data_rd.l3_hit_m.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000001 rtm_retired.aborted_mem Direct and indirect near call instructions retired Spec update: SKL091 (Precise event) Mispredicted direct and indirect near call instructions retired (Precise event) Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0 Memory_Bandwidth Mem;MemoryLat;Offcore_SMT 100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * CPU_CLK_UNHALTED.THREAD)) 100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS Average number of Uops issued by front-end when it issued something Fraction of branches that are CALL or RET 1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY Code miss in all TLB levels causes a page walk that completes. (1G) Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000044 Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response This event counts the number of load uops reissued from Rehabq rehabq.st_splits Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count This event counts the number of times that pipeline was cleared due to memory ordering issues Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF MSROM micro-ops retired Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) (Precise event) This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS) (Precise event) Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.pf_llc_code_rd.llc_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0200 offcore_response.pf_llc_code_rd.llc_hit.no_snoop_needed event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff44 offcore_response.demand_data_rd.all_local_dram_and_remote_cache_hit REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3077 REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM offcore_response.pf_data_rd.other_local_dram REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM event=0xb4,period=100000,umask=0x1 Snoop invalidate requests snoopq_requests_outstanding.code_not_empty event=0xc5,period=20000,umask=0x1 Mispredicted conditional retired branches (Precise Event) Offcore data reads, RFOs, and prefetches satisfied by the local DRAM Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001 Counts all demand data writes (RFOs) that hit in the L3 Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded fp_arith_inst_retired.512b_packed_double event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00122 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00010 offcore_response.pf_l2_rfo.l3_miss.any_snoop L2_Evictions_Silent_PKI CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.THREAD ( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 ) * 4 / 1000000000 / duration_time event=0x35,umask=0x21,config1=0x41833 event=0x50,umask=0x0C UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data. Unit: uncore_upi PCI Express bandwidth reading at IIO, part 1. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part1 PCI Express bandwidth writing at IIO, part 1. Unit: uncore_iio unc_cha_dir_update.tor event=0x54,umask=0x02 Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA PCIe Completion Buffer occupancy of completions with data: Part 0-3. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_read.part0 unc_iio_data_req_by_cpu.mem_write.part3 Write request of 4 bytes made to IIO Part3 by the CPU. Unit: uncore_iio unc_iio_data_req_by_cpu.peer_write.part0 Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target. Unit: uncore_iio Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit. Unit: uncore_iio event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x04 unc_iio_txn_req_of_cpu.mem_write.part0 Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio event=0x18 event=0x11,umask=0x8 Number of reads in which direct to Intel UPI transactions were overridden. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket event=0x38,umask=0x80 FLITs that bypassed the TxL Buffer. Unit: uncore_upi mem_load_l3_miss_retired.remote_pmm ocr.all_data_rd.l3_hit.hit_other_core_fwd OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE ocr.all_data_rd.l3_hit_e.any_snoop ocr.all_data_rd.l3_hit_e.no_snoop_needed OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE ocr.all_data_rd.l3_hit_m.hitm_other_core OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200490 OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_hit_m.hitm_other_core OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C07F7 ocr.all_reads.l3_hit_e.hit_other_core_fwd ocr.all_rfo.l3_hit.any_snoop ocr.all_rfo.l3_hit_e.snoop_miss ocr.all_rfo.l3_hit_f.snoop_none ocr.all_rfo.l3_hit_s.hitm_other_core ocr.all_rfo.l3_hit_s.snoop_none ocr.demand_code_rd.l3_hit.any_snoop ocr.demand_code_rd.l3_hit.no_snoop_needed ocr.demand_data_rd.l3_hit_f.any_snoop Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit_f.snoop_none ocr.demand_data_rd.l3_hit_s.any_snoop Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200002 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP ocr.demand_rfo.l3_hit_m.snoop_miss ocr.other.l3_hit_e.hit_other_core_fwd ocr.other.l3_hit_f.snoop_none ocr.other.l3_hit_m.hitm_other_core ocr.other.l3_hit_s.hitm_other_core Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200400 Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.l3_hit.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_hit_m.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200080 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_e.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200100 ocr.pf_l3_rfo.l3_hit_f.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020491 offcore_response.all_pf_data_rd.l3_hit_e.any_snoop offcore_response.all_pf_data_rd.l3_hit_e.snoop_none offcore_response.all_pf_data_rd.l3_hit_m.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_reads.l3_hit.snoop_miss This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE offcore_response.all_reads.supplier_none.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800207F7 offcore_response.all_rfo.l3_hit_e.hit_other_core_no_fwd offcore_response.all_rfo.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE offcore_response.all_rfo.l3_hit_m.snoop_miss offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed offcore_response.demand_code_rd.supplier_none.hitm_other_core offcore_response.demand_code_rd.supplier_none.hit_other_core_fwd offcore_response.demand_data_rd.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.demand_rfo.l3_hit_e.no_snoop_needed offcore_response.demand_rfo.l3_hit_f.no_snoop_needed offcore_response.demand_rfo.l3_hit_s.hitm_other_core offcore_response.demand_rfo.l3_hit_s.no_snoop_needed offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd offcore_response.pf_l2_data_rd.l3_hit_m.no_snoop_needed offcore_response.pf_l2_data_rd.l3_hit_s.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_hit_e.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD LSD_Coverage event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000491 OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP ocr.all_pf_data_rd.l3_miss.snoop_none ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000490 ocr.all_pf_rfo.l3_miss.snoop_none ocr.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8040007F7 ocr.all_rfo.l3_miss.hitm_other_core OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000002 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000002 Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604008000 ocr.other.l3_miss_remote_hop1_dram.snoop_none ocr.pf_l1d_and_sw.l3_miss.snoop_miss ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_none ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000010 Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.pf_l3_data_rd.l3_miss_local_dram.any_snoop ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000080 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.demand_data_rd.l3_miss.hit_other_core_fwd offcore_response.other.l3_miss.remote_hitm This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE offcore_response.pf_l3_rfo.l3_miss.hitm_other_core OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP ocr.all_pf_data_rd.any_response ocr.all_pf_data_rd.supplier_none.hitm_other_core OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE OCR.ALL_READS.ANY_RESPONSE have any response type ocr.all_reads.supplier_none.snoop_miss OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.any_response ocr.pf_l1d_and_sw.supplier_none.snoop_none event=0xd3,umask=0x2 UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 l1d_pend_miss.fb_full_periods event=0x48,period=1000003,umask=0x1 Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache event=0x24,period=200003,umask=0x28 Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_no_fwd DSB-to-MITE switch true penalty cycles idq.dsb_cycles_ok Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) event=0xc8,period=100003,umask=0x1 event=0x54,period=100003,umask=0x1 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000400 Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) br_misp_retired.cond_taken Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event) Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000001 ocr.reads_to_core.remote_cache.snoop_fwd Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FC00002 ocr.itom.l3_miss_local event=0xef,period=1000003,umask=0x40 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000001 DRAM Precharge commands. : Precharge due to page table. Unit: uncore_imc unc_m_pre_count.all DRAM Precharge commands. Unit: uncore_imc Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent. Unit: uncore_cha TOR Occupancy : All requests from iA Cores that Hit the LLC. Unit: uncore_cha TOR Occupancy : All requests from iA Cores that Missed the LLC. Unit: uncore_cha event=0x36,umask=0xC001FD04 event=0x35,umask=0xC88FFE01 unc_cha_tor_inserts.ia_miss_drd_pref_remote TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_partial_streaming_wr event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x80 event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x80 unc_iio_clockticks_freerun event=0xd5,fc_mask=0x04,umask=0x20 PCIe Completion Buffer Occupancy of completions with data : Part 3. Unit: uncore_iio Misc Events - Set 1 : Lost Forward. Unit: uncore_irp event=0x2d,umask=0x02 Clockticks of the mesh to memory (M2M). Unit: uncore_m2m l2_request.all Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM) mem_bound_stalls.ifetch_llc_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0044 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0001 Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache ocr.uc_rd.l3_miss bus_lock.self_locks event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000044 ocr.demand_data_and_l1pf_rd.any_response This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800000010000 Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check (Precise event) Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions topdown_fe_bound.all Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS) TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : All requests from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 FAF RF full Counts the number of Extended Page Directory Entry misses Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Unit: cpu_core L2 cache misses per kilo instruction for all request types (including speculative). Unit: cpu_core CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY Percentage of total non-speculative loads with a address aliasing block. Unit: cpu_atom Estimated_Pause_Cost Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache. Unit: cpu_atom Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M. Unit: cpu_atom mem_scheduler_block.all Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise). Unit: cpu_atom L2 code requests. Unit: cpu_core Demand Data Read requests. Unit: cpu_core All L2 requests.[This event is alias to L2_REQUEST.ALL]. Unit: cpu_core RFO requests that hit L2 cache. Unit: cpu_core All retired store instructions Supports address when precise (Precise event). Unit: cpu_core Demand and prefetch data reads. Unit: cpu_core Stalls caused by changing prefix length of the instruction. Unit: cpu_core Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match when load subsequently retires. Unit: cpu_atom event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001 Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS). Unit: cpu_atom Not taken branch instructions retired (Precise event). Unit: cpu_core Core cycles the allocator was stalled due to recovery from earlier clear event for this thread. Unit: cpu_core event=0xad,period=1000003,umask=0x10 event=0xe7,period=1000003,umask=0xc event=0xe7,period=1000003,umask=0x80 int_vec_retired.vnni_128 TMA slots wasted due to incorrect speculation by branch mispredictions. Unit: cpu_core event=0xb2,period=2000003,umask=0x10 incoming write request page status is Page Empty. Unit: uncore_imc Counts the number of page walks completed due to store DTLB misses to any page size. Unit: cpu_atom All L2 requests.[This event is alias to L2_RQSTS.REFERENCES] event=0x2a,period=100003,umask=0x1,offcore_rsp=0x830000001 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808000002 Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex MEMORY_ACTIVITY.STALLS_L3_MISS event=0x2a,period=100003,umask=0x1,offcore_rsp=0x94000800 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104000001 AMX_OPS_RETIRED.INT8 This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE Miss-predicted near indirect branch instructions retired (excluding returns) (Precise event) INST_RETIRED.REP_ITERATION unc_m_pmm_rpq_occupancy.all_sch0 unc_m_pmm_wpq_occupancy.all_sch0 event=0x3,umask=0x0000000010 unc_m_cas_count.pch0 event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000002 unc_upi_rxl_occupancy.slot0 event=0xc1,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000001 event=0xc1,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000004 event=0xc2,ch_mask=0x02,fc_mask=0x07,umask=0x0000000004 event=0x35,umask=0x00c001fe04 event=0x35,umask=0x00cc43fe04 event=0x35,umask=0x00C001FFC8 event=0x35,umask=0x00c807ff01 event=0x36,umask=0x00c001fe01 TOR Occupancy; Misses from local IO. Unit: uncore_cha event=0x36,umask=0x00c803fe04 event=0x36,umask=0x0000000002 event=0x37,umask=0x0000000002 TOR Inserts; LLCPrefCode hits from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_llcprefcode event=0x36,umask=0x00cccfff01 event=0x35,umask=0x00c8170a01 event=0x35,umask=0x00c8170601 unc_cha_tor_inserts.io_clflush event=0x36,umask=0x00c8968601 unc_cha_tor_occupancy.ia_miss_crd_local TOR Occupancy : CLFlushOpts issued by iA Cores. Unit: uncore_cha event=0x36,umask=0x00cc27ff01 unc_cha_tor_occupancy.ia_miss_ucrdf L1 BTB Correction All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch) All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4 event=0xc3 Retired Conditional Branch Instructions event=0xd3 fp_retx87_fp_ops.all Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision divide/square root FLOPS fp_num_mov_elim_scal_op.sse_mov_ops_elim event=0x45,umask=0xff ls_tablewalker.dside ls_pref_instr_disp.prefetch_nta Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2 ls_inef_sw_pref.mab_mch_cnt event=0xaf,umask=0x08 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailable 1core clocks Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason Number of SMIs received event=0x2d All L1 DTLB Misses or Reloads L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB ls_hw_pf_dc_fill.ls_mabresp_rmt_dram de_dis_uop_queue_empty_di0 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semantics event=0x18e,umask=0x18 Software Prefetch Data Cache Fills by Data Source. From Local L2 to the core Hardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX Count of Allocated Mabs de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall de_dis_dispatch_token_stalls2.int_sch0_token_stall Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 0 available all_data_cache_accesses L1 Data Cache Fills: From External CCX Cache Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket) ls_any_fills_from_sys.all event=0x59,umask=0x80 event=0x70,umask=0x02 event=0x72,umask=0x04 l2_pf_miss_l2_l3.all event=0x15f,umask=0x7fe local_processor_write_data_beats_cs8 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 1 remote_processor_read_data_beats_cs3 remote_processor_read_data_beats_cs7 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 10 remote_processor_write_data_beats_cs3 event=0x81f,umask=0x7fe Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0 event=0x85f,umask=0x7ff event=0x85f,umask=0xbfe Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 7 event=0x51f,umask=0x7ff remote_socket_inf0_inbound_data_beats_ccm6 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 7 remote_socket_inf0_outbound_data_beats_ccm0 remote_socket_inf1_outbound_data_beats_ccm0 Retired scalar floating-point add ops Retired scalar floating-point multiply-accumulate ops Retired scalar floating-point compare ops event=0xa,umask=0x0e Retired vector floating-point subtract ops Retired MMX integer multiply ops sse_avx_ops_retired.mmx_mac sse_avx_ops_retired.sse_avx_add Retired SSE and AVX integer CLM ops Retired SSE and AVX integer shift ops fp_pack_ops_retired.fp128_mul Retired 256-bit packed floating-point multiply-accumulate ops event=0xc,umask=0x80 Retired 256-bit packed integer multiply-accumulate ops umc_act_cmd.wr 4kB misaligned (page crossing) loads Number of cycles dispatch is stalled for integer scheduler queue 1 tokens PipelineL2;backend_bound_group retiring_microcode Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit l1_dcache L1 data cache fills from within the same CCX L1 instruction TLB misses dram_read_data_for_remote_processor 3.0517578125e-5MiB memory_controller UNC_CBO_HYPHEN. Unit: uncore_cbox FR_RETIRED_TAKEN_BRANCHES FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING ITLB_REFILL EXC_EXECUTED AXI_WRITE MEM_UNALIGNED_ACCESS_REPLAY EVENT_24H EVENT_2CH EVENT_5FH EVENT_69H EVENT_75H EVENT_7AH EVENT_B6H EVENT_E3H EVENT_131H EVENT_17CH EVENT_182H EVENT_1A8H EVENT_1C9H EVENT_1D5H EVENT_230H EVENT_23BH EVENT_245H EVENT_26FH EVENT_270H EVENT_273H EVENT_2A7H EVENT_2BBH EVENT_2C1H EVENT_2CBH EVENT_2DAH EVENT_2DCH EVENT_332H EVENT_33BH EVENT_371H EVENT_378H EVENT_387H EVENT_3AFH EVENT_3C2H EVENT_3C8H EVENT_3D0H EVENT_3D7H L1D_CACHE_LD EXC_TRAP_OTHER RC_ST_SPEC hnf_cache_fill hnf_intv_dirty hni_nonpcie_serialization cxha_snppcrd_lnk0_stall TRUE_BRANCH_TARGET_HITS L1_DATA_SNOOP_HITS L1_DATA_LOAD_HIT FP_STORE_INSTR_COMPLETED_IN_LSU LSU_INDEXED_ALIAS_STALL LWARX_INSTR_COMPLETED L1_DATA_CACHE_RELOADS SYNC_INSTR_COMPLETED DST_STREAM_3_CACHE_LINE_FETCHES EXTERNAL_SNOOP_RETRY GROUP_MARKED_IDU PM_EVENT_TRANSITIONS LOAD_GUARDED_MISS_CYCLES PART2_MISALIGNED_CACHE_ACCESS_CYCLES L2MMU_MISSES STWCX_SUCCESSES multiply-pipe-excluding-junk-ops shared memory-controller-hi-pri-bypass QUALIFIER K7 BRANCH-INSTRUCTION-RETIRED LONGEST_LAT_CACHE.REFERENCE br_inst_retired.all_branches regex '%s' failed to compile, ignoring
%s, "tid": "%d"}
GenuineIntel-6-3C v24 v13 1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) ) UPI UpTB ILP Branch instructions per taken branch 1000 * L2_RQSTS.MISS / INST_RETIRED.ANY GFLOPs 1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0 Cycles Per Instruction for the Operating System (OS) Kernel mode Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches This event counts duration of L1D miss outstanding in cycles l2_rqsts.rfo_hit RFO requests that hit L2 cache RFO requests that miss L2 cache event=0xf0,period=200003,umask=0x8 l2_trans.rfo Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100, BDE70 (Precise event) event=0x60,period=2000003,umask=0x2 Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ? event=0xc7,period=2000003,umask=0x3 event=0xc7,period=2000005,umask=0x2a Number of SIMD Move Elimination candidate uops that were not eliminated event=0x80,period=200003,umask=0x2 This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ event=0xc8,period=2000003,umask=0x10 hle_retired.aborted_misc5 br_inst_exec.all_branches This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches This event counts taken speculative and retired indirect branches that have a return mnemonic event=0xc5,period=400009,umask=0x20 cpu_clk_thread_unhalted.ref_xclk_any event=0xa3,cmask=1,period=2000003,umask=0x1 inst_retired.prec_dist event=0xc0,period=2000003,umask=0x1 event=0x7,period=100003,umask=0x1 load_hit_pre.sw_pf event=0xc1,period=100003,umask=0x40 Cycles per thread when uops are executed in port 3 event=0xe,period=2000003,umask=0x40 This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight Supports address when precise (Precise event) Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event event=0x35,umask=0x3,filter_opc=0x18f,filter_nc=1 event=0x35,umask=0x1,filter_opc=0x181 L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox event=0x35,umask=0x1,filter_opc=0x18c event=0x1,umask=0xC unc_p_prochot_external_cycles event=0x85,period=100003,umask=0x60 Core misses that miss the DTLB and hit the STLB (4K) event=0xbc,period=2000003,umask=0x24 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020091 offcore_response.all_data_rd.supplier_none.snoop_miss offcore_response.all_pf_code_rd.l3_hit.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010040 offcore_response.pf_l2_data_rd.supplier_none.snoop_hitm offcore_response.pf_l3_code_rd.supplier_none.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020200 Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element offcore_response.all_data_rd.l3_miss_local_dram.snoop_none offcore_response.corewb.l3_miss.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000004 offcore_response.demand_data_rd.supplier_none.snoop_non_dram offcore_response.other.l3_miss.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C008000 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000100 This event counts taken branch instructions retired (Precise event) unc_cbo_cache_lookup.any_mesi L3 Lookup write request that access cache and found line in E or S-state unc_arb_trk_requests.drd_direct Number of Writes allocated - any write transactions: full/partials writes and evictions ( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * CPU_CLK_UNHALTED.THREAD ) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00100 l1d_cache.ld event=0x28,period=200000,umask=0x44 event=0x28,period=200000,umask=0x48 l2_ld.self.demand.m_state event=0x24,period=200000,umask=0x70 event=0x30,period=200000,umask=0x74 L2 store requests event=0x2a,period=200000,umask=0x4f event=0x2a,period=200000,umask=0x48 Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions event=0xc7,period=2000000,umask=0x10 event=0xb1,period=2000000,umask=0x0 Icache miss uops.ms_cycles event=0x5,period=200000,umask=0x97 event=0x5,period=200000,umask=0x9 misalign_mem_ref.st_split prefetch.software_prefetch.ar event=0x68,period=200000,umask=0x40 cycles_div_busy event=0xdc,period=2000000,umask=0x2 All store forwards event=0x82,period=200000,umask=0x2 event=0xcb,period=200000,umask=0x4 page_walks.i_side_cycles Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.l2_hit Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000004 Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_data_rd.outstanding Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Store uops that split a page (Precise event capable) (Must be precise) Retired near call instructions (Precise event capable) (Must be precise) Counts near indirect CALL branch instructions retired (Must be precise) event=0xc4,period=200003,umask=0xfd Store uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) offcore_response.any_read.any_response Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000001000 Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0x49,period=2000003,umask=0x2 Number of instruction fetches that hit the L2 cache Number of instruction fetches that missed the L2 cache This event counts requests originating from the core that reference a cache line in the last level cache Number of SIMD FP assists due to output values Number of front end re-steers due to BPU misprediction Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles offcore_response.all_reads.l3_miss.any_response Counts the number of conditional branch instructions retired (Precise event) Reference cycles when the thread is unhalted. (counts at 100 MHz rate) unc_cbo_xsnp_response.miss_external Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC. Unit: uncore_arb ITLB misses that hit STLB (2M) This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses event=0xbc,period=2000003,umask=0x82 offcore_response.demand_data_rd.llc_miss.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00080 event=0x24,period=200003,umask=0x1 Counts all demand & prefetch prefetch RFOs Counts number of X87 uops executed offcore_response.demand_code_rd.llc_miss.dram uops_dispatched_port.port_1_core Cycles per thread when uops are dispatched to port 5 A snoop misses in some processor core. Unit: uncore_cbox LLC lookup request that access cache and found line in I-state event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0010 event=0x36,umask=0x2A unc_p_freq_band3_cycles freq_ge_3000mhz_cycles % Number of GSSE-256 Computational FP single precision uops issued this cycle This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for This event counts the number of the divide operations executed Multiply packed/scalar single precision uops allocated This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions Cycles with either free list is empty event=0x5b,period=2000003,umask=0xf This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization (Precise event) Counts the number of load micro-ops retired that caused micro TLB miss Counts the matrix events specified by MSR_OFFCORE_RESPx offcore_response.any_code_rd.l2_hit_near_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000044 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state offcore_response.any_pf_l2.l2_hit_far_tile Counts any request that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_rfo.l2_hit_far_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400400 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400400 offcore_response.partial_writes.l2_hit_near_tile_m offcore_response.pf_l1_data_rd.l2_hit_near_tile_m offcore_response.pf_l2_rfo.l2_hit_near_tile_m offcore_response.pf_l2_rfo.l2_hit_this_tile_e Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000020 uops_retired.scalar_simd Counts the number of times the MSROM starts a flow of uops Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180603091 offcore_response.any_pf_l2.mcdram Counts Demand cacheable data write requests that accounts for data responses from DRAM Local offcore_response.demand_code_rd.mcdram_far offcore_response.demand_rfo.ddr_far Counts L2 code HW prefetches that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400040 offcore_response.pf_l2_rfo.mcdram event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000200 Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event) Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP (Precise event) recycleq.any_st event=0x3,umask=0x01 event=0x51,period=2000000,umask=0x1 event=0x40,period=2000000,umask=0x4 l1d_cache_lock.m_state L1 data cache stores in M state l2_data_rqsts.any L2 data demand loads in E state L2 data demand loads in S state event=0xf2,period=100000,umask=0xf L2 instruction fetch misses l2_transactions.rfo mem_inst_retired.latency_above_threshold_4 event=0xcb,period=200000,umask=0x2 Offcore requests blocked due to Super Queue full event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8FF offcore_response.any_rfo.remote_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4708 offcore_response.corewb.remote_cache_dram Offcore writebacks that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x277 Offcore request = all data, response = any location event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4703 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x230 Offcore prefetch data requests satisfied by a remote cache or remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4740 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF20 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x820 offcore_response.prefetch.any_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F70 Offcore prefetch requests that HIT in a remote cache event=0x10,period=2000000,umask=0x40 fp_mmx_trans.to_fp 128 bit SIMD integer pack operations event=0xa6,period=2000000,umask=0x1 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4011 offcore_response.corewb.remote_dram Offcore demand RFO requests satisfied by a remote DRAM Offcore prefetch data requests that missed the LLC offcore_response.pf_data.local_dram Offcore prefetch RFO requests satisfied by a remote DRAM Loads dispatched that bypass the MOB partial_address_alias arith.div event=0x88,period=20000,umask=0x4 event=0x88,period=200000,umask=0x7 Instructions that must be decoded by decoder 0 resource_stalls.store Cycles Uops were issued on either thread event=0xc2,period=2000000,umask=0x1 Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted All retired memory instructions Supports address when precise (Precise event) Retired load instructions that split across a cacheline boundary Supports address when precise (Precise event) Retired load instructions that miss the STLB Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hit Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM offcore_response.demand_code_rd.l3_hit_e.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40100004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040001 Counts all demand data writes (RFOs)have any response type offcore_response.demand_rfo.l3_hit_e.snoop_miss offcore_response.demand_rfo.l3_hit_e.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0040002 offcore_response.demand_rfo.supplier_none.snoop_not_needed offcore_response.other.l3_hit_m.snoop_not_needed sw_prefetch_access.nta Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 Cycles where a code fetch is stalled due to L1 instruction cache tag miss Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles Supports address when precise (Must be precise) offcore_requests.l3_miss_demand_data_rd Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ offcore_response.demand_code_rd.l3_miss.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C8000 offcore_response.other.l3_miss.snoop_non_dram Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes event=0x9,period=2000003,umask=0x1 event=0xc5,period=400009,umask=0x2 event=0x3c,cmask=1,edge=1,period=100007 Cycles total of 2 uops are executed on all ports and Reservation Station was not empty Cycles total of 3 uops are executed on all ports and Reservation Station was not empty Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4 Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide Bad;BadSpec;BrMispredicts_SMT arb@event\=0x80\,umask\=0x2@ / arb@event\=0x80\,umask\=0x2\,cmask\=1@ Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic. Unit: uncore_arb Page walk completed due to a demand data store to a 1G page Page walk completed due to a demand data store to a 2M/4M page Code miss in all TLB levels causes a page walk that completes. (All page sizes) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000044 Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts demand and DCU prefetch instruction cacheline that miss L2 rehabq.any_st rehabq.sta_full This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of "retirement" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS) (Precise event) Retired store uops that miss the STLB. (Precise Event - PEBS) (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0244 offcore_response.all_pf_rfo.llc_hit.no_snoop_needed Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0122 offcore_response.all_rfo.llc_hit.snoop_miss Counts all prefetch (that bring data to L2) RFOs that hit in the LLC Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all prefetch RFOs that miss the LLC and the data returned from dram REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb0,period=100000,umask=0x10 REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f04 offcore_response.other.all_local_dram_and_remote_cache_hit REQUEST = OTHER and RESPONSE = ANY_LOCATION REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff20 REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE event=0xf4,period=2000000,umask=0x4 offcore_response.any_request.any_dram_and_remote_fwd REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x20ff offcore_response.data_ifetch.other_local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3033 REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3002 REQUEST = OTHER and RESPONSE = REMOTE_DRAM REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD snoopq_requests.code event=0x8,period=200000,umask=0x80 Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF50 Retired load instructions which data sources missed L3 but serviced from local dram Supports address when precise (Precise event) mem_load_l3_miss_retired.remote_fwd offcore_response.all_pf_data_rd.l3_hit.hitm_other_core Counts prefetch RFOs that have any response type Counts prefetch RFOs that hit in the L3 offcore_response.pf_l3_data_rd.l3_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000120 offcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.all_rfo.l3_miss.any_snoop offcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.demand_rfo.l3_miss.snoop_miss_or_no_fwd offcore_response.pf_l1d_and_sw.l3_miss.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000080 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) ) Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches unc_m_rpq_inserts event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x04 Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines unc_cha_misc.rfo_hit_s PCIe Completion Buffer Inserts of completions with data: Part 2. Unit: uncore_iio event=0xd5,fc_mask=0x04,umask=0x08 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x01 Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden unc_m2m_imc_reads.normal event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100491 ocr.all_pf_data_rd.l3_hit_e.any_snoop ocr.all_pf_data_rd.l3_hit_f.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200490 ocr.all_pf_data_rd.l3_hit_s.no_snoop_needed OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD ocr.all_pf_rfo.l3_hit_f.snoop_miss OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100120 ocr.all_reads.l3_hit.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C07F7 ocr.all_reads.l3_hit_f.no_snoop_needed OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD ocr.all_rfo.l3_hit_s.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100122 ocr.all_rfo.l3_hit_s.hit_other_core_no_fwd ocr.all_rfo.l3_hit_s.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080004 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C8000 ocr.other.l3_hit.no_snoop_needed ocr.other.l3_hit_s.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080400 ocr.pf_l1d_and_sw.l3_hit_s.any_snoop ocr.pf_l1d_and_sw.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0010 Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit_m.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080080 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit.any_snoop Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.all_data_rd.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.all_data_rd.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400491 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE offcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_fwd offcore_response.all_pf_data_rd.l3_hit_m.hitm_other_core offcore_response.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400120 This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.all_reads.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS offcore_response.all_reads.l3_hit_s.snoop_none This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.l3_hit_s.hitm_other_core offcore_response.demand_rfo.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.demand_rfo.l3_hit_f.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS offcore_response.other.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.other.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l1d_and_sw.l3_hit_f.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020400 offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.pf_l3_data_rd.l3_hit_m.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400080 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000490 OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_pf_rfo.l3_miss.remote_hit_forward OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C0007F7 ocr.all_rfo.l3_miss_local_dram.hitm_other_core Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE ocr.demand_code_rd.l3_miss.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000001 Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC08000 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000400 ocr.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss ocr.pf_l2_data_rd.l3_miss.hit_other_core_fwd ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000080 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS offcore_response.all_reads.l3_miss.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM offcore_response.all_rfo.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss offcore_response.other.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.pf_l3_data_rd.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE ocr.all_pf_rfo.supplier_none.snoop_none ocr.all_rfo.supplier_none.hit_other_core_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP ocr.demand_rfo.supplier_none.hit_other_core_no_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED ocr.other.supplier_none.no_snoop_needed Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED ocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none ocr.pf_l3_data_rd.supplier_none.snoop_miss ocr.pf_l3_rfo.pmm_hit_local_pmm.any_snoop Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED event=0x48,cmask=1,edge=1,period=1000003,umask=0x2 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0002 Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not 1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) ) event=0x60,cmask=1,period=1000003,umask=0x10 Counts the number of times RTM commit succeeded Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region Counts taken branch instructions retired (Precise event) event=0xc5,period=50021 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9 MemoryBound;MemoryLat event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000002 C1_Core_Residency event=0xef,period=1000003,umask=0x1 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000002 ocr.reads_to_core.snc_dram Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect (Precise event) All DRAM CAS commands issued. Unit: uncore_imc DRAM Clockticks. Unit: uncore_imc unc_m_wpq_occupancy_pch1 PMM Read Pending Queue Occupancy. Unit: uncore_imc PMM Commands : Reads - RPQ. Unit: uncore_imc event=0x36,umask=0xC001FD01 unc_cha_cms_clockticks CMS Clockticks. Unit: uncore_cha event=0x35,umask=0xC897FF01 event=0x36,umask=0xC816FE01 unc_cha_tor_inserts.ia_miss_drd_remote TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC. Unit: uncore_cha TOR Inserts; WCiLF misses from local IA. Unit: uncore_cha event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x01 event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x04 unc_iio_txn_req_by_cpu.mem_write.part5 unc_iio_txn_req_by_cpu.mem_write.part7 event=0x1f,umask=0x10 unc_i_coherent_ops.wbmtoi event=0x11,umask=0x08 unc_i_snoop_resp.all_hit_m Counts the number of load uops retired that hit in the L3 cache (Precise event) ocr.corewb_m.l3_hit Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded ocr.hwpf_l2_data_rd.l3_hit Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded ocr.uc_rd.l3_hit.snoop_hitm Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001003C0000 Counts the number of floating point operations retired that required microcode assist Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation Counts uncached memory reads that were not supplied by the L3 cache ocr.partial_streaming_wr.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10470 Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls event=0x71,period=1000003,umask=0x80 Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions unc_cha_tor_occupancy.ia_drd_opt Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 Counts the number of first level TLB misses but second level hits due to loads that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB event=0x49,period=2000003,umask=0x80 Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Unit: cpu_core Average data fill bandwidth to the L1 data cache [GB / sec]. Unit: cpu_core INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORE 100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / ( MEM_BOUND_STALLS.IFETCH ) Inst_Miss_Cost_L2Hit_Percent Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Unit: cpu_core Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]. Unit: cpu_core event=0x20,period=1000003,umask=0x8 event=0x40,period=100003,umask=0x8 arith.fpdiv_active fp_arith_dispatched.port_0 Retired instructions after front-end starvation of at least 1 cycle (Precise event). Unit: cpu_core icache_data.stalls Counts the number of instructions retired. (Fixed event) (Precise event). Unit: cpu_atom Mispredicted indirect CALL retired (Precise event). Unit: cpu_core Core cycles when the thread is not in halt state. Unit: cpu_core event=0xc0,period=2000003,umask=0x10 int_vec_retired.add_128 Cycles when at least one PMH is busy with a page walk for a demand load. Unit: cpu_core Page walks completed due to a demand data store to a 4K page. Unit: cpu_core Instruction fetch requests that miss the ITLB and hit the STLB. Unit: cpu_core Code miss in all TLB levels causes a page walk that completes. (All page sizes). Unit: cpu_core Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.MISS] Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches Supports address when precise OFFCORE_REQUESTS.ALL_REQUESTS fp_arith_inst_retired2.256b_packed_half event=0x2a,period=100003,umask=0x1,offcore_rsp=0x70C004477 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x703004477 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket event=0xec,period=2000003,umask=0x10 INT_VEC_RETIRED.256BIT Number of uops dispatch to execution ports 4 and 9 unc_m_cas_count.rd_pre_reg Valid Flits Sent : Slot 1. Unit: uncore_upi unc_upi_txl_flits.llctrl unc_upi_rxl_flits.data event=0x32,umask=0x0000000002 unc_upi_txl_occupancy event=0x42 event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000004 event=0xc1,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000004 unc_m2m_prefcam_demand_drops.ch0_upi unc_m2m_prefcam_demand_merge.upi_allch event=0x50,umask=0x000000000c Write requests made into the CHA. Unit: uncore_cha event=0x35,umask=0x0000000020 event=0x35,umask=0x0000000040 TOR Inserts : Just Remote Targets. Unit: uncore_cha TOR Occupancy; Misses from Local IA. Unit: uncore_cha TOR Occupancy : All from Local iA. Unit: uncore_cha event=0x36,umask=0x00C000FF05 TOR Occupancy : Just Hits. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_rfo_pref event=0x36,umask=0x00cc43ff04 event=0x36,umask=0x00c88fff01 unc_cha_tor_occupancy.ia_miss_rfo_remote TOR Inserts; RdCur and FsRdCur misses from local IO. Unit: uncore_cha unc_cha_tor_occupancy.ia_llcprefcode unc_cha_tor_inserts.ia_miss_drd_pref_ddr TOR Inserts : ItoMs issued by iA Cores that Hit LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_remote_wcil_pmm unc_cha_tor_occupancy.ia_miss_drd_local_pmm unc_cha_tor_occupancy.ia_miss_drd_pref_local_ddr TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally. Unit: uncore_cha TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_remote_wcil_ddr unc_cha_tor_occupancy.io_clflush event=0x91 Decoder Overrides Existing Branch Prediction (speculative) ic_fetch_stall.ic_stall_dq_empty Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure event=0x8c,umask=0x02 The number of ITLB reload requests All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads event=0x61,umask=0x40 Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used event=0x63,umask=0x01 Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2 Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2 L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead event=0x1cf,umask=0x02 Unit: amd_df fp_retx87_fp_ops.div_sqr_r_ops Divide and square root Ops event=0x3,umask=0xff x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits event=0x5,umask=0x01 ls_mab_alloc.loads ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss bp_l1_tlb_miss_l2_tlb_miss.if1g Total number uOps assigned to pipe 2 Divide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 event=0x24,umask=0x02 ls_smi_rx ls_refills_from_sys.ls_mabresp_lcl_l2 L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB event=0x4b,umask=0xff Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stall Dispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed ls_mab_alloc.all_allocations ls_mab_alloc.hardware_prefetcher_allocations event=0x41,umask=0x40 ls_dmnd_fills_from_sys.mem_io_local ls_dmnd_fills_from_sys.int_cache Demand Data Cache Fills by Data Source. From L3 or different L2 in same CCX ls_sw_pf_dc_fills.int_cache Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts) Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction ex_ret_uncond_brnch_instr_mispred Retired unconditional branch instructions event=0x43,umask=0x80 Any data cache fills from L3 cache or different L2 cache in the same CCX Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2) Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB) ls_sw_pf_dc_fills.dram_io_far Software prefetch data cache fills from all types of data sources ls_hw_pf_dc_fills.dram_io_far Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2 l2_pf_hit_l2.l2_next_line Instruction cache misses L3 cache fill requests sourced from DRAM in a different NUMA node. Unit: amd_l3 Core cycles not in halt local_processor_read_data_beats_cs1 Read data beats (64 bytes) for local processor at Coherent Station (CS) 5 event=0x9f,umask=0xbff Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2 event=0x89f,umask=0xbfe local_socket_inf1_outbound_data_beats_ccm1 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 3 local_socket_inf1_outbound_data_beats_ccm4 event=0x41f,umask=0xbfe Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 3 event=0xcdf,umask=0xf3e fp_ops_retired_by_type.scalar_div fp_ops_retired_by_type.vector_mul Retired vector floating-point multiply-accumulate ops fp_ops_retired_by_type.vector_cvt Retired vector floating-point convert ops fp_ops_retired_by_type.vector_other event=0xb,umask=0x0a event=0xb,umask=0x20 sse_avx_ops_retired.sse_avx_aes event=0xb,umask=0xe0 Retired 128-bit packed floating-point logical ops event=0xd,umask=0xc0 packed_int_op_type.int256_logical Ops dispatched from loop buffer Number of cycles dispatch is stalled for Load queue token 6 * ls_not_halted_cyc d_ratio(bad_speculation * resyncs_or_nc_redirects, ex_ret_brn_misp + resyncs_or_nc_redirects) Fraction of dispatch slots used by microcode ops that retired All L2 cache misses (l3_xi_sampled_latency.all * 10) / l3_xi_sampled_latency_requests.all l1_demand_data_cache_fills_from_local_l2 local_processor_read_data_beats_cs0 + local_processor_read_data_beats_cs1 + local_processor_read_data_beats_cs2 + local_processor_read_data_beats_cs3 + local_processor_read_data_beats_cs4 + local_processor_read_data_beats_cs5 + local_processor_read_data_beats_cs6 + local_processor_read_data_beats_cs7 + local_processor_read_data_beats_cs8 + local_processor_read_data_beats_cs9 + local_processor_read_data_beats_cs10 + local_processor_read_data_beats_cs11 remote_socket_upstream_read_beats_iom0 + remote_socket_upstream_read_beats_iom1 + remote_socket_upstream_read_beats_iom2 + remote_socket_upstream_read_beats_iom3 remote_socket_inf0_inbound_data_beats_ccm0 + remote_socket_inf1_inbound_data_beats_ccm0 + remote_socket_inf0_inbound_data_beats_ccm1 + remote_socket_inf1_inbound_data_beats_ccm1 + remote_socket_inf0_inbound_data_beats_ccm2 + remote_socket_inf1_inbound_data_beats_ccm2 + remote_socket_inf0_inbound_data_beats_ccm3 + remote_socket_inf1_inbound_data_beats_ccm3 + remote_socket_inf0_inbound_data_beats_ccm4 + remote_socket_inf1_inbound_data_beats_ccm4 + remote_socket_inf0_inbound_data_beats_ccm5 + remote_socket_inf1_inbound_data_beats_ccm5 + remote_socket_inf0_inbound_data_beats_ccm6 + remote_socket_inf1_inbound_data_beats_ccm6 + remote_socket_inf0_inbound_data_beats_ccm7 + remote_socket_inf1_inbound_data_beats_ccm7 event=0x34 LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP DC_MICROARCHITECTURAL_EARLY_CANCEL FR_INTERRUPTS_MASKED_CYCLES FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL FR_DISPATCH_STALL_WHEN_FPU_IS_FULL FR_NUMBER_OF_BREAKPOINTS_FOR_DR2 L1_ICACHE_REFILL L2_CACHE_REFILL L2_CACHE_MISS L1_ICACHE_HASH_MISS EVENT_2FH EVENT_3CH EVENT_40H EVENT_6DH EVENT_7DH PLE_FIFO_OVERFLOW EVENT_130H EVENT_166H EVENT_16FH EVENT_17BH EVENT_18DH EVENT_1C1H EVENT_1E8H EVENT_1EFH EVENT_216H EVENT_21DH EVENT_22EH EVENT_256H EVENT_272H EVENT_28CH EVENT_294H EVENT_29AH EVENT_2A5H EVENT_2FCH EVENT_321H EVENT_338H EVENT_352H EVENT_355H EVENT_374H EVENT_39DH EVENT_3B3H EVENT_3F7H dn_rxreq_dvmop sbsx_txdat_stall rni_txreq_flits_total rni_rdb_unord cxra_req_pcrd_stalls_lnk0 cxla_rx_tlp_link0 IU2_INSTR_COMPLETED LSU_TOUCH_ALIAS_VS_CSQ L3_TOUCH_HITS BUS_RETRY PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH BUS_LOW CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES STORE_RETRIES L2_CACHE_DATA_HITS FPU_DOUBLE_PUMP FPU_DIVIDE_CYCLES FPU_PIPE_SYNC_STALLS store-pipe-excluding-junk-ops accesses low-op-pos-0 sse-and-x87-microtraps RUNNING ps->ps_len == 0 fc_mask {"type": "procfork" GenuineIntel-6-3D v8 GenuineIntel-6-85 GenuineIntel-6-2C GenuineIntel-6-7D Backend_Bound_SMT CPI Execute_per_Issue BpTkBranch C6 residency percent per package L2 cache lines filling L2 L2 prefetch requests that hit L2 cache L2 prefetch requests that miss L2 cache event=0xf0,period=200003,umask=0x80 L2 cache accesses when fetching instructions event=0xf0,period=200003,umask=0x1 event=0xf0,period=200003,umask=0x20 event=0xd3,period=100007,umask=0x20 event=0xd1,period=50021,umask=0x10 event=0xb2,period=2000003,umask=0x1 This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention fp_assist.x87_input event=0x79,cmask=1,period=2000003,umask=0x10 Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE Cycles with less than 2 uops delivered by the front end event=0xc8,period=2000003,umask=0x8 Number of times HLE commit succeeded misalign_mem_ref.stores Number of times RTM commit succeeded Number of times a TSX line had a cache conflict event=0x5c,period=2000003,umask=0x1 All (macro) branch instructions retired. (Precise Event - PEBS) Spec update: BDW98 (Must be precise) event=0xc4,period=400009,umask=0x10 Taken speculative and retired mispredicted indirect branches with return mnemonic Cycles while memory subsystem has an outstanding load load_hit_pre.hw_pf Not software-prefetch load dispatches that hit FB allocated for software prefetch Number of integer Move Elimination candidate uops that were eliminated event=0xa2,period=2000003,umask=0x10 This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end event=0x5e,period=2000003,umask=0x1 Cycles per thread when uops are executed in port 1 uops_executed.core_cycles_ge_3 Cycles per core when uops are exectuted in port 5 read requests to local home agent. Unit: uncore_ha unc_m_pre_count.page_miss Pre-charges due to page misses. Unit: uncore_imc Pre-charge for reads. Unit: uncore_imc This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 event=0x49,period=100003,umask=0x40 Operations that miss the first ITLB level but hit the second and do not cause any page walks Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache event=0x24,period=200003,umask=0xd0 This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0091 offcore_response.all_data_rd.l3_hit.snoop_hit_no_fwd offcore_response.all_data_rd.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0120 offcore_response.all_rfo.l3_hit.snoop_none offcore_response.demand_code_rd.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020040 offcore_response.pf_l2_data_rd.supplier_none.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0100 offcore_response.pf_l3_rfo.l3_hit.snoop_not_needed offcore_response.pf_l3_rfo.supplier_none.snoop_hit_no_fwd offcore_response.pf_l3_rfo.supplier_none.snoop_not_needed Counts randomly selected loads with latency value being above 16 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above 32 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000090 offcore_response.all_rfo.l3_miss_local_dram.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000122 offcore_response.pf_l2_data_rd.l3_miss.snoop_hit_no_fwd offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss event=0x3c,period=100003,umask=0x2 unc_cbo_cache_lookup.any_m L3 Lookup read request that access cache and found line in any MESI-state unc_clock.socket Counts all data/code/rfo reads (demand & prefetch) miss in the L3 Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache QPI clock ticks. Unit: uncore_qpi (UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100. event=0x29,period=200000,umask=0x58 event=0x26,period=200000,umask=0x70 l2_lines_out.self.demand l2_reject_busq.self.demand.e_state l2_st.self.e_state Load splits (At Retirement) Bus cycles while processor receives data bus_drdy_clocks.this_agent HIT signal asserted event=0xc4,period=200000,umask=0x8 Retired branch instructions that were mispredicted taken event=0xc4,period=2000000,umask=0xc div.ar event=0xc,period=2000000,umask=0x1 event=0xc,period=200000,umask=0x2 event=0xd1,period=200003,umask=0x40 Counts memory uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) Counts data reads (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000432b7 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x02000032b7 Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_needed event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000004 offcore_response.demand_data_rd.l2_miss.hitm_other_core event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000001 Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwd Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000002 offcore_response.partial_streaming_stores.l2_miss.any Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not Cycles pending interrupts are masked event=0xc4,period=200003,umask=0xbf br_inst_retired.taken_jcc event=0xc5,period=200003,umask=0xeb Loads blocked due to store data not ready (Precise event capable) (Must be precise) Counts load uops retired that caused a DTLB miss Supports address when precise (Must be precise) Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks Page walk completed due to an instruction fetch in a 4K page Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) event=0xd1,period=100003,umask=0x20 Retired store uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Data read requests sent to uncore (demand and prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Number of transitions from AVX-256 to legacy SSE when penalty applicable Spec update: HSD56, HSM57 Counts cycles MITE is delivered four uops. Set Cmask = 4 Counts demand data reads miss in the L3 Counts the number of near return instructions retired (Precise event) Execution stalls due to L1 data cache miss loads. Set Cmask=0CH Cycles at least 2 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 This events counts the cycles where at least two uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 Cycles per core when uops are executed in port 5 L3 Lookup write request that access cache and found line in I-state. Unit: uncore_cbox event=0x22,umask=0x21 Code miss in all TLB levels causes a page walk that completes. (4K) event=0xbd,period=100003,umask=0x20 offcore_response.demand_code_rd.llc_hit.hitm_other_core offcore_response.demand_code_rd.llc_miss.local_dram event=0x27,period=200003,umask=0x8 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0004 offcore_response.all_data_rd.llc_miss.dram Number of requests allocated in Coherency Tracker unc_cbo_xsnp_response.inval event=0x34,umask=0x40 Cycles PMH is busy with this walk offcore_response.pf_llc_data_rd.llc_hit.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads that miss in the LLC Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f820010 PCIe allocating writes that hit in LLC (DDIO hits). Derived from unc_c_tor_inserts.opcode.ddio_hit. Unit: uncore_cbox Occupancy for all LLC misses that are addressed to local memory. Unit: uncore_cbox unc_q_rxl0p_power_cycles (UNC_Q_RxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100. unc_p_freq_band2_cycles Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter. (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu freq_max_current_cycles % l1d.allocated_in_m Instructions retired. (Precise Event - PEBS) (Must be precise) Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss) other_assists.itlb_miss_retired Occupancy counter for all LLC misses; we divide this by UNC_C_CLOCKTICKS to get average Q depth. Unit: uncore_cbox tor_occupancy.miss_all % event=0x8,period=100003,umask=0x2 This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800403091 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004003091 offcore_response.any_pf_l2.l2_hit_near_tile_m Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.bus_locks.l2_hit_far_tile Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.demand_code_rd.l2_hit_far_tile_m Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400002 Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state offcore_response.pf_l2_code_rd.l2_hit_far_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800181000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080803091 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181808000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080808000 offcore_response.demand_code_rd.mcdram_near Counts Demand cacheable data writes that accounts for responses from DDR (local and far) offcore_response.partial_reads.ddr_near event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101002000 offcore_response.pf_l2_rfo.ddr event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800020 no_alloc_cycles.rob_full l1d_wb_l2.mesi l1d_wb_l2.m_state l2_data_rqsts.demand.i_state L2 load misses L2 instruction fetch transactions event=0xf0,period=200000,umask=0x1 event=0xb,period=20,umask=0x10,ldlat=0x1000 event=0xcb,period=40000,umask=0x8 offcore_response.any_data.llc_hit_other_core_hitm offcore_response.any_ifetch.any_location offcore_response.any_request.any_location offcore_response.any_rfo.llc_hit_no_other_core Offcore writebacks to the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1808 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8004 offcore_response.demand_ifetch.local_cache_dram offcore_response.demand_rfo.llc_hit_other_core_hitm Offcore prefetch data requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F20 offcore_response.pf_rfo.local_cache Offcore prefetch requests satisfied by the LLC or local DRAM offcore_response.prefetch.remote_cache_hit All Floating Point to and from MMX transitions event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4044 offcore_response.data_in.remote_dram Offcore demand data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4004 Offcore prefetch data reads satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2040 offcore_response.prefetch.remote_dram l1i.misses event=0x13,period=2000000,umask=0x4 Mispredicted indirect non call branches executed Mispredicted taken branches executed event=0xc0,cmask=16,inv=1,period=2000000,umask=0x1 Cycles no uops were delivered by the LSD Uops executed on port 5 uops_issued.cycles_all_threads Fused Uops issued event=0xc2,cmask=1,inv=1,period=2000000,umask=0x1 Counts all retired memory instructions - loads and stores Supports address when precise (Precise event) mem_load_retired.fb_hit event=0xd1,period=100007,umask=0x40 Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080001 offcore_response.demand_data_rd.l3_hit_s.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100002 offcore_response.other.l4_hit_local_l4.snoop_hit_no_fwd Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Must be precise) frontend_retired.latency_ge_16 frontend_retired.latency_ge_2 frontend_retired.latency_ge_512 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x44000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C408000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000408000 Counts the number of hardware interruptions received by the processor Not taken branch instructions retired Spec update: SKL091 Cycles where the Store Buffer was full and no outstanding load uops_executed.x87 Load miss in all TLB levels causes a page walk that completes. (All page sizes) event=0x49,period=2000003,umask=0x10 event=0x85,cmask=1,period=100003,umask=0x10 Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response offcore_response.any_rfo.l2_miss.snoop_miss offcore_response.corewb.l2_miss.no_snoop_needed offcore_response.demand_code_rd.l2_miss.snoop_miss Counts demand and DCU prefetch data read that miss L2 Any reissued load uops event=0x86,period=200003,umask=0x3f Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0240 Counts all prefetch data reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0004 Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10080 offcore_response.pf_l2_code_rd.llc_miss.dram offcore_requests.any Offcore demand RFO requests Outstanding offcore reads event=0x60,cmask=1,period=2000000,umask=0x1 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f11 REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM offcore_response.data_in.local_dram_and_remote_cache_hit REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM REQUEST = OTHER and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f50 REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD offcore_response.pf_ifetch.any_dram_and_remote_fwd event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2780 offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd Counts all prefetch data reads that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0100 Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800010 Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions. SMT version; use when SMT is enabled and measuring per logical CPU unc_m_cas_count.all DRAM Underfill Read CAS Commands issued. Unit: uncore_imc event=0x4,umask=0x4 DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode. Unit: uncore_imc unc_cha_tor_inserts.ia_miss unc_cha_requests.reads Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe. Unit: uncore_cha unc_cha_sf_eviction.e_state Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states Clockticks of the IIO Traffic Controller. Unit: uncore_iio PCIe Completion Buffer occupancy of completions with data: Part 0 unc_iio_data_req_by_cpu.peer_read.part1 unc_iio_data_req_by_cpu.peer_read.part3 unc_iio_txn_req_by_cpu.mem_read.part2 unc_iio_txn_req_by_cpu.mem_read.part3 Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio unc_i_faf_inserts event=0x27 Messages sent direct to the Intel UPI. Unit: uncore_m2m unc_m2m_directory_lookup.state_a Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to I (Invalid) AD Egress (to CMS) Occupancy. Unit: uncore_m2m event=0x16,umask=0x03 Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power event=0x2,umask=0x27 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100491 OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_hit_m.hitm_other_core OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200004 Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit_s.hit_other_core_fwd ocr.demand_data_rd.l3_hit_s.snoop_miss Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0400 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_hit_f.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040010 ocr.pf_l2_data_rd.l3_hit_s.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080020 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP ocr.pf_l3_data_rd.l3_hit_f.any_snoop Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040080 ocr.pf_l3_data_rd.l3_hit_s.hitm_other_core ocr.pf_l3_rfo.l3_hit_e.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP offcore_response.all_data_rd.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.all_pf_data_rd.l3_hit_f.snoop_none offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_fwd offcore_response.all_pf_rfo.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE offcore_response.all_reads.l3_hit_e.snoop_miss offcore_response.all_reads.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400001 This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE offcore_response.demand_rfo.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS offcore_response.other.l3_hit_f.snoop_miss offcore_response.other.pmm_hit_local_pmm.any_snoop offcore_response.pf_l1d_and_sw.l3_hit_s.any_snoop offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_hit_e.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element ocr.all_data_rd.l3_miss_local_dram.hitm_other_core ocr.all_data_rd.l3_miss_local_dram.no_snoop_needed ocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.all_pf_data_rd.l3_miss.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000490 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1040007F7 ocr.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd ocr.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.demand_data_rd.l3_miss.any_snoop ocr.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000001 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_miss_local_dram.no_snoop_needed Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000080 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000100 ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE offcore_response.other.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.all_reads.supplier_none.any_snoop ocr.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_none ocr.pf_l2_rfo.supplier_none.snoop_miss unc_m_pmm_bandwidth.total unc_m_pmm_wpq_occupancy.all unc_m2m_imc_writes.to_pmm Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Number of cycles a demand request has waited due to L1D due to lack of L2 resources Counts demand requests that miss L2 cache Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1 Supports address when precise (Precise event) Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts retired Instructions who experienced Instruction L1 Cache true miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x510006 TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1 Other_Branches Number of machine clears due to memory ordering conflicts Number of times an instruction execution caused the transactional nest count supported to be exceeded event=0x54,period=100003,umask=0x8 br_inst_retired.cond Mispredicted non-taken conditional branch instructions retired (Precise event) number of branch instructions retired that were mispredicted and taken. Non PEBS (Precise event) Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case event=0xa3,cmask=4,period=1000003,umask=0x4 Number of all retired NOP instructions (Precise event) misc_retired.pause_inst uops_dispatched.port_5 event=0xe,cmask=1,inv=1,period=1000003,umask=0x1 Pipeline;PortsUtil Flops;HPC ocr.demand_data_rd.snc_cache.hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1030000477 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080800 event=0x60,period=1000003,umask=0x2 UOPS_RETIRED.SLOTS / BR_INST_RETIRED.NEAR_TAKEN Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84002380 ocr.other.l3_miss_local ocr.reads_to_core.l3_miss For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM ocr.demand_rfo.snc_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x12380 Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400477 2LM Tag Check : Hit in Near Memory Cache. Unit: uncore_imc event=0x2,umask=0x10 unc_cha_tor_inserts.ia_hit_crd event=0x35,umask=0xCCC7FD01 TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC. Unit: uncore_cha event=0x35,umask=0xCC43FD04 TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC. Unit: uncore_cha unc_iio_data_req_by_cpu.mem_write.part6 unc_iio_data_req_by_cpu.mem_write.part7 event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x04 unc_iio_data_req_of_cpu.cmpd.part4 event=0xc2,ch_mask=0x01,fc_mask=0x04,umask=0x03 unc_i_irp_all.inbound_inserts unc_i_faf_transactions Tag Hit : Dirty NearMem Read Hit. Unit: uncore_m2m unc_m3upi_clockticks Cycles in L0p. Unit: uncore_upi unc_cha_tor_inserts.io_itomcachenear_remote l2_request.hit Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache ocr.all_code_rd.l3_miss_local event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000001 ocr.hwpf_l2_rfo.l3_miss_local ocr.all_code_rd.dram Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return (Precise event) Counts the total number of instructions retired. (Fixed event) (Precise event) Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline event=0x35,umask=0xC827FE01 unc_cha_tor_occupancy.ia_drd_opt_pref unc_cha_tor_occupancy.ia_hit_drd_opt Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 itlb.fills ehl metrics Counts the total number of machine clears including memory ordering, memory disambiguation, self-modifying code, page faults and floating point assist adl metrics ( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * CPU_CLK_UNHALTED.DISTRIBUTED ) Average Frequency Utilization relative nominal frequency. Unit: cpu_core Percentage of total non-speculative loads with a store forward or unknown store address block. Unit: cpu_atom Branch_Mispredict_to_Unknown_Branch_Ratio Inst_Miss_Cost_DRAMHit_Percent mem_scheduler_block.rsv L2 cache lines filling L2. Unit: cpu_core SW prefetch requests that hit L2 cache. Unit: cpu_core SW prefetch requests that miss L2 cache. Unit: cpu_core mem_store_retired.l2_hit Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core Retired Instructions who experienced iTLB true miss (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x600106 Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event). Unit: cpu_core Counts streaming stores that have any type of response. Unit: cpu_atom assists.page_fault event=0xc1,period=1000003,umask=0x8 Counts the total number of mispredicted branch instructions retired for all branch types (Precise event). Unit: cpu_atom Cycles when divide unit is busy executing divide or square root operations. Unit: cpu_core arith.int_divider_active event=0xec,period=2000003,umask=0x40 Number of machine clears (nukes) of any type. Unit: cpu_core Uops executed on port 1. Unit: cpu_core Incoming read prefetch request from IA. Unit: uncore_imc unc_m_dram_page_empty_wr unc_mc1_rdcas_count_freerun event=0x11,cmask=1,period=100003,umask=0x10 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008004477 event=0xcf,period=100003,umask=0x3 event=0xce,period=1000003,umask=0x2 Mispredicted indirect CALL retired (Precise event) M2P Clockticks. Unit: uncore_m2pcie event=0x1,ch_mask=0x0000 Write Requests from a unit on this socket. Unit: uncore_cha unc_cha_requests.invitoe TOR Occupancy for DRd misses from local IA targeting remote memory. Unit: uncore_cha TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha unc_upi_rxl_flits.slot1 event=0x3,umask=0x0000000097 event=0x3,umask=0x0000000047 Matches on Transmit path of a UPI Port : Non-Coherent Bypass. Unit: uncore_upi event=0x5,umask=0x000000000e event=0x12,umask=0x0000000001 event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000004 event=0xc1,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000004 event=0x21,umask=0x0320 unc_cha_osb.local_invitoe event=0x35,umask=0x00c001ff08 event=0x35,umask=0x00c80ffd01 TOR Inserts : Just Hits. Unit: uncore_cha unc_cha_tor_inserts.mmio event=0x35,umask=0x00c8a7fe01 event=0x35,umask=0x00c887fe01 event=0x35,umask=0x00c8c7ff01 event=0x35,umask=0x00c8d7ff01 TOR Occupancy : IRQ - Non iA. Unit: uncore_cha TOR Occupancy : WBQ. Unit: uncore_cha TOR Occupancy : All from Local iA and IO. Unit: uncore_cha TOR Occupancy : All Snoops from Remote. Unit: uncore_cha TOR Occupancy : Just Misses. Unit: uncore_cha event=0x36,umask=0x00c827fd01 event=0x36,umask=0x00c897fe01 TOR Occupancy; DRd Pref misses from local IA. Unit: uncore_cha All LLC lines in M state that are victimized on a fill. Unit: uncore_cha event=0x35,umask=0x00c8f3fe04 unc_cha_tor_inserts.ia_hit_llcprefcode TOR Inserts; LLCPrefData misses from local IA. Unit: uncore_cha event=0x36,umask=0x00ccd7fe01 unc_cha_tor_inserts.ia_miss_crd_local event=0x35,umask=0x00C8668601 TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC. Unit: uncore_cha TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_ddr event=0x36,umask=0x00c86fff01 event=0x36,umask=0x00c86ffe01 ic_cache_inval.l2_invalidating_probe event=0x60,umask=0x40 l2_request_g1.group2 event=0x61,umask=0x80 l2_request_g2.ic_rd_sized event=0x61,umask=0x10 ex_ret_brn_tkn_misp event=0xcb,umask=0x01 event=0x887,umask=0x02 dram_channel_data_controller_6 Total number multi-pipe uOps assigned to pipe 0 fpu_pipe_assignment.total0 event=0x4,umask=0x02 event=0x25,umask=0x01 Number of STLF hits event=0x46,umask=0x04 The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit de_dis_dispatch_token_stalls0.alsq3_token_stall branch_misprediction_ratio l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 all_l2_cache_misses event=0x85,umask=0x07 event=0x85,umask=0x01 event=0xae,umask=0x40 SSE/AVX bottom-executing ops retired. The number of serializing Ops retired The number of retired CLFLUSH instructions. This is a non-speculative event Any Data Cache Fills by Data Source. From L3 or different L2 in same CCX ls_any_fills_from_sys.lcl_l2 Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHW Software Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations ls_dmnd_fills_from_sys.local_ccx ls_dmnd_fills_from_sys.dram_io_far ls_any_fills_from_sys.dram_io_all ls_sw_pf_dc_fills.dram_io_near Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node l2_cache_req_stat.all event=0x71,umask=0x01 event=0x4,umask=0xfe event=0xac,umask=0x04 L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node. Unit: amd_l3 Retired instructions Cycles with no retire due to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects) event=0xdf,umask=0x7fe event=0x21f,umask=0xbfe remote_processor_write_data_beats_cs0 event=0x5f,umask=0xbff Write data beats (64 bytes) for remote processor at Coherent Station (CS) 11 local_socket_upstream_read_beats_iom1 event=0x89f,umask=0x7fe local_socket_upstream_write_beats_iom2 remote_socket_upstream_write_beats_iom3 event=0x45f,umask=0x7fe local_socket_inf0_outbound_data_beats_ccm4 event=0x41f,umask=0x7ff remote_socket_inf1_inbound_data_beats_ccm0 event=0x4de,umask=0xbff fp_ops_retired_by_type.scalar_mul event=0xa,umask=0x08 event=0xa,umask=0xe0 Retired MMX integer subtract ops event=0xb,umask=0x40 sse_avx_ops_retired.sse_avx_shift Retired SSE and AVX integer pack ops event=0xc,umask=0x04 fp_pack_ops_retired.fp128_logical event=0xc,umask=0x0f fp_pack_ops_retired.fp256_mac Retired 256-bit packed floating-point blend ops packed_int_op_type.int128_sub packed_int_op_type.int256_cmp Retired 256-bit packed integer ops of other types umc_cas_cmd.wr Number of memory load operations dispatched to the load-store unit bp_l1_tlb_fetch_hit.all Instruction fetches that hit in the L1 ITLB for all page sizes backend_bound l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all L3 cache access, read Total cache misses DC_REFILL_FROM_L2 FR_RETIRED_X86_INSTRUCTIONS PC_BRANCH_MIS_PRED L1_ICACHE_ACCESS EVENT_44H EVENT_67H EVENT_99H EVENT_B5H EVENT_BDH EVENT_CFH EVENT_D5H EVENT_E2H EVENT_FBH EXTERNAL_INTERRUPT PLE_FIFO_FLUSH EVENT_10CH EVENT_124H EVENT_167H EVENT_17FH EVENT_1ADH EVENT_1C0H EVENT_232H EVENT_255H EVENT_284H EVENT_288H EVENT_2E9H EVENT_302H EVENT_304H EVENT_316H EVENT_32CH EVENT_360H EVENT_36DH EVENT_37EH EVENT_383H EVENT_386H EVENT_3D6H EVENT_3E5H L1D_CACHE_REFILL_ST BUS_ACCESS_PERIPH dn_rxreq_retried hnf_cmp_adq_full rni_s2_rdata_beats rni_wrt_occ_ovfl rni_rrt_alloc clk_upload_stall TLB_BIT_TRANSITIONS LS_LM_COMPLETED L1_INSTR_CACHE_ACCESSES VEC_LOAD_INSTR_COMPLETED CYCLES_ONE_INSTR_DISPATCHED VTQ_STREAM_CANCELED_PREMATURELY VTQ_LINE_FETCH_MISS BRANCH_FLUSHES L2_EXTERNAL_INTERVENTIONS BUS_TAS_FOR_WRITES SNOOP_REQUESTS dc-fill victim-from-l2 write-to-read-turnaround SOFT-CLOCK.HARD DMC620_PMU_C INTEL_ALDERLAKE INTEL_ATOM_TREMONT %s: %s
any GenuineIntel-6-46 Frontend_Bound_SMT TopdownL1_SMT This category represents fraction of slots wasted due to incorrect speculations This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD ) IpArith_Scalar_DP Average data fill bandwidth to the L2 cache [GB / sec] 64 * L2_LINES_IN.ALL / 1000000000 / duration_time L2 cache misses per kilo instruction for all demand loads (including speculative) Mem;MemoryLat;SoC IpFarBranch l1d_pend_miss.pending_cycles event=0xf1,period=100003,umask=0x4 l2_rqsts.l2_pf_hit event=0xf0,period=200003,umask=0x40 This event counts Read for Ownership (RFO) requests that access L2 cache mem_load_uops_l3_hit_retired.xsnp_hit offcore_requests_outstanding.cycles_with_demand_data_rd fp_arith_inst_retired.256b_packed_double Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1 This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention event=0xc1,period=100003,umask=0x8 idq_uops_not_delivered.cycles_le_1_uop_deliv.core Number of times an HLE execution aborted due to HLE-unfriendly instructions mem_trans_retired.load_latency_gt_4 event=0xcd,period=100003,umask=0x1,ldlat=0x4 Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details) Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region Number of times a TSX Abort was triggered due to a non-release/commit store to lock tx_mem.hle_elision_buffer_full This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access br_inst_exec.all_direct_near_call event=0x88,period=200003,umask=0xd0 br_inst_exec.taken_indirect_near_return event=0xc4,period=400009,umask=0x4 br_misp_exec.all_indirect_jump_non_call_ret event=0xc5,period=400009 cpu_clk_unhalted.one_thread_active cpu_clk_unhalted.thread_p int_misc.rat_stall_cycles int_misc.recovery_cycles machine_clears.maskmov Self-modifying code (SMC) detected Number of times any microcode assist is invoked by HW upon uop writeback resource_stalls.rob rob_misc_events.lbr_inserts Count cases of saving new LBR rs_events.empty_end This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0 event=0xb1,cmask=1,period=2000003,umask=0x2 uops_executed.cycles_ge_4_uops_exec llc_misses.mmio_read LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox (UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) * 100. Load misses that miss the DTLB and hit the STLB (4K) event=0x49,period=100003,umask=0x60 dtlb_store_misses.stlb_hit_2m page_walker_loads.itlb_l2 ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020120 offcore_response.demand_code_rd.l3_hit.any_snoop offcore_response.demand_code_rd.supplier_none.snoop_none Counts all demand data writes (RFOs) have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100028000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020010 offcore_response.pf_l2_rfo.any_response offcore_response.pf_l3_data_rd.l3_hit.snoop_hitm Counts all prefetch (that bring data to LLC only) RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000090 offcore_response.demand_code_rd.l3_miss_local_dram.any_snoop offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss offcore_response.demand_rfo.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084008000 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_miss offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020080 Return instructions retired (Precise event) L3 Lookup any request that access cache and found line in I-state event=0x34,umask=0x86 unc_cbo_cache_lookup.write_es unc_arb_trk_occupancy.drd_direct event=0x81,umask=0x01 event=0x84,umask=0x01 offcore_response.demand_rfo.llc_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00091 l2_data_rqsts.self.m_state l2_ld.self.demand.i_state simd_instr_retired SIMD micro-ops executed (excluding stores) prefetch.prefetcht2 busq_empty.self event=0x7b,period=200000,umask=0x0 event=0x6e,period=200000,umask=0xe0 Instruction-fetch bus transactions event=0x6a,period=200000,umask=0x40 br_inst_retired.pred_not_taken event=0x88,period=2000000,umask=0x1 Instructions retired Micro-op reissues for any cause store_forwards.good uops_retired.stalls event=0x82,period=200000,umask=0x4 Requests rejected by the XQ Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.hitm_other_core event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000008000 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000002000 offcore_response.pf_l2_data_rd.l2_miss.any event=0xcd,period=200003,umask=0x2 Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect hw_interrupts.pending_and_masked Counts hardware interrupts received by the processor Retired far branch instructions (Precise event capable) (Must be precise) Retired near relative call instructions (Precise event capable) (Must be precise) Counts loads that block because their address modulo 4K matches a pending store (Must be precise) event=0x3,period=200003,umask=0x1 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem offcore_response.streaming_stores.l2_miss.hitm_other_core Counts data cache lines requests by software prefetch instructions hit the L2 cache Cycles the code-fetch stalls and an ITLB miss is outstanding Retired load uops with L1 cache hits as data sources Supports address when precise. Spec update: HSD29, HSM30 (Precise event) All retired load uops Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore Spec update: HSD62, HSD61, HSM63 avx_insts.all event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00244 FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling Cycles which a uop is dispatched on port 1 in this thread unc_cbo_cache_lookup.extsnp_m Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory). Unit: uncore_arb event=0xbc,period=2000003,umask=0x41 event=0xbc,period=2000003,umask=0x84 event=0xf2,period=100003,umask=0x1 event=0x24,period=200003,umask=0x3 l2_store_lock_rqsts.all Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0001 Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram Loads blocked by overlapping with store buffer that cannot be forwarded Cycles which a Uop is dispatched on port 5 event=0x22,umask=0x01 unc_cbo_xsnp_response.hit Demand load cycles page miss handler (PMH) is busy with this walk offcore_response.all_pf_data_rd.llc_hit.no_snoop_needed Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803c8000 Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.pf_l2_data_rd.llc_miss.local_dram LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode.rfo_prefetch. Unit: uncore_cbox Partial PCIe reads. Derived from unc_c_tor_inserts.opcode.pcie_partial. Unit: uncore_cbox event=0x35,umask=0x1,filter_opc=0x1e5 unc_p_freq_band1_cycles L1D data cache lines in M state evicted due to replacement offcore_response.all_demand_mlc_pref_reads.llc_miss.local_dram br_misp_retired.taken event=0x7,period=100003,umask=0x8 Performance sensitive flags-merging uops added by Sandy Bridge u-arch resource_stalls.lb resource_stalls.lb_sb event=0x5b,period=2000003,umask=0x40 Memory controller clock ticks. Used to get percentages of memory controller cycles events. Unit: uncore_imc event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080044 Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state offcore_response.bus_locks.l2_hit_near_tile_e_f offcore_response.demand_data_rd.l2_hit_this_tile_f Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state offcore_response.demand_rfo.l2_hit_near_tile_e_f offcore_response.partial_reads.l2_hit_far_tile Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080040 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000040 Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state Counts any Prefetch requests that accounts for data responses from MCDRAM Local offcore_response.bus_locks.ddr Counts Bus locks and split lock requests that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400004 offcore_response.demand_rfo.mcdram event=0xb7,period=100007,umask=0x1,offcore_rsp=0x2000020080 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800100 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080202000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800040 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101001000 offcore_response.uc_code_reads.ddr Counts the number of mispredicted branch instructions retired (Precise event) This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched ddr bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_imc unc_e_wpq_inserts event=0x42,period=2000000,umask=0x2 l2_data_rqsts.demand.e_state event=0xf1,period=100000,umask=0x7 L2 RFO hits L2 RFO misses l2_write.lock.hit L2 demand store RFOs in I state (misses) Memory instructions retired above 64 clocks (Precise Event) Retired loads that hit valid versions in the LLC cache (Precise Event) event=0xb7,period=100000,umask=0x1,offcore_rsp=0x111 offcore_response.any_request.io_csr_mmio event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2FF event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8022 offcore_response.any_rfo.llc_hit_other_core_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x722 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3822 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF08 Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8003 Offcore demand data reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x204 offcore_response.other.any_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8080 Offcore other requests satisfied by the LLC offcore_response.pf_data.remote_cache_dram offcore_response.pf_data_rd.remote_cache_hitm offcore_response.pf_ifetch.local_cache_dram offcore_response.pf_rfo.llc_hit_other_core_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3820 Offcore prefetch RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4770 fp_mmx_trans.any simd_int_64.pack simd_int_64.unpack Instructions decoded Macro-fused instructions decoded event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF822 offcore_response.corewb.any_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2008 Offcore data reads, RFO's and prefetches statisfied by the local DRAM offcore_response.pf_data_rd.local_dram offcore_response.pf_rfo.any_dram Offcore prefetch requests satisfied by any DRAM Large ITLB hit sq_full_stall_cycles event=0x88,period=20000,umask=0x20 Retired conditional branch instructions (Precise Event) br_misp_exec.return_near event=0x3c,cmask=2,inv=1,period=2000000,umask=0x0 Instructions retired (Programmable counter and Precise Event) (Precise event) event=0xc3,period=20000,umask=0x1 rat_stalls.rob_read_port SIMD Packed-Double Uops retired (Precise Event) SIMD Packed-Single Uops retired (Precise Event) Cycles Uops executed on ports 0-4 (core count) Cycles no Uops issued on any port (core count) event=0xb1,period=2000000,umask=0x1 Retirement slots used (Precise Event) itlb_misses.any event=0xd0,period=2000003,umask=0x83 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C0004 offcore_response.demand_code_rd.l3_hit_m.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040004 offcore_response.demand_code_rd.l3_hit_s.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0400004 offcore_response.demand_rfo.l3_hit_s.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400088000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100088000 offcore_response.other.l3_hit_m.snoop_none Number of PREFETCHT0 instructions executed sw_prefetch_access.t1_t2 Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event) Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000100001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC400002 This event counts conditional branch instructions retired Spec update: SKL091 (Precise event) Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event) Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions Cycles where the pipeline is stalled due to serializing operations Counts the number of x87 uops executed Fraction of branches that are unconditional (direct or indirect) jumps Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture This event counts requests originating from the core that references a cache line in the L2 cache This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l1_data_rd.l2_miss.snoop_miss REL_CALL counts the number of near relative CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) This event counts the number of store uops retired. (Precise Event - PEBS) (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0004 Counts all demand rfo's Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0100 offcore_response.pf_data_rd.llc_miss_local.dram offcore_response.pf_ifetch.llc_miss_local.dram This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions event=0x60,period=2000000,umask=0x4 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7fff event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2ff REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f10 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf803 offcore_response.demand_data_rd.other_local_dram REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10120 Counts all demand & prefetch RFOs that hit in the L3 Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all demand data writes (RFOs) that have any response type Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00491 Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00080 offcore_response.pf_l3_rfo.l3_miss.any_snoop offcore_response.pf_l3_rfo.l3_miss.remote_hit_forward read requests to memory controller. Unit: uncore_imc event=0x35,umask=0x21,config1=0x40e33 read requests from remote home agent. Unit: uncore_cha unc_cha_requests.writes event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x04 LLC_MISSES.PCIE_WRITE event=0x53,umask=0x01 unc_cha_sf_eviction.s_state unc_iio_clockticks PCIe Completion Buffer Inserts of completions with data: Part 1. Unit: uncore_iio PCIe Completion Buffer occupancy of completions with data: Part 1. Unit: uncore_iio unc_iio_txn_req_by_cpu.mem_write.part2 unc_iio_txn_req_of_cpu.mem_read.part2 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Number of reads in which direct to core transaction were overridden. Unit: uncore_m2m Multi-socket cacheline Directory lookup (cacheline found in S state). Unit: uncore_m2m Multi-socket cacheline Directory update from A to S. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller) unc_m2m_txc_ad_occupancy Cycles Intel UPI is in L1 power mode (shutdown). Unit: uncore_upi FLITs received which bypassed the Slot0 Receive Buffer. Unit: uncore_upi unc_upi_rxl_bypassed.slot1 event=0x3,umask=0x97 Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting. Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs ocr.all_data_rd.l3_hit.no_snoop_needed OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200491 OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_hit_s.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800807F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000807F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8002007F7 ocr.all_reads.l3_hit_m.hit_other_core_fwd OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD ocr.all_rfo.l3_hit_e.hitm_other_core ocr.demand_data_rd.l3_hit.snoop_miss ocr.demand_data_rd.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200002 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED ocr.other.l3_hit.snoop_none ocr.other.l3_hit_m.hit_other_core_fwd ocr.other.l3_hit_s.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040400 ocr.pf_l2_data_rd.l3_hit_e.hit_other_core_fwd ocr.pf_l2_data_rd.l3_hit_f.hitm_other_core Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_hit.snoop_hit_with_fwd ocr.pf_l2_rfo.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200020 ocr.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwd ocr.pf_l2_rfo.l3_hit_f.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100080 ocr.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200100 ocr.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd ocr.pf_l3_rfo.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_f.any_snoop offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_s.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_rfo.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE offcore_response.all_reads.l3_hit_s.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS offcore_response.all_reads.supplier_none.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000207F7 This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS offcore_response.all_rfo.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE offcore_response.demand_code_rd.l3_hit_f.no_snoop_needed offcore_response.demand_code_rd.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE offcore_response.demand_data_rd.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP offcore_response.other.l3_hit_f.no_snoop_needed offcore_response.other.pmm_hit_local_pmm.snoop_not_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_none offcore_response.pf_l1d_and_sw.supplier_none.hitm_other_core offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd offcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_e.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l2_rfo.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020100 OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000491 ocr.all_pf_data_rd.l3_miss.remote_hitm OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE ocr.all_reads.l3_miss.no_snoop_needed ocr.all_rfo.l3_miss.snoop_miss ocr.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000004 ocr.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed ocr.demand_data_rd.l3_miss.hit_other_core_no_fwd ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_fwd ocr.demand_data_rd.l3_miss_local_dram.snoop_none Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.other.l3_miss.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804008000 ocr.other.l3_miss_local_dram.hit_other_core_no_fwd ocr.other.l3_miss_remote_hop1_dram.any_snoop Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD ocr.pf_l2_data_rd.l3_miss.snoop_miss Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS ocr.pf_l3_data_rd.l3_miss.hitm_other_core ocr.pf_l3_data_rd.l3_miss.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.pf_l3_rfo.l3_miss.remote_hit_forward Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS ocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_miss offcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd offcore_response.all_pf_rfo.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.demand_rfo.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED unc_m_pmm_cmd1.wr unc_m_tagchk.miss_dirty Tag Check; Dirty event=0x48,period=1000003,umask=0x2 Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill ocr.demand_code_rd.l3_hit.snoop_not_needed Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not ocr.hwpf_l2_data_rd.l3_hit.snoop_hitm event=0x60,cmask=1,period=1000003,umask=0x8 For every cycle, increments by the number of outstanding demand data read requests pending For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor sq_misc.sq_full Cycles the queue waiting for offcore responses is full event=0xc7,period=100003,umask=0x10 event=0xab,cmask=1,edge=1,period=100003,umask=0x2 Decode Stream Buffer (DSB)-to-MITE transitions count Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity event=0x79,period=100003,umask=0x30 1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0 event=0xc8,period=100003,umask=0x80 Cycles where at least one demand data read request known to have missed the L3 cache is pending Counts Unfriendly TSX abort triggered by a nest count that is too deep Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads event=0x54,period=100003,umask=0x2 Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes ocr.hwpf_l2_rfo.any_response Mispredicted indirect CALL instructions retired (Precise event) Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector) TMA slots wasted due to incorrect speculation by branch mispredictions event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1830000477 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( cha_0@event\=0x0@ / duration_time ) Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket core_snoop_response.s_fwd_fe Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster 2LM Tag Check : Read Hit in Near Memory Cache. Unit: uncore_imc unc_m_tagchk.nm_wr_hit unc_cha_tor_inserts.io event=0x36,umask=0xC817FE01 unc_cha_tor_occupancy.ia_miss_drd_local TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha event=0x35,umask=0xC886FE01 event=0x35,umask=0xc86ffe01 event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x01 event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x01 PCIe Completion Buffer Inserts of completions with data: Part 5. Unit: uncore_iio PCIe Completion Buffer Inserts of completions with data: Part 6. Unit: uncore_iio Page walks completed due to a demand data store to a 1G page Counts the number of L2 Cache accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis mem_bound_stalls.ifetch Counts the number of load uops retired that performed one or more locks Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0044 Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded Counts streaming stores that were supplied by the L3 cache ocr.uc_rd.l3_hit Counts the number of cycles the floating point divider is busy. Does not imply a stall waiting for the divider Counts the number of instruction cache misses ocr.demand_data_and_l1pf_rd.dram ocr.demand_data_and_l1pf_rd.outstanding Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0 (Precise event) Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter (Precise event) topdown_fe_bound.itlb Counts the number of uops that are from complex flows issued by the micro-sequencer (MS) (Precise event) unc_cha_tor_inserts.ia_hit_drd_opt TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0x35,umask=0xC86FFE01 Free running counter that increments for integrated IO (IIO) traffic controller clockticks Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 event=0x8,period=200003,umask=0x80 Counts the number of page walks completed due to load DTLB misses to any page size Total number of retired Instructions Instructions per Load (lower number means higher occurrence rate). Unit: cpu_core Counts the numer of issue slots that result in retirement slots. Unit: cpu_atom 5 * CPU_CLK_UNHALTED.CORE Instructions per Far Branch. Unit: cpu_atom Branch_Mispredict_Ratio Demand Data Read requests that hit L2 cache. Unit: cpu_core assists.sse_avx_mix event=0x5,period=1000003,umask=0x84 Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles Supports address when precise (Must be precise). Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles Supports address when precise (Must be precise). Unit: cpu_core core_power.license_3 topdown_bad_speculation.nuke Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses. Unit: cpu_atom cpu_clk_unhalted.pause_inst Cycles stalled due to no store buffers available. (not including draining form sync). Unit: cpu_core Incoming VC1 write request. Unit: uncore_imc incoming read request page status is Page Empty. Unit: uncore_imc ACT command for a write request sent to DRAM. Unit: uncore_imc event=0x49,period=2000003,umask=0xe Page walks completed due to a demand data store to a 2M/4M page. Unit: cpu_core Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS] Retired load instructions which data sources missed L3 but serviced from local DRAM Supports address when precise event=0xcf,period=100003,umask=0x8 event=0xcf,period=100003,umask=0x1 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x84000800 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C000004 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket cpu_clk_unhalted.c01 TMA slots wasted due to incorrect speculations event=0x5,umask=0x00000000c1 event=0x20,umask=0x0000000002 event=0x5,umask=0x00000000e0 event=0xe0,umask=0x0000000004 unc_m_pmm_rpq_occupancy.no_gnt_sch1 unc_m_pre_count.ufill_pch0 M2M Clockticks. Unit: uncore_m2m M3UPI Clockticks. Unit: uncore_m3upi CHA Clockticks. Unit: uncore_cha event=0x35,umask=0x00c897fe01 unc_upi_txl_flits.prothdr unc_upi_rxl_flits.llcrd event=0x3,umask=0x0000000027 unc_upi_rxl_inserts.slot2 Read request for 4 bytes made by IIO Part2 to Memory. Unit: uncore_iio event=0xc1,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000001 Number Transactions requested by the CPU : Core reading from Cards MMIO space. Unit: uncore_iio unc_cha_tor_inserts.snps_from_rem event=0x35,umask=0x0000000008 event=0x35,umask=0x00c817ff01 event=0x35,umask=0x00C88FFF01 TOR Inserts;CLFlushOpt from Local IA. Unit: uncore_cha TOR Occupancy; LLCPrefRFO hits from local IA. Unit: uncore_cha TOR Occupancy; Hits from local IO. Unit: uncore_cha event=0x36,umask=0x0000000004 TOR Occupancy : RRQ. Unit: uncore_cha unc_cha_tor_occupancy.loc_io unc_cha_tor_occupancy.match_opc unc_cha_tor_occupancy.premorph_opc event=0x37,umask=0x0000000001 event=0x37,umask=0x0000000004 event=0x35,umask=0xcc3fff01 unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmm event=0x35,umask=0x00C80EFE01 event=0x35,umask=0x00C867FE01 unc_cha_tor_inserts.ia_miss_local_wcilf_ddr unc_cha_tor_occupancy.ia_miss_drd_local_ddr event=0x36,umask=0x00c8d7ff01 unc_cha_tor_occupancy.ia_wcilf TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally. Unit: uncore_cha bp_de_redirect l2_request_g2.ic_rd_sized_nc l2_cache_req_stat.ls_rd_blk_l_hit_s Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2 ex_ret_cond Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired fpu_pipe_assignment.dual fpu_pipe_assignment.dual2 Total number of fp uOps on pipe 3 event=0x5,umask=0x02 event=0x29,umask=0x02 Total Page Table Walks on I-side event=0xaf,umask=0x20 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable L2 Cache Misses from L1 Data Cache Misses l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 l2_dtlb_misses The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB page Number of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes Number of retired CLFLUSH instructions ls_refills_from_sys.ls_mabresp_lcl_dram ls_sw_pf_dc_fill.ls_mabresp_lcl_dram event=0x5a,umask=0x08 Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local) Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Floating point register file resource stall. Applies to all FP ops that have a destination register event=0x18e,umask=0x1f Instruction Cache Hit. Counts various IC tag related hit and miss events Any Data Cache Fills by Data Source. From Local L2 to the core ls_sw_pf_dc_fills.ext_cache_remote Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node ls_hw_pf_dc_fills.int_cache Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP Flush recovery stall ls_sw_pf_dc_fills.all L2 cache requests: data cache stores event=0x71,umask=0x80 Retired CPUID instructions event=0x1c1 Ops tagged by IBS Ops tagged by IBS that retired Read data beats (64 bytes) for local processor at Coherent Station (CS) 3 Read data beats (64 bytes) for local processor at Coherent Station (CS) 4 event=0x19f,umask=0x7ff event=0x19f,umask=0xbfe remote_processor_read_data_beats_cs9 remote_processor_write_data_beats_cs6 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 8 remote_socket_upstream_write_beats_iom2 local_socket_inf0_outbound_data_beats_ccm1 remote_socket_inf0_inbound_data_beats_ccm0 event=0x4df,umask=0xbfe fp_ops_retired_by_type.scalar_sub fp_ops_retired_by_type.scalar_cvt event=0xb,umask=0x90 event=0xb,umask=0xff Retired 128-bit packed floating-point multiply-accumulate ops event=0xc,umask=0x10 fp_pack_ops_retired.fp256_other event=0xd,umask=0x0b Number of clocks used by the data bus for reads ls_tlb_flush.all l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all L1 data cache fills from a different NUMA node l1_demand_data_cache_fills_from_near_memory DRAM read data for remote processor Remote socket upstream DMA read data remote_socket_upstream_dma_write_data Estimated combined memory bandwidth UNC_CBO_TWO_HYPH ddr write-cycles event. Unit: uncore_sys_ddr_pmu uncore_sys_ccn_pmu , FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS FR_NUMBER_OF_BREAKPOINTS_FOR_DR3 L2_CACHE_WB CYCLES_NONIDLE_NEON_INT EVENT_29H EVENT_34H EVENT_3BH EVENT_4BH EVENT_68H EVENT_DBH EVENT_E4H EVENT_F5H EVENT_FDH STREX_FAILED ISSUE_DNOT_DISPATCH_ANY_INSTR DMB EVENT_101H EVENT_10EH EVENT_12EH EVENT_139H EVENT_1B8H EVENT_1C5H EVENT_1C8H EVENT_1E0H EVENT_1FDH EVENT_201H EVENT_2B2H EVENT_2B6H EVENT_2B7H EVENT_301H EVENT_36CH EVENT_37FH EVENT_3B9H BUS_ACCESS_SHARED REMOTE_ACCESS dn_rxreq_trk_full hnf_pocq_retry hnf_qos_pocq hnf_snp_fwded rnd_s0_wdata_beats rnd_wrt_alloc cxha_snppcrd_lnk1_stall cxra_req_pcrd_stalls_lnk1 cxla_avg_rx_tlp_sz_ccix_msg cxla_rx_tlp_buffer_full clkdiv2_arbitrate EIEIO_INSTR_COMPLETED VTQ_SUSPENDS_DUE_TO_CTX_CHANGE LSU_RA_LATCH_STALL FALL_THROUGH_BRANCHES_PROCESSED FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY THIRD_SPECULATION_BUFFER_ACTIVE GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD FP_STORE_DOUBLE_COMPLETES_IN_LSU BUS_RETRY_DUE_TO_COLLISION REJECT_COMPLETION_STALL TOTAL_ALLOCATED_TO_DLFB DATA_MMU_BUSY CRIT_INPUT_INTR_LATENCY_CYCLES STALLS_NO_CAQ_OR_COB tlb-reload nop INTEL_ATOM_GOLDMONT INTEL_ICELAKE_XEON PPC_E500 PPC_POWER8 SC ex_ret_instr {"type": "procexec" {"type": "callchain" Cor;Pipeline FP_Arith_Utilization_SMT Branches;Fed;InsType ( cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) SMT_2T_Utilization C6_Core_Residency This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.
Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type Cycles with L1D load Misses outstanding from any thread on physical core This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted event=0x24,period=200003,umask=0x22 This event counts the number of L2 cache accesses when fetching instructions event=0xd2,period=20011,umask=0x2 This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_l3_miss_retired.remote_dram Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x2 event=0xd0,period=100003,umask=0x12 event=0x60,cmask=1,period=2000003,umask=0x8 This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit) idq.all_dsb_cycles_4_uops This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE event=0x79,period=2000003,umask=0x20 idq.ms_uops mem_trans_retired.load_latency_gt_256 event=0x5,period=2000003,umask=0x1 Speculative cache line split load uops dispatched to L1 cache rtm_retired.aborted_misc2 Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region tx_mem.abort_hle_store_to_elided_lock arith.fpu_div_active event=0x88,period=200003,umask=0x82 br_inst_retired.all_branches_pebs Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS) (Precise event) Core cycles when at least one thread on the physical core is not in halt state cycle_activity.cycles_l1d_pending cycle_activity.stalls_l2_miss machine_clears.count other_assists.any_wb_assist Cycles stalled due to re-order buffer full event=0xe,period=2000003,umask=0x1 uncore cache MMIO writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_references.streaming_partial write requests to home agent. Unit: uncore_ha unc_m_power_channel_ppd uncore power prochot_external_cycles % Load misses in all DTLB levels that cause page walks Spec update: BDM69 This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 event=0x49,period=100003,umask=0x4 itlb_misses.walk_duration STLB flush attempts This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) offcore_response.all_pf_data_rd.supplier_none.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010122 offcore_response.corewb.l3_hit.snoop_hit_no_fwd offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400028000 Counts prefetch (that bring data to L2) data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020200 offcore_response.pf_l3_data_rd.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020080 Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000120 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000120 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_not_needed offcore_response.all_rfo.l3_hit.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000122 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hitm offcore_response.demand_code_rd.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000040 offcore_response.pf_l2_code_rd.l3_miss.snoop_none offcore_response.pf_l2_data_rd.l3_hit.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000080 Mispredicted conditional branch instructions retired (Precise event) L3 Lookup any request that access cache and found line in M-state. Unit: uncore_cbox event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0604000244 offcore_response.all_reads.llc_miss.local_dram event=0,umask=0x2 event=0x2c,period=200000,umask=0x44 event=0x2c,period=200000,umask=0x41 event=0x28,period=200000,umask=0x42 event=0x29,period=200000,umask=0x42 l2_ld.self.prefetch.m_state event=0x30,period=200000,umask=0x48 event=0x2e,period=200000,umask=0x42 event=0x2e,period=200000,umask=0x5f SIMD packed shift micro-ops executed x87_comp_ops_exe.any.ar x87_comp_ops_exe.fxch.s Decode stall due to PFB empty Instruction fetches event=0x7,period=2000000,umask=0x10 event=0x7,period=200000,umask=0x86 Memory bus transactions hw_int_rcv Only taken macro conditional branch instructions br_inst_type_retired.dir_call Multiply operations retired Duration of I-Side page walks event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400003091 Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000043010 Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hit_other_core_no_fwd event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040022 offcore_response.any_rfo.l2_miss.hitm_other_core Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000800 Load uops that split a page (Precise event capable) (Must be precise) Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY) Unfilled issue slots per cycle to recover ld_blocks.all_block uops_not_delivered.any Counts uops which retired (Must be precise) event=0x5,period=200003,umask=0x1 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x40000032b7 Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received offcore_response.sw_prefetch.outstanding Demand requests that miss L2 cache Spec update: HSD78, HSM80 Retired load uops with L3 cache hits as data sources Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) offcore_response.all_reads.l3_hit.hitm_other_core offcore_response.demand_rfo.l3_hit.hitm_other_core Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00080 Cycles with pending memory loads. Set Cmask=2 to count cycle Cycles where at least 4 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core. Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core Completed page walks due to demand load misses that caused 4K page walks in any TLB levels This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks event=0xae,period=100003,umask=0x1 Counts the number of ITLB flushes, includes 4k/2M/4M pages Completed page walks in ITLB of any page size Number of DTLB page walker loads that hit in the L1+FB Number of ITLB page walker hits in the L1+FB Number of ITLB page walker hits in Memory Spec update: HSD25 mem_load_uops_llc_hit_retired.xsnp_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0091 ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400091 Number of self-modifying-code machine clears detected unc_cbo_cache_lookup.i event=0x34,umask=0x08 unc_cbo_cache_lookup.read_filter event=0xd3,period=100007,umask=0x3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c03f7 offcore_response.other.lru_hints offcore_response.pf_llc_data_rd.llc_hit.hitm_other_core Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20004 Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) unc_m_act_count.rd event=0xb,filter_band0=12 Retired load uops which data sources were hits in LLC without snoops required This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event) event=0x17,period=2000003,umask=0x1 resource_stalls.mem_rs event=0xa2,period=2000003,umask=0xf0 resource_stalls2.ooo_rsrc uops_dispatched.core unc_m_rpq_occupancy event=0x4,period=200003,umask=0x1 mem_uops_retired.l2_hit_loads Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000070 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x08004032f7 offcore_response.any_request.l2_hit_far_tile Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state offcore_response.partial_reads.l2_hit_far_tile_m Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.pf_l1_data_rd.l2_hit_this_tile_s event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008002000 offcore_response.pf_l2_rfo.l2_hit_near_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400200 offcore_response.uc_code_reads.l2_hit_this_tile_e Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200044 Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000400 offcore_response.demand_code_rd.ddr event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200004 Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100402000 Counts L2 code HW prefetches that accounts for data responses from DRAM Local offcore_response.pf_l2_code_rd.mcdram_near offcore_response.pf_software.ddr_far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180601000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800200 Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far Counts the number of near relative CALL branch instructions retired (Precise event) Fixed Counter: Counts the number of instructions retired no_alloc_cycles.rat_stall Counts any retired load that was pushed into the recycle queue for any reason l1d_all_ref.cacheable L1 data cache reads l1d_cache_st.e_state l1d_prefetch.triggers l1d_wb_l2.i_state event=0x26,period=200000,umask=0xf0 l2_lines_in.e_state L2 Load transactions L2 demand lock RFOs in E state All demand L2 lock RFOs that hit the cache l2_write.lock.s_state Memory instructions retired above 16384 clocks (Precise Event) mem_inst_retired.latency_above_threshold_8192 Retired loads that hit the L2 cache (Precise Event) event=0xf,period=10000,umask=0x20 offcore_response.any_data.any_location Offcore code reads satisfied by the LLC and HITM in a sibling core offcore_response.any_request.remote_cache_hitm offcore_response.data_ifetch.any_location event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4777 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F33 offcore_response.data_in.llc_hit_other_core_hitm Offcore data reads, RFO's and prefetches that HITM in a remote cache Offcore demand data requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x101 offcore_response.other.local_cache_dram offcore_response.pf_ifetch.any_location Offcore prefetch requests satisfied by the LLC and HITM in a sibling core event=0x10,period=2000000,umask=0x80 Offcore data reads satisfied by a remote DRAM offcore_response.any_ifetch.local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x20FF Offcore writebacks to any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2077 offcore_response.data_in.local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF804 offcore_response.demand_rfo.any_dram I/O transactions Mispredicted branches executed br_misp_exec.direct Any Instruction Length Decoder stall cycles event=0x20,period=2000000,umask=0x1 event=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x1f uops_executed.port1 Uops executed on port 3 (core count) uops_executed.port5 event=0xe,cmask=1,inv=1,period=2000000,umask=0x1 itlb_flush mem_load_retired.l1_miss mem_load_retired.l3_miss offcore_response.demand_code_rd.l3_hit_m.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_none offcore_response.demand_rfo.l3_hit_s.snoop_miss offcore_response.demand_rfo.supplier_none.snoop_none offcore_response.other.l4_hit_local_l4.snoop_hitm sw_prefetch_access.t0 Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles Supports address when precise (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x44000004 offcore_response.demand_data_rd.l3_miss.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000048000 offcore_response.other.l3_hit_s.snoop_non_dram memory_disambiguation.history_reset All (macro) branch instructions retired Spec update: SKL091 (Must be precise) Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (OFFCORE_REQUESTS_BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) DSBmiss;Fed_SMT Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed event=0x8,cmask=1,period=100003,umask=0x10 Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake Loads missed UTLB Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts demand and DCU prefetch data read that miss L2 with a snoop miss response rehabq.ld_block_std_notready This event counts the number of retire loads that experienced cache line boundary splits (Precise event) This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding Retired load uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) offcore_response.all_pf_code_rd.llc_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0120 Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.pf_llc_code_rd.llc_hit.snoop_miss offcore_response.all_rfo.llc_miss.dram This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel 64 and IA-32 Architectures Optimization Reference Manual snb metrics Offcore read requests event=0xb0,period=100000,umask=0x2 REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x80ff REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff01 REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE offcore_response.pf_data.local_dram_and_remote_cache_hit REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf833 Loads that partially overlap an earlier store Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all demand code reads that have any response type Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts prefetch (that bring data to L2) data reads that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800004 offcore_response.demand_rfo.l3_miss.remote_hit_forward Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00020 offcore_response.pf_l3_rfo.l3_miss.remote_hitm idi_misc.wb_upgrade ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) ( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000000 / duration_time cha_0@event\=0x0@ Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ event=0x35,umask=0x21,config1=0x40041e33 event=0x50,umask=0x01 Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s) Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe. Unit: uncore_cha Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state Read request for 4 bytes made by the CPU to IIO Part2. Unit: uncore_iio Write request of 4 bytes made to IIO Part1 by the CPU. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_write.part2 Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_write.part1 Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_by_cpu.peer_read.part0 Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_write.part1 event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x02 Inbound write (fast path) requests received by the IRP. Unit: uncore_irp Messages sent direct to core (bypassing the CHA). Unit: uncore_m2m unc_m2m_direct2core_txn_override unc_m2m_directory_lookup.any AD Egress (to CMS) Allocations Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0491 OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_hit.snoop_none ocr.all_pf_rfo.l3_hit_e.snoop_none OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE ocr.all_pf_rfo.l3_hit_f.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040120 OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002007F7 ocr.all_reads.l3_hit_m.hitm_other_core OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP ocr.all_rfo.l3_hit_e.hit_other_core_fwd ocr.all_rfo.l3_hit_e.snoop_none OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE ocr.all_rfo.l3_hit_m.hitm_other_core ocr.all_rfo.l3_hit_m.snoop_none OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE ocr.demand_code_rd.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080004 ocr.demand_code_rd.l3_hit_m.snoop_miss Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD ocr.other.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C8000 ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_hit.no_snoop_needed ocr.pf_l3_data_rd.l3_hit.snoop_none ocr.pf_l3_data_rd.l3_hit_m.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100080 ocr.pf_l3_rfo.l3_hit_f.any_snoop ocr.pf_l3_rfo.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.all_data_rd.l3_hit_e.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.all_pf_data_rd.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP offcore_response.demand_rfo.l3_hit_m.hit_other_core_no_fwd offcore_response.demand_rfo.l3_hit_s.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020002 offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_none offcore_response.pf_l1d_and_sw.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE offcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020020 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_none offcore_response.pf_l3_rfo.l3_hit_e.hitm_other_core offcore_response.pf_l3_rfo.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400100 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (OFFCORE_REQUESTS_BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ( 1000000000 * ( imc@event\=0xe0\,umask\=0x1@ / imc@event\=0xe3@ ) / imc_0@event\=0x0@ ) ( ( 64 * imc@event\=0xe7@ / 1000000000 ) / duration_time ) ocr.all_data_rd.l3_miss.any_snoop OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000120 OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000120 OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.all_rfo.l3_miss.remote_hit_forward OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISS ocr.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core ocr.demand_rfo.l3_miss.no_snoop_needed ocr.demand_rfo.l3_miss_local_dram.snoop_none ocr.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000080 ocr.pf_l3_rfo.l3_miss_local_dram.any_snoop This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD offcore_response.all_data_rd.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.l3_miss.hitm_other_core offcore_response.all_reads.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.all_rfo.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_miss.no_snoop_needed ocr.all_data_rd.supplier_none.hitm_other_core Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.pf_l2_data_rd.supplier_none.hit_other_core_fwd ocr.pf_l3_data_rd.supplier_none.hit_other_core_fwd ocr.pf_l3_rfo.any_response All Reads - RPQ or Ufill event=0xea,umask=0x8 unc_cha_tor_inserts.ia_miss_drd event=0x35,umask=0x21,config1=0x40433 M2M Reads Issued to iMC; All, regardless of priority event=0x2c,umask=0x04 Counts the number of cache lines replaced in L1 data cache Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0x79,cmask=5,period=2000003,umask=0x8 event=0x9c,cmask=5,period=1000003,umask=0x1 Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) ocr.other.local_dram event=0x3c,period=2000003,umask=0x8 This event counts cycles without actually retired instructions int_misc.uop_dropping Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3) event=0xa6,cmask=5,period=2000003,umask=0x21 Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data ocr.demand_data_rd.snc_cache.hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400001 ocr.hwpf_l1d_and_swpf.l3_miss_local event=0xef,period=1000003,umask=0x20 Counts demand data reads that were supplied by DRAM ocr.hwpf_l2.any_response Counts hardware prefetches to the L3 only that have any type of response Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket unc_m_wpq_occupancy_pch0 event=0xe4,umask=0x01 unc_cha_tor_inserts.ia_hit_drd_pref unc_cha_tor_inserts.ia_rfo unc_cha_tor_inserts.ia_miss_drd_local event=0x35,umask=0xCCD7FF01 Number Transactions requested of the CPU : Card reading from DRAM. Unit: uncore_iio event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x80 Number Transactions requested by the CPU : Core reading from Card's MMIO space. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_read.part7 event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x04 Free running counter that increments for IIO clocktick. Unit: uncore_iio Clockticks of the IO coherency tracker (IRP). Unit: uncore_irp M2M Writes Issued to iMC : PMM - All Channels. Unit: uncore_m2m TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory. Unit: uncore_cha Counts the number of load uops retired Supports address when precise (Precise event) This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801F803C0000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0040 Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache ocr.partial_streaming_wr.l3_miss_local event=0xb7,period=100003,umask=0x1,offcore_rsp=0x202184000000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000044 ocr.hwpf_l2_code_rd.any_response Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for (Precise event) Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch event=0x74,period=1000003,umask=0x8 TOR Inserts : UCRdFs issued by iA Cores that Missed LLC. Unit: uncore_cha TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault Counts the number of retired loads that are blocked due to a first level TLB miss (Precise event) Per-Logical Processor actual clocks when the Logical Processor is active. Unit: cpu_core Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Unit: cpu_core Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Unit: cpu_core L1 cache true misses per kilo instruction for retired demand loads. Unit: cpu_core L2 cache true misses per kilo instruction for retired demand loads. Unit: cpu_core Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the last level cache or other core with HITE/F/M. Unit: cpu_atom event=0x4,period=20003,umask=0x4 event=0xc6,period=100007,umask=0x1,frontend=0x604006 Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring. Unit: cpu_atom event=0x76,period=1000003,umask=0x1 Cycles where at least 1 uop was executed per-thread. Unit: cpu_core Counts the number of x87 uops dispatched. Unit: cpu_core ACT command sent to DRAM. Unit: uncore_imc event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008000001 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C4477 FP_ARITH_INST_RETIRED2.SCALAR event=0xcf,period=100003,umask=0x1c event=0xc6,period=100007,umask=0x1,frontend=0x8 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x94002380 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x70CC04477 event=0xa5,period=1000003,umask=0x7 Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state INT_VEC_RETIRED.MUL_256 UPI Clockticks. Unit: uncore_upi event=0x2,umask=0x0000000004 Valid Flits Sent : LLCRD Not Empty. Unit: uncore_upi event=0x2,umask=0x0000000040 Valid Flits Received : Protocol Header. Unit: uncore_upi event=0x4,umask=0x000000000e event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000004 event=0xc1,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000004 event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000080 unc_m2m_tracker_inserts.ch1 event=0x32,umask=0x0000000204 event=0x58,umask=0x0000000001 event=0x35,umask=0x0000000002 unc_cha_tor_inserts.irq_non_ia unc_cha_tor_inserts.prq_non_iosf event=0x35,umask=0x00c806fe01 TOR Inserts RFO misses from local IA. Unit: uncore_cha event=0x36,umask=0x00c80ffe01 unc_cha_tor_occupancy.io_miss_itom TOR Occupancy : IPQ. Unit: uncore_cha event=0x36,umask=0x00c897fd01 event=0x36,umask=0x00c806fe01 event=0x35,umask=0x00cccfff01 event=0x35,umask=0x00C8968601 unc_cha_tor_inserts.ia_itomcachenear event=0x35,umask=0x00C8678A01 TOR Inserts : WCiLs issued by iA Cores. Unit: uncore_cha event=0x35,umask=0x00C86E8601 event=0x35,umask=0x00C8C3FF04 event=0x36,umask=0x00c8168a01 event=0x36,umask=0x00c88efe01 TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha event=0x36,umask=0x00cc47ff01 unc_cha_tor_occupancy.ia_miss_wcilf TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely. Unit: uncore_cha The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB event=0x60,umask=0x80 event=0x64,umask=0x09 Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types) l2_pf_hit_l2 Div Op Count Total number multi-pipe uOps assigned to all pipes event=0x3,umask=0x20 fp_ret_sse_avx_ops.sp_mult_add_flops ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit event=0xaf,umask=0x10 de_dis_dispatch_token_stalls0.alsq2_token_stall l2_cache_accesses_from_ic_misses l1_itlb_misses event=0x94,umask=0x02 Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 Demand Data Cache Fills by Data Source. DRAM or IO from different die L1 DTLB Miss. DTLB reload coalesced page miss Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line in L2 ls_any_fills_from_sys.int_cache Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node All TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed instead Any Integer dispatch. Types of Oops Dispatched from Decoder macro_ops_retired Instruction decoder corrects the predicted target and resteers the branch predictor Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction event=0x59,umask=0xdf ls_hw_pf_dc_fills.dram_io_near Hardware prefetch data cache fills from extension memory L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) l2_pf_miss_l2_hit_l3.l2_up_down event=0xac,umask=0x3f event=0xd6,umask=0xa2 Read data beats (64 bytes) for local processor at Coherent Station (CS) 9 Write data beats (64 bytes) for local processor at Coherent Station (CS) 6 remote_processor_read_data_beats_cs1 event=0x11f,umask=0xbfe Read data beats (64 bytes) for remote processor at Coherent Station (CS) 11 event=0x89f,umask=0x7ff local_socket_upstream_write_beats_iom3 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 0 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 3 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 6 event=0x45f,umask=0x7ff remote_socket_inf0_inbound_data_beats_ccm2 event=0x51e,umask=0xbff remote_socket_inf1_outbound_data_beats_ccm5 local_socket_outbound_data_beats_link4 event=0x8,umask=0x01 event=0x8,umask=0x04 event=0xa,umask=0x05 Retired scalar floating-point blend ops Retired vector floating-point ops of all types fp_pack_ops_retired.fp256_blend event=0xc,umask=0xb0 Retired 256-bit packed floating-point logical ops Retired 256-bit packed floating-point ops of all types packed_int_op_type.int128_pack Retired 128-bit packed integer ops of all types Retired 256-bit packed integer subtract ops packed_int_op_type.int256_mul event=0xd,umask=0x30 Retired 256-bit packed integer MOV ops packed_int_op_type.all Number of CAS commands sent for reads de_src_op_disp.all event=0x1a0,umask=0x1e Fraction of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses) l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all L1 demand data cache fills from another CCX cache in a different NUMA node Ratio of memory controller CAS commands for writes (umc_cas_cmd.rd * 64) / 1e6 / duration_time Memory controller PRECHARGE command rate DC_COPYBACK BUS_CYCLES BRANCH_DIR_MISPREDICT EVENT_41H EVENT_6CH EVENT_9BH EVENT_115H EVENT_125H EVENT_161H EVENT_174H EVENT_1CBH EVENT_1CCH EVENT_1D2H EVENT_1D4H EVENT_1DDH EVENT_1E7H EVENT_2C0H EVENT_2C2H EVENT_2E2H EVENT_2FBH EVENT_31AH EVENT_324H EVENT_341H EVENT_348H EVENT_3B4H EVENT_3D9H EVENT_3F4H UNALIGNED_ST_SPEC STREX_PASS_SPEC DP_SPEC EXC_SMC dn_rxreq_trk_occupancy hnf_sfbi_dir_snp_sent rnd_s1_wdata_beats rni_s1_wdata_beats cxra_chi_rsp_upload_stalls cxla_tx_tlp_link1 clkdiv2_highhigh_qos_depth clkdiv2_refresh VIU2_INSTR_COMPLETED GPR_ISSUE_QUEUE_DISPATCHES LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0 FP_LOAD_DOUBLE_COMPLETED_IN_LSU LSU_MISALIGNED_LOAD_FINISH TLBIE_INSTR_COMPLETED DTLB_HW_SEARCH_CYCLES MARKED_STORE_COMPLETED STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES L2_CACHE_CLEAN_REDUNDANT_UPDATES IAC1S_DETECTED piggyback unhalted-cycles INTERRUPT INTEL_CORE2EXTREME pmclog_get_event LLC-MISSES "0x%016jx", v4 GenuineIntel-6-3A Retiring_SMT SLOTS INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) Bad;BadSpec;BrMispredicts INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES Average CPU Utilization OS Cycles with L1D load Misses outstanding This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects l2_rqsts.all_rfo This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION) This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 event=0x79,cmask=4,period=2000003,umask=0x24 This event counts loads with latency value being above 32 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above eight Spec update: BDM100, BDM35 (Must be precise) Number of times RTM abort was triggered (PEBS) (Precise event) event=0xc9,period=2000003,umask=0x40 event=0xc9,period=2000003,umask=0x80 rtm_retired.commit Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow event=0x5c,cmask=1,edge=1,period=100007,umask=0x1 event=0x88,period=200003,umask=0xc2 This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic This event counts taken speculative and retired indirect branches excluding calls and return branches br_inst_retired.near_call_r3 This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events int_misc.recovery_cycles_any Number of Uops delivered by the LSD event=0xa2,period=2000003,umask=0x1 Cycles stalled due to no store buffers available. (not including draining form sync) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5 uops_dispatched_port.port_6 Cycles where at least 1 uop was executed per-thread event=0xa1,any=1,period=2000003,umask=0x1 llc_misses.pcie_write PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox uncore_ha unc_h_snoop_resp.rspsfwd freq_trans_cycles % dtlb_store_misses.walk_completed itlb_misses.walk_completed_2m_4m event=0x85,period=100003,umask=0x4 ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES event=0x24,period=200003,umask=0xc1 Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020240 offcore_response.all_pf_data_rd.supplier_none.snoop_hitm Counts prefetch RFOs have any response type offcore_response.corewb.supplier_none.snoop_miss Counts any other requests have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C8000 offcore_response.other.l3_hit.snoop_none offcore_response.other.supplier_none.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020010 offcore_response.pf_l2_rfo.l3_hit.snoop_hit_no_fwd offcore_response.pf_l2_rfo.supplier_none.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000091 offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020120 offcore_response.all_rfo.l3_miss_local_dram.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000080 offcore_response.pf_l3_data_rd.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000100 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_not_needed Direct and indirect near call instructions retired (Precise event) event=0x22,umask=0x41 A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core. Unit: uncore_cbox event=0x22,umask=0x81 L3 Lookup any request that access cache and found line in M-state unc_cbo_cache_lookup.read_i event=0x34,umask=0x18 event=0x81,umask=0x02 offcore_response.all_requests.llc_hit.any_response Counts prefetch (that bring data to LLC only) code reads hit in the L3 Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram l2_data_rqsts.self.s_state L2 cache reads event=0x29,period=200000,umask=0x41 event=0x24,period=200000,umask=0x50 l2_reject_busq.self.any.mesi event=0x30,period=200000,umask=0x42 l2_rqsts.self.demand.i_state Retired Streaming SIMD Extensions (SSE) packed-single instructions event=0xc7,period=2000000,umask=0x2 event=0xb3,period=2000000,umask=0x10 simd_uop_type_exec.shift.s macro_insts.cisc_decoded bus_bnr_drv.all_agents event=0x64,period=200000,umask=0x40 bus_trans_p.all_agents Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions event=0xe0,period=2000000,umask=0x1 br_inst_retired.mispred_taken Divide operations executed event=0x86,period=200003,umask=0x2 mem_uops_retired.split offcore_response.any_data_rd.l2_miss.hitm_other_core offcore_response.demand_data_rd.l2_hit Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040020 event=0xc5,period=200003,umask=0xf7 Counts core cycles the integer divide unit is busy event=0x3,period=200003,umask=0x8 Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.any_pf_data_rd.outstanding event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010022 Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache Page walks outstanding due to a demand load every cycle event=0xbd,period=20003,umask=0x20 Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e Dirty L2 cache lines evicted by demand Demand data read requests that missed L2, no rejects Spec update: HSD78, HSM80 All requests that miss L2 cache Spec update: HSD78, HSM80 All requests that missed L2 Spec update: HSD78, HSM80 Demand data read requests that access L2 cache Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops that split across a cacheline boundary Supports address when precise. Spec update: HSD29, HSM30 (Precise event) offcore_response.all_reads.l3_hit.hit_other_core_no_fwd miss in the L3 event=0xc4,period=100003,umask=0x8 This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP) This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued Cycles per core when uops are executed in port 0 uops_issued.core_stall_cycles Cycles when PMH is busy with page walks page_walker_loads.ept_itlb_memory l2_lines_out.pf_clean Clean L2 cache lines evicted by the MLC prefetcher Miss in last-level (L3) cache. Excludes Unknown data-source (Precise event) Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore offcore_requests_outstanding.cycles_with_demand_code_rd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0244 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0002 ( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time Loads with latency value being above 16 (Must be precise) mem_trans_retired.precise_store uops_dispatched_port.port_5_core event=0x22,umask=0x08 Filter on cross-core snoops initiated by this Cbox due to external snoop request. Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to external snoop request Misses in all TLB levels that caused page walk completed of any size by demand loads mem_load_uops_llc_miss_retired.remote_fwd offcore_response.all_pf_data_rd.llc_hit.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c03f7 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded (UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100. RFOs that hit cache lines in E state This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded Taken speculative and retired mispredicted direct near calls event=0x59,period=2000003,umask=0x20 event=0x1 offcore_response.any_data_rd.l2_hit_near_tile_e_f Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008003091 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180070 Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state offcore_response.any_read.l2_hit_near_tile_e_f Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002008000 Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state Counts Bus locks and split lock requests that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000400 Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000002 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800402000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080040 offcore_response.pf_l2_rfo.l2_hit_near_tile offcore_response.pf_software.l2_hit_near_tile_e_f offcore_response.pf_software.l2_hit_this_tile_s Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state offcore_response.uc_code_reads.l2_hit_far_tile_m Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts any Prefetch requests that accounts for responses from MCDRAM (local and far) Counts any Read request that accounts for data responses from DRAM Local Counts Demand cacheable data write requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400022 Counts Bus locks and split lock requests that accounts for responses from DDR (local and far) Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions offcore_response.pf_l1_data_rd.ddr event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181802000 Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local Counts the number of branch instructions retired that were conditional jumps and predicted taken (Precise event) br_misp_retired.call Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted cache_lock_cycles.l1d event=0x42,period=2000000,umask=0x1 event=0x28,period=100000,umask=0x1 event=0x26,period=200000,umask=0x1 L2 data prefetches in E state L2 modified lines evicted by a prefetch request event=0xf0,period=200000,umask=0x80 event=0xf0,period=200000,umask=0x4 All demand L2 lock RFOs L2 demand lock RFOs in S state event=0xb,period=10000,umask=0x10,ldlat=0x10 event=0xb,period=2000000,umask=0x2 mem_load_retired.llc_miss event=0xf,period=20000,umask=0x8 offcore_requests.l1d_writeback event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F11 Offcore data reads satisfied by the LLC and not found in a sibling core Offcore data reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3811 offcore_response.any_data.remote_cache_hitm Offcore code reads satisfied by the IO, CSR, MMIO unit offcore_response.any_rfo.any_cache_dram offcore_response.corewb.io_csr_mmio offcore_response.corewb.llc_hit_other_core_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1877 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x233 offcore_response.demand_data.llc_hit_other_core_hit offcore_response.demand_data_rd.remote_cache_dram offcore_response.demand_rfo.local_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1002 Offcore demand RFO requests that HIT in a remote cache offcore_response.pf_data.any_location event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8040 offcore_response.pf_rfo.llc_hit_no_other_core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3870 128 bit SIMD integer multiply operations SIMD integer 64 bit pack operations SIMD integer 64 bit logical operations simd_int_64.packed_shift event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2044 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4022 offcore_response.data_ifetch.any_llc_miss offcore_response.data_in.any_dram Offcore data reads, RFO's and prefetches statisfied by the remote DRAM Offcore demand data reads that missed the LLC offcore_response.demand_ifetch.any_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6040 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4040 Offcore prefetch code reads satisfied by a remote DRAM ES segment renames large_itlb.hit Thread responded HITE to snoop Divide Operations executed event=0xc4,period=20000,umask=0x2 br_misp_exec.direct_near_call br_misp_exec.near_calls Stall cycles due to BPU MRU bypass Load buffer stall cycles Retired loads that miss the DTLB (Precise Event) Offcore data reads, RFO's and prefetches that HIT in a remote cache event=0xf2,period=200003,umask=0x2 Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3 Spec update: SKL057 Retired load instructions which data sources were hits in L3 without snoops required Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080004 offcore_response.demand_code_rd.l3_hit_s.snoop_none offcore_response.demand_code_rd.l4_hit_local_l4.snoop_none offcore_response.demand_data_rd.l3_hit_m.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40100002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40088000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100048000 event=0x32,period=2000003,umask=0x1 sw_prefetch_access.prefetchw This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.
Note: Invoking MITE requires two or three cycles delay Retired Instructions who experienced Instruction L2 Cache true miss (Precise event) frontend_retired.latency_ge_2_bubbles_ge_1 Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event) frontend_retired.latency_ge_32 offcore_response.demand_rfo.l3_miss.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C408000 offcore_response.other.l4_hit_local_l4.snoop_non_dram rtm_retired.aborted_unfriendly Return instructions retired Spec update: SKL091 (Precise event) Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel) Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events event=0x59,period=2000003,umask=0x1 Counts the number of macro-fused uops retired. (non precise) Total pipeline cost of Branch Misprediction related bottlenecks 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) BigFoot;Fed;Frontend;IcMiss;MemoryTLB Cond_TK This event counts the number of load ops retired that hit in the L2 (Precise event) Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000010 Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l2_rfo.l2_miss.snoop_miss This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time Counts the number of RETURN baclears event=0xca,period=200003,umask=0x50 Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0120 offcore_response.data_in.any_response Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0020 Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_l_data_rd.any_response Counts all prefetch data reads that miss the LLC and the data returned from dram offcore_response.all_pf_rfo.llc_miss.dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400002 offcore_response.pf_llc_code_rd.llc_miss.dram offcore_requests.any.rfo offcore_response.any_ifetch.local_dram_and_remote_cache_hit REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x208 offcore_response.demand_ifetch.local_dram_and_remote_cache_hit REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0x450 REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM Misaligned store references REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM Offcore data reads, RFOs, and prefetches that HIT in a remote cache offcore_response.all_data_rd.l3_hit.no_snoop_needed offcore_response.pf_l1d_and_sw.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0400 offcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0010 Counts all prefetch (that bring data to L2) RFOs that have any response type Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000491 offcore_response.all_pf_rfo.l3_miss.any_snoop Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache Counts demand data reads that miss the L3 and the data is returned from local or remote dram offcore_response.pf_l2_data_rd.l3_miss.any_snoop Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800100 skx metrics 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) ) INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) ( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time unc_m_cas_count.rd_underfill write requests from home agent. Unit: uncore_cha Core Cross Snoops Issued; Multiple Eviction. Unit: uncore_cha unc_cha_dir_lookup.snp PCIe Completion Buffer Inserts of completions with data: Part 0 event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x01 event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x02 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x02 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_read.part0 unc_iio_txn_req_of_cpu.mem_read.part3 event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x08 Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to A (SnoopAll) unc_m2m_prefcam_inserts unc_m2m_rxc_ad_occupancy event=0x31,umask=0x4 Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches. Precise event Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x80 ocr.all_data_rd.l3_hit.snoop_none ocr.all_pf_data_rd.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080490 OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_hit_s.snoop_none OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.SNOOP_MISS ocr.all_reads.l3_hit_m.hit_other_core_no_fwd ocr.demand_code_rd.l3_hit.snoop_none Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200001 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit_f.no_snoop_needed Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000208000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200400 ocr.pf_l1d_and_sw.l3_hit_m.hitm_other_core ocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0010 ocr.pf_l2_data_rd.l3_hit_e.any_snoop Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040100 ocr.pf_l3_rfo.l3_hit_s.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.all_pf_rfo.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP offcore_response.all_reads.l3_hit_e.snoop_none This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.all_rfo.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.other.l3_hit.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.supplier_none.no_snoop_needed offcore_response.pf_l2_data_rd.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP offcore_response.pf_l2_data_rd.supplier_none.hit_other_core_no_fwd offcore_response.pf_l2_data_rd.supplier_none.no_snoop_needed offcore_response.pf_l2_rfo.l3_hit_s.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l3_data_rd.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_needed This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP offcore_response.pf_l3_rfo.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP Fed;LSD PMM_Read_BW Mem;MemoryBW;SoC;Server PMM_Write_BW OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000490 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000120 ocr.all_rfo.l3_miss_local_dram.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000122 ocr.demand_code_rd.l3_miss.snoop_miss ocr.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000001 ocr.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed ocr.demand_rfo.l3_miss.hitm_other_core ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.other.l3_miss_local_dram.snoop_miss Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000010 Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000080 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000100 ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.demand_code_rd.l3_miss_local_dram.hitm_other_core offcore_response.demand_data_rd.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE ocr.demand_rfo.supplier_none.any_snoop ocr.demand_rfo.supplier_none.snoop_none ocr.other.pmm_hit_local_pmm.snoop_none Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD ocr.other.supplier_none.snoop_none Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.pf_l3_rfo.supplier_none.hit_other_core_no_fwd SW prefetch requests that miss L2 cache Counts retired load instructions with locked access Supports address when precise (Precise event) ocr.demand_code_rd.l3_hit.any ocr.hwpf_l2_data_rd.l3_hit.snoop_not_needed ocr.hwpf_l2_rfo.l3_hit.snoop_sent Cycles DSB is delivering optimal number of Uops Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path Uops delivered to IDQ while MS is busy CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED (cstate_pkg@c9\-residency@ / msr@tsc@) * 100 event=0xc8,period=100003,umask=0x20 Counts the number of times we entered an HLE region. Does not count nested transactions event=0x5d,period=100003,umask=0x4 Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response Counts far branch instructions retired (Precise event) Counts core crystal clock cycles when the thread is unhalted event=0x87,period=500009,umask=0x1 Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products event=0xa2,period=100003,umask=0x8 event=0xa2,period=100003,umask=0x2 event=0xa4,period=10000003,umask=0x8 Counts cycles when at least 4 micro-ops are executed from any thread on physical core Number of page walks outstanding for an outstanding code request in the PMH each cycle ocr.demand_code_rd.snc_cache.hitm Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0477 event=0x60,cmask=1,period=1000003,umask=0x2 UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000000 / duration_time Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally event=0xb7,period=100003,umask=0x1,offcore_rsp=0x700C00477 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x700800477 event=0x4,umask=0x30 event=0x10,umask=0x02 Half clockticks for IMC. Unit: uncore_imc event=0x1,umask=0x0B TOR Inserts : DRds issued by iA Cores that Hit the LLC. Unit: uncore_cha event=0x35,umask=0xC001FE04 unc_cha_tor_occupancy.io TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_rfo unc_cha_tor_inserts.ia_miss_drd_local_ddr event=0x85,ch_mask=0xFF,fc_mask=0x07,umask=0x01 event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x01 event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x80 Valid Flits Received : Null FLITs received from any slot. Unit: uncore_upi Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis l2_request.rejects event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401F803C0000 Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed Counts uncached memory reads that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010003C0000 Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt) (Precise event) Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache ocr.uc_wr.l3_miss bus_lock.cycles_self_block Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2 topdown_bad_speculation.fastnuke topdown_be_bound.reorder_buffer event=0x71,period=1000003,umask=0x2 Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations event=0x35,umask=0xC001FE01,config1=0x41a33 TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0x35,umask=0xC867FE01 TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : DRd_Opts issued by iA Cores. Unit: uncore_cha TOR Occupancy : DRd_Opt_Prefs issued by iA Cores. Unit: uncore_cha Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 event=0x49,period=200003,umask=0xe event=0x4f,period=2000003,umask=0x2 Counts the number of memory ordering machine clears triggered by a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate). Unit: cpu_core L3 cache true misses per kilo instruction for retired demand loads. Unit: cpu_core event=0xd0,period=1000003,umask=0x5,ldlat=0x10 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise). Unit: cpu_atom mem_uops_retired.load_latency_gt_64 RFO requests to L2 cache. Unit: cpu_core event=0x79,period=1000003,umask=0x20 event=0x9c,cmask=6,period=1000003,umask=0x1 assists.hardware Counts the total number of consumed retirement slots (Precise event). Unit: cpu_atom Number of instructions retired. Fixed Counter - architectural event (Precise event). Unit: cpu_core integer ADD, SUB, SAD 256-bit vector instructions. Unit: cpu_core int_vec_retired.mul_256 Self-modifying code (SMC) detected. Unit: cpu_core topdown.memory_bound_slots Cycles at least 3 micro-op is executed from any thread on physical core. Unit: cpu_core Cycles at least 4 micro-op is executed from any thread on physical core. Unit: cpu_core Cycles where at least 2 uops were executed per-thread. Unit: cpu_core event=0x1a event=0x22 ld_head.dtlb_miss_at_ret Stores that miss the DTLB and hit the STLB. Unit: cpu_core event=0xd3,period=1000003,umask=0x4 MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM Supports address when precise event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F803C0004 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x80080800 fp_arith_inst_retired2.128b_packed_half FP_ARITH_INST_RETIRED2.256B_PACKED_HALF FP_ARITH_INST_RETIRED2.VECTOR event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104000002 amx_ops_retired.bf16 event=0xce,period=1000003,umask=0x1 integer ADD, SUB, SAD 128-bit vector instructions integer ADD, SUB, SAD 256-bit vector instructions event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000001 Valid Flits Sent : Slot 0. Unit: uncore_upi event=0x3,umask=0x000000000f Matches on Receive path of a UPI Port : Non-Coherent Bypass. Unit: uncore_upi event=0x5,umask=0x000000010f event=0x30,umask=0x0000000004 Read request for 4 bytes made by IIO Part1 to Memory. Unit: uncore_iio event=0xc1,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000004 event=0x20,umask=0x08 unc_cha_osb.local_read TOR Inserts; ItoM misses from local IO. Unit: uncore_cha unc_cha_tor_inserts.rrq TOR Occupancy; CRd misses from local IA. Unit: uncore_cha unc_cha_tor_occupancy.prq unc_cha_tor_occupancy.loc_ia unc_cha_tor_occupancy.remote_tgt TOR Occupancy; CRd Pref hits from local IA. Unit: uncore_cha TOR Occupancy; CRd from local IA. Unit: uncore_cha event=0x36,umask=0x00c886fe01 unc_cha_tor_occupancy.ia_hit_llcprefcode unc_cha_tor_occupancy.ia_miss_llcprefdata TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_wcilf_ddr unc_cha_tor_occupancy.ia_miss_drd_remote_pmm event=0x36,umask=0x00c8678a01 event=0x36,umask=0x00c8670a01 unc_cha_tor_occupancy.io_hit_itomcachenear L2 BTB Correction The number of instruction fetches that hit in the L1 ITLB event=0x87,umask=0x04 l2_cache_req_stat.ic_dc_hit_in_l2 event=0x9a,umask=0x3f ex_ret_brn_far Retired Branch Resyncs ex_ret_mmx_fp_instr.mmx_instr dram_channel_data_controller_1 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3 event=0,umask=0x20 fpu_pipe_assignment.total The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Ops event=0x3,umask=0x08 fp_num_mov_elim_scal_op.optimized This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass) event=0x4,umask=0x01 Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores ls_mab_alloc.dc_prefetcher event=0x4b,umask=0x04 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable recommended L1 Instruction Cache (32B) Fetch Miss Ratio event=0x78,umask=0xdf event=0xe,umask=0x04 ls_locks.spec_lock_lo_spec Cycles where the Micro-Op Queue is empty The number of retired branch instructions, that were mispredicted Multiply FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent Retired lock instructions. Comparable to legacy bus lock event=0x41,umask=0x3f Load Store Allocations. Counts when a LS pipe allocates a MAB entry event=0x44,umask=0x08 Op Cache (64B) Fetch Miss Ratio Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) Any data cache fills from either DRAM or MMIO in the same NUMA node L2 cache requests of common types not including prefetches event=0x71,umask=0x08 Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node. Unit: amd_l3 local_processor_read_data_beats_cs2 event=0xdf,umask=0x7ff remote_processor_read_data_beats_cs4 remote_processor_write_data_beats_cs2 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 7 local_socket_upstream_write_beats_iom1 event=0x4de,umask=0x7fe local_socket_inf0_outbound_data_beats_ccm3 remote_socket_inf1_inbound_data_beats_ccm6 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 6 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 0 event=0xa,umask=0x0f event=0xa,umask=0x50 event=0xb,umask=0x0d sse_avx_ops_retired.sse_avx_clm Retired 256-bit packed floating-point square root ops Retired 128-bit packed integer AES ops Retired 128-bit packed integer pack ops packed_int_op_type.int128_other Floating-point dispatch faults for YMM fills Floating-point dispatch faults for YMM spills umc_mem_clk Number of ACTIVATE commands sent for reads d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + resyncs_or_nc_redirects) All data cache accesses 0x01 IC_REFILL_FROM_L2 NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW EVENT_0DH EVENT_2AH EVENT_3AH EVENT_47H EVENT_4DH EVENT_58H EVENT_A5H EVENT_AEH EVENT_D7H EVENT_DCH EVENT_E5H PC_WRITE_RETIRED EVENT_105H EVENT_110H EVENT_143H EVENT_14CH EVENT_177H EVENT_196H EVENT_1D1H EVENT_20FH EVENT_231H EVENT_234H EVENT_257H EVENT_267H EVENT_27BH EVENT_2B4H EVENT_30DH EVENT_32AH EVENT_32BH EVENT_335H EVENT_343H EVENT_350H EVENT_38AH EVENT_38EH EVENT_390H EVENT_3AEH EVENT_3B8H EVENT_3DDH EXC_TRAP_FIQ STALL_FRONTEND L1I_TLB L1D_CACHE_REFILL_INNER L1D_CACHE_REFILL_OUTER hnf_seq_full rnd_txreq_flits_replayed cxra_snp_sink_buf_occ DST_INSTR_DISPATCHED CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS CANCELLED_L1_INSTR_CACHE_MISSES VT2_FETCHES BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY L2_LOAD_HITS INTERVENTION BUS_WRITES_NOT_RETRIED THRESHOLD_TIMEOUT CR_MARKED_INSTR_FINISH CACHE_INHIBITED_ACCESS_TRANSLATED INSTR_MMU_VSP_RELOADS STASH_L1_HITS COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES hw_interrupts.received {"type": "userdata" %s, "pid": "%d", "start": "0x%016jx", "pathname": "%s"}
GenuineIntel-6-27 v1 GenuineIntel-6-7E GenuineIntel-6-6C TopdownL1 Backend_Bound IPC Ret;Summary 4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) SLOTS_SMT Core actual clocks when any Logical Processor is active on the Physical Core Instructions per Store (lower number means higher occurrence rate) INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE Instructions L2MPKI_Load Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches event=0xf1,period=100003,umask=0x7 This event counts L2 writebacks that access L2 cache event=0xd3,period=100007,umask=0x1 All retired load uops. (Precise Event - PEBS) Supports address when precise (Precise event) Retired store uops that miss the STLB. (Precise Event - PEBS) Supports address when precise (Precise event) Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: BDM76 offcore_requests_outstanding.demand_data_rd Split locks in SQ event=0xc7,period=2000003,umask=0x20 idq.dsb_uops event=0x79,cmask=1,edge=1,period=2000003,umask=0x10 event=0x9c,period=2000003,umask=0x1 idq_uops_not_delivered.cycles_0_uops_deliv.core Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Number of times an HLE execution aborted due to uncommon conditions Loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=50021,umask=0x1,ldlat=0x8 rtm_retired.aborted_misc4 Number of times we entered an RTM region
does not count nested transactions event=0x54,period=2000003,umask=0x10 Speculative and retired branches event=0xc4,period=100007,umask=0x8 br_misp_exec.taken_indirect_near_call event=0xc5,period=400009,umask=0x1 event=0xc5,period=100007,umask=0x8 Reference cycles when the thread is unhalted (counts at 100 MHz rate) event=0x3c,any=1,period=2000003,umask=0x1 event=0x3c,any=1,period=2000003 Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache This event counts self-modifying code (SMC) detected, which causes a machine clear event=0xa1,period=2000003,umask=0x40 uops_executed.core_cycles_none event=0xb1,cmask=4,period=2000003,umask=0x1 uops_executed_port.port_1_core event=0x21,umask=0x20 Cycles Memory is in self refresh power mode. Unit: uncore_imc freq_max_power_cycles % This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) Data from local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) Retired load uops that miss the STLB Supports address when precise (Precise event) This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020004 Counts all demand data writes (RFOs) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200028000 offcore_response.pf_l2_data_rd.l3_hit.snoop_miss offcore_response.pf_l2_rfo.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0200 Counts all prefetch (that bring data to LLC only) data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020100 Counts randomly selected loads with latency value being above eight Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000091 offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000122 offcore_response.all_rfo.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000040 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000100 This 48-bit fixed counter counts the UCLK cycles. Unit: uncore_ncu offcore_response.all_reads.llc_hit.hitm_other_core Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram offcore_response.all_reads.llc_miss.remote_hit_forward Cycles the L2 transfers data to the core l2_ifetch.self.mesi event=0x2d,period=200000,umask=0x4f l2_reject_busq.self.demand.m_state L2 cache requests bus_trans_burst.all_agents bus_trans_ifetch.self IO bus transactions event=0x67,period=200000,umask=0x40 dispatch_blocked.any event=0x7e,period=200000,umask=0xe0 bogus_br br_missp_type_retired.cond_taken event=0x12,period=2000000,umask=0x81 resource_stalls.div_busy store_forwards.any event=0x8,period=200000,umask=0x9 event=0x2e,period=200003,umask=0x41 Loads retired that came from DRAM (Precise event capable) Supports address when precise (Must be precise) offcore_response.any_request.l2_hit Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000008 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000020 Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xe6,period=200003,umask=0x8 Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0) Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return (Must be precise) Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken (Must be precise) Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event event=0xca,period=200003,umask=0x1 Loads blocked (Precise event capable) (Must be precise) event=0xc3,period=200003 Uops retired (Precise event capable) (Must be precise) Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000008000 Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000004800 event=0xc3,period=20003,umask=0x8 Page walk completed due to a demand load to a 2M or 4M page itlb_misses.walk_completed_1gb Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault event=0x85,period=2000003,umask=0x4 Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault l2_lines_out.demand_dirty offcore_response.pf_l3_rfo.l3_hit.any_response Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 Randomly selected loads with latency value being above 256 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) offcore_response.all_code_rd.l3_miss.local_dram Counts all prefetch (that bring data to L2) RFOs miss in the L3 Cycles with pending L1 cache miss loads unc_cbo_cache_lookup.extsnp_i Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G) event=0x49,period=100003,umask=0x80 Completed page walks due to misses in ITLB 2M/4M page entries Number of DTLB page walker hits in the L3 + XSNP Spec update: HSD25 page_walker_loads.ept_itlb_l1 offcore_response.demand_data_rd.llc_hit.hitm_other_core l2_store_lock_rqsts.miss Core-originated cacheable demand requests missed LLC mem_load_uops_llc_hit_retired.xsnp_none Retired store uops that miss the STLB. (Precise Event) Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010004 Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle event=0xc1,period=100003,umask=0x20 event=0x11,period=2000003,umask=0x2 1 / ( ((FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD) + ((FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD) ) Loads with latency value being above 128 (Must be precise) Loads with latency value being above 32 (Must be precise) Cycles which a Uop is dispatched on port 2 event=0xa1,any=1,period=2000003,umask=0xc Retired uops (Precise event) unc_cbo_cache_lookup.write_filter Cycle PMH is busy with a walk due to demand loads Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses offcore_response.pf_llc_data_rd.llc_hit.snoop_miss Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram event=0xb (UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100. event=0xd,edge=1 dtlb_load_misses.demand_ld_walk_completed Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) This event counts the number of Uops issued by the front-end of the pipeilne to the back-end event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010070 offcore_response.any_pf_l2.l2_hit_this_tile_e Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state offcore_response.any_request.l2_hit_this_tile_m Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.demand_rfo.l2_hit_this_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080080 offcore_response.partial_reads.l2_hit_this_tile_f Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts UC code reads (valid only for Outstanding response type) that accounts for any response Counts all instruction fetches, including uncacheable fetches Counts the number of times the machine clears due to memory ordering hazards event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000100 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400020 offcore_response.uc_code_reads.mcdram_near event=0xc5,period=200003,umask=0xbf Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire recycleq.sta_full event=0xcb,period=200003,umask=0x1 event=0x5,edge=1,period=100003,umask=0x3 l1d_cache_lock.e_state L1 data cache load lock hits L2 lines allocated in the S state event=0x24,period=200000,umask=0x30 L2 instruction fetches Memory instructions retired above 16 clocks (Precise Event) mem_inst_retired.latency_above_threshold_32768 mem_inst_retired.latency_above_threshold_4096 Instructions retired which contains a load (Precise Event) Retired loads that miss the LLC cache (Precise Event) Load instructions retired that HIT modified data in sibling core (Precise Event) event=0xb7,period=100000,umask=0x1,offcore_rsp=0x144 Offcore code reads satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1844 Offcore requests that HITM in a remote cache Offcore RFO requests satisfied by the LLC and HIT in a sibling core offcore_response.any_rfo.local_cache All offcore writebacks offcore_response.data_ifetch.any_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8077 Offcore code or data read requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x777 offcore_response.data_ifetch.remote_cache_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F03 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x403 offcore_response.demand_data.local_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF01 offcore_response.demand_ifetch.any_cache_dram Offcore demand code reads satisfied by the LLC and not found in a sibling core offcore_response.demand_rfo.any_location event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F80 Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core Offcore prefetch RFO requests that HIT in a remote cache Offcore prefetch requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x770 X87 Floating point assists for invalid output value (Precise Event) fp_comp_ops_exe.sse_fp_packed Offcore requests satisfied by a remote DRAM Offcore RFO requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6077 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF803 offcore_response.demand_data_rd.any_dram offcore_response.demand_ifetch.any_llc_miss Offcore prefetch data requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2010 event=0x89,period=20000,umask=0x1 Mispredicted non call branches executed Cycles when thread is not halted (fixed counter) Instruction Queue full stall cycles load_hit_pre event=0xa2,period=2000000,umask=0x4 SIMD Scalar-Double Uops retired (Precise Event) uops_executed.port2_core event=0xae,period=2000000,umask=0x1 event=0xcb,period=200000,umask=0x80 Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted mem_inst_retired.split_loads Counts retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_miss Counts both cacheable and non-cacheable code read requests offcore_response.demand_code_rd.l3_hit_e.spl_hit offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hitm offcore_response.demand_code_rd.l4_hit_local_l4.snoop_not_needed offcore_response.demand_rfo.l3_hit_e.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C8000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000088000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40108000 event=0xe6,period=100003,umask=0x1 frontend_retired.itlb_miss Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event) Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) Cycles where a code fetch is stalled due to L1 instruction cache miss cycle_activity.stalls_l3_miss Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles Supports address when precise (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000100002 Instruction decoders utilized in a cycle Counts resource-related stall cycles Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread skl metrics BigFoot;Fed;Frontend;IcMiss;MemoryTLB_SMT Average per-core data access bandwidth to the L3 cache [GB / sec] 1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture Counts any code reads (demand & prefetch) that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000044 Counts any request that hit in the other module where modified copies were found in other core's L1 cache Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache offcore_response.pf_l2_code_rd.l2_miss.any ALL_BRANCHES counts the number of any branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) RETURN counts the number of near RET branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND Mispredicted taken branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xb0,period=100000,umask=0x80 offcore_response.any_data.all_local_dram_and_remote_cache_hit REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5010 REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM offcore_response.demand_data.other_local_dram event=0x49,period=200000,umask=0x20 Counts all prefetch data reads that hit in the L3 offcore_response.all_rfo.l3_hit.no_snoop_needed offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all demand & prefetch data reads that miss in the L3 Counts prefetch RFOs that miss the L3 and the data is returned from local dram Counts all demand code reads that miss the L3 and the data is returned from local or remote dram offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram CORE_POWER.LVL0_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) Read Pending Queue Occupancy. Unit: uncore_imc MMIO reads. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha PCI Express bandwidth writing at IIO, part 0. Unit: uncore_iio event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x01 event=0x59,umask=0x01 CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH. Unit: uncore_cha event=0x3d,umask=0x04 unc_iio_comp_buf_inserts.cmpd.part1 unc_iio_data_req_of_cpu.peer_write.part3 Read request for up to a 64 byte transaction is made by IIO Part1 to Memory. Unit: uncore_iio event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x02 Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP unc_i_faf_occupancy event=0x23 unc_m2m_direct2upi_txn_override Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden Multi-socket cacheline Directory lookup (cacheline found in I state). Unit: uncore_m2m unc_m2m_directory_lookup.state_s event=0x2d,umask=0x4 event=0x12,umask=0x2 OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080491 ocr.all_pf_data_rd.l3_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080490 OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080120 ocr.all_pf_rfo.l3_hit_m.any_snoop ocr.all_pf_rfo.l3_hit_m.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040120 OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000407F7 OCR.ALL_READS.L3_HIT_M.SNOOP_MISS ocr.all_rfo.l3_hit_f.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040122 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_hit_e.any_snoop ocr.demand_code_rd.l3_hit_f.hit_other_core_no_fwd Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200001 ocr.demand_rfo.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200002 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80208000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800208000 ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200400 ocr.pf_l2_data_rd.l3_hit_e.snoop_none ocr.pf_l2_data_rd.l3_hit_f.snoop_none ocr.pf_l2_data_rd.l3_hit_m.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080020 ocr.pf_l2_rfo.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040080 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_hit_s.snoop_none Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100100 offcore_response.all_pf_data_rd.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE offcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.all_rfo.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.l3_hit_s.hit_other_core_no_fwd offcore_response.demand_rfo.l3_hit_f.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.demand_rfo.supplier_none.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE offcore_response.other.l3_hit_f.hit_other_core_no_fwd offcore_response.other.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.pf_l2_data_rd.l3_hit_e.snoop_none offcore_response.pf_l2_data_rd.l3_hit_m.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_fwd offcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400080 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE offcore_response.pf_l3_rfo.l3_hit_m.hitm_other_core offcore_response.pf_l3_rfo.supplier_none.hit_other_core_no_fwd ocr.all_data_rd.l3_miss.hitm_other_core ocr.all_data_rd.l3_miss_local_dram.snoop_none ocr.all_data_rd.l3_miss_remote_hop1_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000491 OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000490 OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000002 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810008000 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.pf_l2_rfo.l3_miss.hitm_other_core ocr.pf_l2_rfo.l3_miss.remote_hitm ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss ocr.pf_l3_data_rd.l3_miss.any_snoop ocr.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED offcore_response.all_reads.l3_miss.snoop_miss offcore_response.all_reads.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.all_rfo.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS offcore_response.demand_data_rd.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.pf_l3_rfo.l3_miss.hit_other_core_fwd OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS ocr.demand_rfo.supplier_none.snoop_miss Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED ocr.other.supplier_none.hitm_other_core ocr.pf_l2_rfo.supplier_none.any_snoop ocr.pf_l3_data_rd.any_response Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE Intel Optane DC persistent memory bandwidth total (MB/sec). Unit: uncore_imc event=0xea,umask=0x2 Tag Check; Hit Retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) ocr.other.l3_hit.snoop_hit_no_fwd Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES Counts the number of times RTM abort was triggered event=0xc9,period=100003,umask=0x40 event=0x54,period=100003,umask=0x10 All branch instructions retired (Precise event) event=0xc5,period=50021,umask=0x20 Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event topdown.slots_p Cycles when at least one PMH is busy with a page walk for a demand load ( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CORE_CLKS ) Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock) Supports address when precise (Precise event) Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C27F0 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84408000 Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally ocr.prefetches.l3_miss_local event=0xb7,period=100003,umask=0x1,offcore_rsp=0x70CC00477 Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core ocr.demand_data_rd.local_pmm Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM event=0x20,umask=0x02 PMM Read Queue Inserts. Unit: uncore_imc event=0x35,umask=0xC001FD01 event=0x35,umask=0xC807FE01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC. Unit: uncore_cha event=0x35,umask=0xC80FFF01 event=0x35,umask=0xC896FE01 event=0x35,umask=0xC806FE01 unc_cha_tor_inserts.ia_miss_rfo_pref_local unc_iio_data_req_of_cpu.cmpd.part5 event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x01 event=0xc2,ch_mask=0x10,fc_mask=0x04,umask=0x03 Clockticks of the power control unit (PCU). Unit: uncore_pcu Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis ocr.l1wb_m.l3_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0800 Counts the number of BACLEARS due to an indirect branch baclears.uncond event=0xb7,period=100003,umask=0x1,offcore_rsp=0x802184000000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2002184000000 This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS bus_lock.cycles_other_block ocr.demand_data_and_l1pf_rd.local_dram ocr.demand_data_rd.outstanding ocr.demand_rfo.outstanding event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000000010000 Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter cycles_div_busy.any event=0x3,period=1000003,umask=0x4 event=0x3,period=1000003,umask=0x2 topdown_fe_bound.branch_detect Counts the number of x87 uops retired, includes those in MS flows (Precise event) event=0x35,umask=0xC8A7FF01 TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_hit_drd_opt_pref Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault event=0x3,period=1000003,umask=0x8 Average per-core data access bandwidth to the L3 cache [GB / sec]. Unit: cpu_core Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]. Unit: cpu_core Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation Average Frequency Utilization relative nominal frequency. Unit: cpu_atom Cycles_per_Demand_Load_DRAM_Hit MemLoadPKI Retired load instructions missed L1 cache as data sources Supports address when precise (Precise event). Unit: cpu_core Retired load instructions missed L3 cache as data sources Supports address when precise (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x17 Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops. Unit: cpu_atom Taken branch instructions retired (Precise event). Unit: cpu_core int_vec_retired.128bit event=0xe7,period=1000003,umask=0x20 Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder. Unit: cpu_core topdown.bad_spec_slots This event is deprecated. Refer to new event UOPS_RETIRED.STALLS. Unit: cpu_core unc_m_dram_thermal_hot ACT command for a read request sent to DRAM. Unit: uncore_imc Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. Unit: uncore_arb event=0x26,period=200003,umask=0x2 ASSISTS.SSE_AVX_MIX FP_ARITH_DISPATCHED.PORT_1 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x84002380 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster ocr.write_estimate.memory Counts cycles during which the reservation station (RS) is empty for this logical processor Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load UOPS_DECODED.DEC0_UOPS event=0x3,umask=0x0000000001 unc_m_pre_count.pgt_pch0 event=0x5,umask=0x0000000080 Read and Write Requests; Writes Remote. Unit: uncore_cha Valid Flits Sent : Slot 2. Unit: uncore_upi event=0x2,umask=0x0000000010 event=0x2,umask=0x0000000097 Valid Flits Received : Data. Unit: uncore_upi event=0x32,umask=0x0000000004 FAF occupancy. Unit: uncore_irp event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000080 TOR Inserts; All Snoops from Remote. Unit: uncore_cha TOR Inserts; All from Local IA. Unit: uncore_cha event=0x35,umask=0x00C001FF08 unc_cha_tor_inserts.io_rfo event=0x35,umask=0x00c887ff01 event=0x35,umask=0x00c8a7ff01 unc_cha_tor_occupancy.io_miss_rfo unc_cha_tor_occupancy.irq_non_ia unc_cha_tor_occupancy.prq_non_iosf event=0x36,umask=0x00C000FF01 unc_cha_tor_occupancy.rem_snps event=0x36,umask=0x00C001FFC8 unc_cha_tor_occupancy.ia_hit_drd_pref TOR Occupancy; CRd Pref misses from local IA. Unit: uncore_cha event=0x36,umask=0x00c803fd04 TOR Occupancy; DRd Opt from local IA. Unit: uncore_cha event=0x36,umask=0x00c8077e01 event=0x35,umask=0x00CC47FD01 event=0x35,umask=0x00C867FF01 event=0x35,umask=0x00C8668A01 TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC. Unit: uncore_cha event=0x35,umask=0x00C8670601 unc_cha_tor_inserts.ia_wcil event=0x36,umask=0x00cc47fd01 Indirect Branch Prediction for potential multi-target branch (speculative) ic_fw32 l2_cache_req_stat.ls_rd_blk_l_hit_x event=0x64,umask=0x02 l3_lookup_state.all_l3_req_typs event=0x4,umask=0xff ex_ret_cops ex_ret_brn_resync MMX instructions ex_div_busy Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipes fp_sched_empty fp_retired_ser_ops.sse_bot_ret ls_tablewalker.iside Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailable data_fabric Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel event=0x59,umask=0x02 event=0xae,umask=0x80 de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss) ls_sw_pf_dc_fills.lcl_l2 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 2 available op_cache_fetch_miss_ratio d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses) ls_pref_instr_disp.all event=0x4b,umask=0x07 Software prefetch data cache fills from cache of another CCX in a different NUMA node ls_hw_pf_dc_fills.alternate_memories event=0x70,umask=0x04 l2_pf_hit_l2.l1_stride event=0x72,umask=0x08 l3_lookup_state.all_coherent_accesses_to_l3 Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node. Unit: amd_l3 event=0x21f,umask=0x7ff Write data beats (64 bytes) for local processor at Coherent Station (CS) 8 event=0x1df,umask=0xbfe event=0xdf,umask=0xbff event=0x25f,umask=0xbff remote_socket_upstream_write_beats_iom0 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 7 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 4 remote_socket_inf1_inbound_data_beats_ccm1 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 4 remote_socket_inf1_outbound_data_beats_ccm6 event=0xbdf,umask=0xf3e fp_ret_x87_fp_ops.mul_ops event=0xa,umask=0xf0 event=0xb,umask=0x01 Retired SSE and AVX integer multiply ops event=0xb,umask=0x80 fp_pack_ops_retired.fp256_sqrt packed_int_op_type.int128_shift event=0x94,umask=0x07 In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread bad_speculation_mispredicts backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)) all_l1_data_cache_fills dram_write_data_for_remote_processor umc_activate_cmd_rate FP_DISPATCHED_FPU_OPS DC_DISPATCHED_PREFETCH_INSTRUCTIONS FR_RETIRED_BRANCHES L1_DCACHE_NEON_CACHEABLE PRED_BRANCH_PRED_TAKEN CYCLES_STALLED_NEON_MRC EVENT_60H EVENT_82H EVENT_A0H PLE_REQUEST_PROGRAMMED L1I_CACHE_REFILL BR_PRED EVENT_10BH EVENT_153H EVENT_162H EVENT_171H EVENT_175H EVENT_187H EVENT_18AH EVENT_192H EVENT_1AEH EVENT_1BCH EVENT_1E6H EVENT_1FCH EVENT_23DH EVENT_286H EVENT_2A6H EVENT_2ADH EVENT_2EDH EVENT_2F5H EVENT_320H EVENT_337H EVENT_353H EVENT_367H EVENT_377H EVENT_38CH EVENT_3C3H EVENT_3F1H UNALIGNED_LDST_SPEC BR_IMMED_SPEC hnf_sf_hit hni_pcie_serialization rnd_rdb_replay cxra_req_chain_avg_len cxla_rx_tlp_link1 clkdiv2_read_depth BRANCH_LINK_STAC_PREDICTED ITLB_HW_TABLE_SEARCH_CYCLES TOUCH_ALIAS LSU_LMQ_FULL_STALL FP_DENORMALIZED_RESULT VTQ_RESUMES_DUE_TO_CTX_CHANGE LSU_COMPLETES_FP_STORE_SINGLE STWCX_INSTR_COMPLETED L1_DATA_LOAD_MISS_CYCLES BUS_RETRY_DUE_TO_L1_RETRY MARKED_GROUP_COMPLETED BTB_HITS_PSEUDO_HITS CYCLES_SU2_SCHED_STALLED PART2_MISALIGNED_CACHE_ACCESS PMC2_OVERFLOW L2_CACHE_ACCESSES ic-fill nonpostwrszbyte buffer-release tsc PPC970 AMD_K7 GENERIC TS name: %s
mem_load_l3_miss_retired.remote_hitm {"type": "pmcallocate" {"type": "proccsw" {"type": "map_in" TmaL1_SMT INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL 1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY 1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY L3MPKI ( cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CPU_CLK_UNHALTED.THREAD C6 residency percent per core C7_Core_Residency l2_trans.all_pf mem_uops_retired.stlb_miss_loads Cacheable and noncachaeble code read requests event=0xb0,period=100003,umask=0x1 fp_arith_inst_retired.128b_packed_double Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xca,period=100003,umask=0x8 Cycles with less than 3 uops delivered by the front end hle_retired.aborted_misc1 Number of times we entered an HLE region
does not count nested transactions This event counts loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) tx_exec.misc1 Unfriendly TSX abort triggered by a vzeroupper instruction event=0x54,period=2000003,umask=0x4 Unhalted core cycles when the thread is in ring 0 Cycles when divider is busy executing divide operations br_inst_exec.taken_conditional Taken speculative and retired macro-conditional branch instructions excluding calls and indirects This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: BDW98 (Must be precise) br_inst_retired.near_return This event counts taken speculative and retired mispredicted macro conditional branch instructions This event counts the number of mispredicted ret instructions retired.(Precise Event) event=0x3c,period=2000003,umask=0x1 event=0,period=2000003,umask=0x3 event=0x87,period=2000003,umask=0x1 This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased event=0x58,period=1000003,umask=0x1 Cycles at least 2 micro-op is executed from any thread on physical core Cycles at least 3 micro-op is executed from any thread on physical core This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread MMIO reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox event=0x35,umask=0x3,filter_opc=0x190 llc_misses.pcie_read llc_references.streaming_full unc_h_requests.reads_local event=0x21,umask=0x8 power_state_occupancy.cores_c0 % Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip. Unit: uncore_pcu event=0x6 event=0x8,period=2000003,umask=0x60 Load operations that miss the first DTLB level but hit the second and do not cause page walks itlb_misses.walk_completed_1g page_walker_loads.dtlb_l1 Number of DTLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) offcore_response.all_pf_data_rd.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020120 offcore_response.all_rfo.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0004 offcore_response.demand_code_rd.supplier_none.snoop_hitm offcore_response.demand_data_rd.supplier_none.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010002 offcore_response.other.l3_hit.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0010 offcore_response.pf_l3_code_rd.l3_hit.snoop_hit_no_fwd offcore_response.pf_l3_rfo.l3_hit.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020100 Randomly selected loads with latency value being above 8 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) offcore_response.all_data_rd.l3_miss.snoop_not_needed offcore_response.all_pf_rfo.l3_hit.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000120 offcore_response.corewb.l3_miss_local_dram.snoop_hitm offcore_response.corewb.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.corewb.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000001 offcore_response.other.l3_miss.snoop_miss offcore_response.other.l3_miss_local_dram.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104008000 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000020 offcore_response.pf_l3_data_rd.l3_hit.snoop_non_dram offcore_response.all_reads.llc_miss.remote_hitm offcore_response.all_requests.llc_miss.any_response l2_dbus_busy_rd.self l2_ifetch.self.s_state l2_ld.self.prefetch.s_state event=0x2d,period=200000,umask=0x41 event=0x24,period=200000,umask=0x40 l2_lock.self.mesi event=0x27,period=200000,umask=0x40 Cycles no L2 cache requests are pending l2_reject_busq.self.any.e_state event=0x2e,period=200000,umask=0x72 Floating point assists SIMD assists invoked simd_comp_inst_retired.scalar_double event=0xca,period=2000000,umask=0x8 event=0xc7,period=2000000,umask=0x1 event=0xb0,period=2000000,umask=0x80 Floating point computational micro-ops executed event=0x7,period=200000,umask=0x88 event=0x7,period=200000,umask=0xf Bus queue is empty event=0x6e,period=200000,umask=0x40 bus_trans_def.self event=0x77,period=200000,umask=0x2b event=0x77,period=200000,umask=0xb event=0x88,period=2000000,umask=0x8 cpu_clk_unhalted.core Core cycles when core is not halted Divide operations retired event=0x8,period=200000,umask=0x7 event=0xc,period=2000000,umask=0x3 page_walks.d_side_cycles event=0xd1,period=200003,umask=0x80 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_needed offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwd Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_reads.l2_miss.any event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600004000 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.partial_writes.l2_miss.any Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.any misalign_mem_ref.load_page_split event=0xc4,period=200003 Retired taken branch instructions (Precise event capable) (Must be precise) event=0xc4,period=200003,umask=0xeb event=0xc4,period=200003,umask=0xfe Core cycles when core is not halted (Fixed event) Reference cycles when core is not halted (Fixed event) uops_retired.ms event=0x81,period=200003,umask=0x4 Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss Supports address when precise (Must be precise) Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010004 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.any_response Counts all L2 HW prefetcher requests Counts the number of store RFO requests that hit the L2 cache Offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 offcore_response.pf_l2_code_rd.l3_hit.any_response Counts cycles DSB is delivered four uops. Set Cmask = 4 This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis Spec update: HSD135 offcore_response.all_rfo.l3_miss.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00002 Instructions retired from execution Spec update: HSD140, HSD143 The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use Cycles per core when uops are executed in port 6 event=0x8,period=100003,umask=0x80 Completed page walks due to store misses in one or more TLB levels of 4K page structure Misses at all ITLB levels that cause page walks Number of ITLB page walker loads that hit in the L1+FB Count number of STLB flush attempts Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: HSM30 (Precise event) event=0x24,period=200003,umask=0x20 mem_load_uops_llc_hit_retired.xsnp_miss Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Number of DSB to MITE switches Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles Counts demand data reads that miss the LLC and the data returned from dram event=0x14,cmask=1,edge=1,period=100003,umask=0x4 Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides event=0x34,umask=0x01 LLC lookup request that access cache and found line in S-state. Unit: uncore_cbox LLC lookup request that access cache and found line in E-state or S-state. Unit: uncore_cbox Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_l2_data_rd.llc_hit.hit_other_core_no_fwd offcore_response.all_code_rd.llc_miss.remote_hit_forward Counts all demand & prefetch data reads that hits the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6004003f7 Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram llc_misses.itom_write Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode.streaming_partial. Unit: uncore_cbox ItoM write hits (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.opcode.itom_write_hit. Unit: uncore_cbox unc_q_txl_flits_g0.data unc_p_freq_band0_transitions (UNC_P_FREQ_MAX_CURRENT_CYCLES / UNC_P_CLOCKTICKS) * 100. This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an br_misp_exec.taken_direct_near_call Increments the number of flags-merge uops in flight each cycle resource_stalls2.bob_full Memory page activates. Unit: uncore_imc Load misses at all DTLB levels that cause completed page walks Counts all the store micro-ops retired This event counts the number of store micro-ops retired Counts the number of load micro-ops retired that miss in the L2 Supports address when precise (Precise event) event=0x4,period=200003,umask=0x10 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000083091 offcore_response.any_pf_l2.l2_hit_far_tile_m offcore_response.any_read.l2_hit_far_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010008000 Counts demand code reads and prefetch code reads that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080001 Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts L1 data HW prefetches that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000402000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400040 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000020 Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.uc_code_reads.l2_hit_near_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800044 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181803091 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800070 offcore_response.any_read.mcdram_near Counts Demand cacheable data write requests that accounts for responses from DDR (local and far) offcore_response.demand_code_rd.mcdram event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800002 offcore_response.pf_l2_rfo.ddr_far offcore_response.pf_software.mcdram_near offcore_response.uc_code_reads.mcdram_far Counts the number of unhalted reference clock cycles This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists event=0x5,edge=1,period=100003,umask=0x2 l1d.repl L1 data cache read in M state event=0x26,period=200000,umask=0xff L2 data prefetches in the I state (misses) event=0x24,period=200000,umask=0xc0 l2_transactions.ifetch mem_inst_retired.latency_above_threshold_32 event=0xcb,period=10000,umask=0x10 mem_load_retired.other_core_l2_hit_hitm offcore_response.any_data.llc_hit_other_core_hit offcore_response.any_request.llc_hit_no_other_core Offcore requests satisfied by a remote cache Offcore writebacks to the LLC and not found in a sibling core offcore_response.corewb.local_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F77 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x877 Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit All offcore demand data requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0x804 Offcore demand RFO requests satisfied by the LLC or local DRAM offcore_response.other.remote_cache_hitm offcore_response.pf_data_rd.io_csr_mmio Offcore prefetch data reads satisfied by the LLC and not found in a sibling core offcore_response.pf_data_rd.local_cache_dram offcore_response.pf_ifetch.llc_hit_other_core_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x440 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x220 Offcore prefetch requests satisfied by the IO, CSR, MMIO unit fp_comp_ops_exe.sse_double_precision Offcore code reads that missed the LLC Offcore requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF808 offcore_response.data_ifetch.any_dram Offcore code or data read requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF833 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6003 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6020 br_inst_exec.indirect_non_call Mispredicted return branches executed event=0xc0,period=2000000,umask=0x2 Retired floating-point operations (Precise Event) rat_stalls.any Other Resource related stall cycles ssex_uops_retired.vector_integer event=0xd1,period=2000000,umask=0x4 event=0xb1,cmask=1,inv=1,period=2000000,umask=0x40 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080004 offcore_response.demand_code_rd.l3_hit_m.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C0001 offcore_response.demand_data_rd.l3_hit_s.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C0002 offcore_response.demand_rfo.l3_hit_m.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000048000 event=0xc6,period=100007,umask=0x1,frontend=0x400806 Number of times an HLE execution aborted due to hardware timer expiration Demand Data Read requests who miss L3 cache offcore_response.demand_code_rd.l3_hit_e.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000100004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C0002 This event counts both direct and indirect near call instructions retired Spec update: SKL091 (Precise event) Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path event=0xa6,period=2000003,umask=0x40 exe_activity.exe_bound_0_ports inst_decoded.decoders event=0xd,period=2000003,umask=0x1 Loads blocked due to overlapping with a preceding store that cannot be forwarded Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased Memory_Data_TLBs IpDSB_Miss_Ret 1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY ( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.THREAD ) Stores that miss the DTLB and hit the STLB Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake Counts streaming store that miss L2 Store address buffer full ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Must be precise) This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_llc_code_rd.llc_hit.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel 64 and IA-32 Architectures Optimization Reference Manual for more information offcore_requests.demand.read_code REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_RFO and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5070 Super Queue LRU hints sent to LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x30ff offcore_response.corewb.any_dram_and_remote_fwd REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf801 offcore_response.demand_ifetch.any_dram_and_remote_fwd snoopq_requests_outstanding.code event=0xb0,period=100000,umask=0x20 Offcore data reads, RFOs, and prefetches that HITM in a remote cache Retired load instructions which data sources missed L3 but serviced from local DRAM Supports address when precise (Precise event) event=0xd3,period=100007,umask=0x8 Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0490 offcore_response.all_pf_rfo.l3_hit.no_snoop_needed OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l2_data_rd.l3_hit.no_snoop_needed offcore_response.pf_l2_rfo.l3_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800122 Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000020 Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly write requests to memory controller. Unit: uncore_imc event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x04,ch_mask=0x1f unc_cha_llc_victims.total_s event=0x37,umask=0x04 RspIFwd Snoop Responses Received. Unit: uncore_cha unc_cha_snoop_resp.rsp_fwd_wb PCIe Completion Buffer Inserts of completions with data: Part 0-3. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit. Unit: uncore_iio unc_iio_txn_req_of_cpu.mem_read.part1 Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller) Data Response packets that go direct to Intel UPI. Unit: uncore_upi Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200491 ocr.all_data_rd.l3_hit_m.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040491 ocr.all_pf_data_rd.l3_hit_f.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100490 ocr.all_pf_rfo.l3_hit_e.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C07F7 ocr.all_reads.l3_hit_f.hit_other_core_no_fwd OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080122 ocr.all_rfo.l3_hit_f.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200122 ocr.all_rfo.l3_hit_m.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040122 ocr.demand_code_rd.l3_hit_f.any_snoop Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP ocr.demand_code_rd.l3_hit_m.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100001 Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD ocr.other.l3_hit_e.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400208000 ocr.other.l3_hit_s.hit_other_core_fwd ocr.pf_l1d_and_sw.l3_hit_e.snoop_miss ocr.pf_l1d_and_sw.l3_hit_m.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040400 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100020 ocr.pf_l3_data_rd.l3_hit.snoop_miss Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.all_data_rd.l3_hit_f.hitm_other_core offcore_response.all_data_rd.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE offcore_response.all_pf_rfo.l3_hit_m.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020120 offcore_response.all_rfo.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.all_rfo.l3_hit_s.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400122 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.demand_data_rd.l3_hit_f.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020400 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_e.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_hit_e.no_snoop_needed offcore_response.pf_l2_rfo.l3_hit_f.hitm_other_core offcore_response.pf_l2_rfo.l3_hit_f.no_snoop_needed offcore_response.pf_l2_rfo.l3_hit_s.no_snoop_needed offcore_response.pf_l3_data_rd.l3_hit_m.any_snoop offcore_response.pf_l3_data_rd.l3_hit_s.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_hit_m.any_snoop offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) ) Average 3DXP Memory Bandwidth Use for reads [GB / sec] Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events fp_arith_inst_retired2.128bit_packed_bf16 fp_arith_inst_retired2.512bit_packed_bf16 Intel AVX-512 computational 256-bit packed BFloat16 instructions retired event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000491 OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.all_pf_data_rd.l3_miss_local_dram.any_snoop OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C0007F7 OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6040007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000122 ocr.all_rfo.l3_miss_remote_hop1_dram.any_snoop ocr.demand_data_rd.l3_miss.no_snoop_needed Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed ocr.other.l3_miss.any_snoop Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_miss.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS ocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core ocr.pf_l2_rfo.l3_miss.remote_hit_forward Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000080 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_none offcore_response.all_rfo.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED ocr.all_reads.pmm_hit_local_pmm.any_snoop Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP ocr.demand_rfo.pmm_hit_local_pmm.snoop_not_needed Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.other.supplier_none.any_snoop ocr.other.supplier_none.hit_other_core_no_fwd ocr.other.supplier_none.snoop_miss Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP unc_m_pmm_read_latency unc_m_pmm_cmd1.rd Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability Counts demand data reads that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0020 Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent event=0x32,period=100003,umask=0x2 event=0xc7,period=100003,umask=0x1 Slots_Utilization event=0xc8,period=100003,umask=0x4 ocr.other.l3_miss Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response Counts return instructions retired (Precise event) event=0xd,period=500009,umask=0x1 Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly event=0xa4,period=10000003,umask=0x1 Number of uops executed on port 7 and 8 Counts cycles when at least 2 micro-ops are executed from any thread on physical core Branches;PGO MemoryTLB ocr.reads_to_core.l3_hit.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00400 ocr.demand_data_rd.remote_pmm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703000477 Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xd3,umask=0x02 unc_m_hclockticks event=0xea,umask=0x04 unc_cha_tor_inserts.ia TOR Occupancy : All requests from IO Devices. Unit: uncore_cha unc_cha_tor_occupancy.io_hit unc_cha_tor_inserts.io_miss_itom event=0x35,umask=0xC897FE01 event=0x35,umask=0xC887FF01 TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0xC8F3FF04 event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x80 event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x01 Multi-socket cacheline Directory Lookups : Found in any state. Unit: uncore_m2m event=0x2d,umask=0x08 unc_u_clockticks TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory. Unit: uncore_cha Counts the number of load uops retired that hit in the L2 cache Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3001F803C0000 Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request ocr.demand_data_and_l1pf_rd.l3_hit.snoop_miss Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded ocr.hwpf_l2_data_rd.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001F803C0000 Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request Counts the number of BACLEARS due to a return branch ocr.hwpf_l2_code_rd.l3_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000470 This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM ocr.hwpf_l2_code_rd.dram event=0xe8,period=200003 Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter topdown_be_bound.all event=0x74,period=1000003,umask=0x4 Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS event=0x71,period=1000003,umask=0x8 topdown_fe_bound.frontend_latency Counts the number of integer divide uops retired (Precise event) TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 Counts the number of page walks outstanding in the page miss handler (PMH) for loads every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault event=0x85,period=200003,umask=0x8 Counts the number of memory retired ops that missed in the second level TLB Supports address when precise (Precise event) Counts the number of store ops retired that miss in the second level TLB Supports address when precise (Precise event) Counts the number of load ops retired that hit in DRAM Supports address when precise Average number of Uops issued by front-end when it issued something. Unit: cpu_core Average data fill bandwidth to the L2 cache [GB / sec]. Unit: cpu_core Counts the number of issue slots that were not consumed by the backend due to frontend stalls. Unit: cpu_atom Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Unit: cpu_atom mem_load_completed.l1_miss_any Retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event). Unit: cpu_core Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1 Supports address when precise (Precise event). Unit: cpu_core event=0xe5,period=1000003,umask=0x3 Retired memory uops for any access. Unit: cpu_core fp_arith_dispatched.port_1 Retired Instructions who experienced Instruction L2 Cache true miss (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x610006 Uops not delivered by IDQ when backend of the machine is not stalled. Unit: cpu_core Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Unit: cpu_atom mem_trans_retired.store_sample Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility Supports address when precise (Must be precise). Unit: cpu_core event=0xc1,period=100003,umask=0x4 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10800 Counts the number of unhalted core clock cycles. Unit: cpu_atom machine_clears.mrn_nuke This event is deprecated. Refer to new event ARITH.DIV_ACTIVE. Unit: cpu_core arith.div_active Taken conditional branch instructions retired (Precise event). Unit: cpu_core event=0xad,period=500009,umask=0x80 False dependencies in MOB due to partial compare on address. Unit: cpu_core event=0x3,period=100003,umask=0x88 unc_m_act_count_wr Loads that miss the DTLB and hit the STLB. Unit: cpu_core event=0x12,period=100003,umask=0x4 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1830004477 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD event=0x3,umask=0x0000000008 DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0. Unit: uncore_imc event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000002 event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000001 Read requests from a remote socket. Unit: uncore_cha event=0x35,umask=0x00c8177e01 TOR Inserts for DRd Pref misses from local IA targeting remote memory. Unit: uncore_cha unc_upi_txl_basic_hdr_match.ncs event=0x31,umask=0x0000000001 event=0x31,umask=0x0000000002 RxQ Flit Buffer Bypassed : Slot 2. Unit: uncore_upi event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000004 event=0xc0,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000001 event=0xc1,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000004 event=0x5d,umask=0x000000000a M3UPI CMS Clockticks. Unit: uncore_m3upi event=0x35,umask=0x00c001ff01 event=0x35,umask=0x00ccc7fd01 event=0x35,umask=0x00c001ff04 unc_cha_tor_inserts.loc_all unc_cha_tor_inserts.rem_snps TOR Inserts; ItoM hits from local IO. Unit: uncore_cha TOR Inserts; CRd from local IA. Unit: uncore_cha unc_cha_tor_occupancy.all unc_cha_tor_occupancy.irq_ia unc_cha_tor_occupancy.ia_miss_drd_opt_pref event=0x36,umask=0x00c817ff01 All LLC lines in E state that are victimized on a fill. Unit: uncore_cha event=0x35,umask=0x00c837fd01 event=0x35,umask=0x00c8f3fd04 unc_cha_tor_inserts.ia_llcprefcode TOR Inserts; LLCPrefCode from local IA. Unit: uncore_cha TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_specitom event=0x36,umask=0x00c877de01 unc_cha_tor_occupancy.ia_miss_wcilf_pmm event=0x36,umask=0x00c8668601 event=0x64,umask=0x80 event=0x6d,umask=0x01 The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction ex_ret_near_ret Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2 event=0x187,umask=0x38 Total number uOps assigned to all fpu pipes fpu_pipe_assignment.total2 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2 Add/subtract Ops event=0x3,umask=0x04 ls_misal_accesses de_dis_dispatch_token_stalls0.agsq_token_stall remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3 The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB page Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores ls_locks.non_spec_lock ls_pref_instr_disp.prefetch Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die. From DRAM (home node local) event=0x5a,umask=0x01 event=0xaa,umask=0x02 bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k op_cache_hit_miss.all_op_cache_accesses Op Cache Miss. Counts Op Cache micro-tag hit/miss events event=0x44,umask=0x10 event=0x5f event=0x44,umask=0x48 event=0x44,umask=0x50 l1_data_cache_fills_all ls_any_fills_from_sys.far_cache ls_any_fills_from_sys.all_dram_io event=0x52,umask=0x03 l2_request_g1.all_dc l2_pf_hit_l2.l2_up_down event=0x71,umask=0x10 event=0x71,umask=0x40 Instruction cache lines (64 bytes) fulfilled from system memory or another cache Average sampled latency when data is sourced from DRAM in the same NUMA node. Unit: amd_l3 l3_xi_sampled_latency_requests.ext_near Cycles with no retire for any reason event=0x25f,umask=0x7fe Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1 local_socket_inf1_inbound_data_beats_ccm3 event=0x5de,umask=0x7ff Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 6 event=0x41e,umask=0xbfe remote_socket_inf1_outbound_data_beats_ccm4 local_socket_outbound_data_beats_link2 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 3 Retired SSE and AVX bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing Retired SSE and AVX serializing ops of all types fp_ops_retired_by_width.x87_uops_retired fp_ops_retired_by_width.pack_128_uops_retired Retired scalar floating-point square root ops event=0xa,umask=0x40 sse_avx_ops_retired.sse_avx_sub Retired SSE, AVX and MMX integer ops of all types event=0xd,umask=0x04 event=0xd,umask=0x09 event=0xd,umask=0x0a packed_int_op_type.int128_logical event=0xd,umask=0x0d L1 DTLB misses with L2 DTLB hits for 1G pages de_src_op_disp.loop_buffer Number of ops dispatched to the integer execution unit Number of cycles dispatch is stalled for store queue tokens In each cycle counts ops unable to dispatch because of back-end stalls retiring_fastpath All L2 cache hits Average L3 read miss latency (in core clocks) FR_RETIRED_RESYNCS L1_DCACHE_ACCESS EVENT_28H EVENT_73H EVENT_90H EVENT_94H EVENT_C0H EVENT_C4H EVENT_EBH INSTR_MICRO_TLB_MISS_STALL EVENT_111H EVENT_14AH EVENT_15DH EVENT_1A4H EVENT_1DFH EVENT_233H EVENT_2ABH EVENT_2B0H EVENT_2D9H EVENT_2F0H EVENT_328H EVENT_354H EVENT_394H EVENT_3ADH EVENT_3B6H EVENT_3DBH L2D_CACHE_ST L3D_CACHE_ALLOCATE sbsx_wr_req sbsx_wdb_occ_cnt_ovfl rnd_s1_rdata_beats rni_txreq_flits_retried cxla_rx_tlp_link2 cxla_rx_cxs_link0 clkdiv2_training_request clkdiv2_bk_open_tracker CYCLE INSTR_COMPLETED L1_DATA_SNOOPS CACHE_INHIBITED_STORES SS_SM_INSTR_COMPLETED CYCLES_TWO_INSTR_COMPLETED STORE_MERGE_GATHER DSSALL_INSTR_COMPLETED L2_STORE_HITS L3_LOAD_HITS BORDQ_FULL DATA_L1_CACHE_CASTOUTS EXT_INPU_INTR_LATENCY_CYCLES PMC1_OVERFLOW L2_CACHE_ALLOCATIONS DVT2_DETECTED store dimm-turnaround AMD_K8 true ls_not_halted_cyc l3_comb_clstr_state.request_miss BRANCH_INSTRUCTION_RETIRED {"type": "pmcdetach" GenuineIntel-6-47 GenuineIntel-6-2A GenuineIntel-6-8F Frontend_Bound This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound Instructions per FP Arithmetic instruction (lower number means higher occurrence rate) INST_RETIRED.ANY Summary;TmaL1 L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES L3 cache true misses per kilo instruction for retired demand loads HPC;Summary Fraction of cycles where both hardware Logical Processors were active C2_Pkg_Residency L1D data line replacements l2_lines_in.e Demand requests to L2 cache event=0x24,period=200003,umask=0x30 This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) Retired load uop whose Data Source was: Remote cache HITM (Precise Event) Supports address when precise. Spec update: BDE70 This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) Supports address when precise (Precise event) event=0xf4,period=100003,umask=0x10 fp_arith_inst_retired.scalar_double baclears.any hle_retired.commit mem_trans_retired.load_latency_gt_128 Number of times the TSX watchdog signaled an RTM abort event=0x5d,period=2000003,umask=0x1 tx_exec.misc3 Speculative and retired macro-unconditional branches excluding calls and indirects Not taken macro-conditional branches event=0x3c,period=2000003,umask=0x2 event=0xa3,cmask=4,period=2000003,umask=0x4 Counts number of cycles nothing is executed on any execution port Execution stalls while memory subsystem has an outstanding load event=0,period=2000003,umask=0x1 This is a precise version (that is, uses PEBS) of the event that counts instructions retired Spec update: BDM11, BDM55 (Must be precise) This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch event=0x4c,period=100003,umask=0x1 uops_dispatched_port.port_4 uops_dispatched_port.port_7 event=0xb1,inv=1,period=2000003,umask=0x2 uops_executed.cycles_ge_3_uops_exec uops_executed_port.port_0 uops_issued.single_mul event=0xc2,period=2000003,umask=0x1 event=0 unc_c_llc_lookup.any llc_misses.mmio_write llc_references.code_llc_prefetch event=0x36,umask=0x3,filter_opc=0x182 read requests to home agent. Unit: uncore_ha llc_misses.mem_read llc_misses.mem_write Cycles all ranks are in critical thermal throttle. Unit: uncore_imc This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu event=0x80,occ_sel=2 unc_p_freq_max_limit_thermal_cycles event=0x49,period=100003,umask=0xe Store misses in all DTLB levels that cause completed page walks (2M/4M) Spec update: BDM69 event=0xbc,period=2000003,umask=0x21 event=0xbd,period=100007,umask=0x20 Retired store uops that split across a cacheline boundary Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0240 Counts all prefetch data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0120 offcore_response.all_pf_rfo.l3_hit.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020122 offcore_response.corewb.l3_hit.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0008 offcore_response.demand_data_rd.supplier_none.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000028000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020040 offcore_response.pf_l2_code_rd.supplier_none.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020040 Counts all prefetch (that bring data to L2) RFOs have any response type offcore_response.all_pf_code_rd.l3_hit.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0240 offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_miss offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000090 offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.demand_code_rd.l3_miss.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000002 offcore_response.other.l3_hit.snoop_non_dram offcore_response.other.l3_miss_local_dram.snoop_miss offcore_response.pf_l2_data_rd.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000020 L3 Lookup read request that access cache and found line in E or S-state Retired load uop whose Data Source was: forwarded from remote cache Supports address when precise. Spec update: BDE70 (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0604000122 L1 Data Cacheable reads and writes L1 Data reads and writes event=0x2c,period=200000,umask=0x42 event=0x29,period=200000,umask=0x72 l2_lines_in.self.demand event=0x30,period=200000,umask=0x44 l2_reject_busq.self.demand.s_state simd_inst_retired.vector Saturated arithmetic instructions retired SIMD saturated arithmetic micro-ops executed event=0xb3,period=2000000,umask=0x1 cycles_icache_mem_stalled.icache_mem_stalled event=0x80,period=200000,umask=0x1 event=0x5,period=200000,umask=0x89 prefetch.software_prefetch Outstanding cacheable data read bus requests duration bus_trans_p.self event=0x66,period=200000,umask=0x40 Memory cluster signals to block micro-op dispatch for any reason ext_snoop.all_agents.clean All macro unconditional branch instructions, excluding calls and indirects Micro-op reissues on a store-load collision (At Retirement) itlb.misses Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks Supports address when precise (Must be precise) Counts load uops retired that hit in the L2 cache Supports address when precise (Must be precise) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x36000032b7 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000022 Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwd Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.any Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000044800 Counts data cache lines requests by software prefetch instructions that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200001000 event=0xcb,period=200003,umask=0x2 br_inst_retired.all_taken_branches br_misp_retired.taken_jcc event=0xe,period=200003 Integer divide uops retired. (Precise Event Capable) (Must be precise) itlb.miss Load uops retired that missed the DTLB (Precise event capable) Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x12 Duration of page-walks in cycles event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000013091 Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received offcore_response.bus_locks.l2_miss.hitm_other_core event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000008 Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache This event counts each cache miss condition for references to the last level cache offcore_response.demand_data_rd.l3_hit.hitm_other_core ( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@) Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event) offcore_response.all_reads.l3_miss.local_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400002 This event counts cycles during which no instructions were executed in the execution stage of the pipeline An external snoop hits a modified line in some processor core. Unit: uncore_cbox Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory) ITLB misses that hit STLB (4K) Counts the number of Extended Page Table walks from the DTLB that hit in the L2 Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x083FC007F7 Counts any demand and L1 HW prefetch data load requests to L2 mem_load_uops_retired.llc_hit mem_load_uops_retired.llc_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x000107F7 event=0x11,period=2000003,umask=0x1 DSB Fill encountered > 3 DSB lines Loads with latency value being above 256 (Must be precise) Loads with latency value being above 8 (Must be precise) uops_dispatched_port.port_0_core Cycles which a Uop is dispatched on port 4 LLC lookup request that access cache and found line in M-state offcore_response.all_pf_data_rd.llc_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0090 Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC offcore_response.demand_data_rd.llc_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc00244 Counts demand data reads that miss in the LLC LLC misses for PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.miss_opcode.pcie_write. Unit: uncore_cbox PCIe non-snoop writes (partial). Derived from unc_c_tor_inserts.opcode.pcie_partial_write. Unit: uncore_cbox Read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc event=0xc,edge=1 unc_p_freq_ge_2000mhz_transitions event=0xc5,period=400009,umask=0x10 This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers Counts the cycles of stall due to lack of load buffers (UNC_C_TOR_OCCUPANCY.MISS_ALL / UNC_C_CLOCKTICKS) * 100. offcore_response.any_data_rd.l2_hit_far_tile offcore_response.any_data_rd.l2_hit_far_tile_m Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000022 offcore_response.bus_locks.l2_hit_this_tile_e offcore_response.demand_rfo.l2_hit_near_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000014000 Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010040 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400020 offcore_response.pf_software.outstanding offcore_response.uc_code_reads.l2_hit_this_tile_m offcore_response.any_code_rd.ddr_far Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local Counts any Read request that accounts for responses from DDR (local and far) offcore_response.any_read.ddr_near offcore_response.any_read.mcdram_far offcore_response.partial_reads.non_dram offcore_response.partial_writes.ddr_near Counts all the retired locked loads. It does not include stores because we would double count if we count stores Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included L1 data cache read in E state l1d_cache_ld.i_state event=0x42,period=2000000,umask=0x8 event=0x28,period=100000,umask=0x2 l2_rqsts.prefetch_miss event=0xf0,period=200000,umask=0x2 Memory instructions retired above 512 clocks (Precise Event) event=0xb7,period=100000,umask=0x1,offcore_rsp=0x811 All offcore code reads Offcore code reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x80FF offcore_response.any_request.local_cache_dram Offcore request = all data, response = any cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1833 Offcore data reads, RFO's and prefetches that HIT in a remote cache Offcore demand data requests satisfied by the LLC and HIT in a sibling core offcore_response.demand_data_rd.any_location Offcore demand data reads that HIT in a remote cache Offcore demand code reads that HITM in a remote cache offcore_response.demand_rfo.any_cache_dram Offcore demand RFO requests satisfied by a remote cache offcore_response.other.io_csr_mmio offcore_response.pf_data.llc_hit_other_core_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1030 offcore_response.pf_data.remote_cache_hitm offcore_response.pf_data_rd.any_cache_dram offcore_response.pf_data_rd.remote_cache_hit All offcore prefetch code reads offcore_response.prefetch.remote_cache_dram event=0xf4,period=2000000,umask=0x10 store_blocks.at_ret fp_mmx_trans.to_mmx event=0x12,period=200000,umask=0x2 event=0xfd,period=200000,umask=0x8 Offcore data reads satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6044 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4008 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF877 offcore_response.data_in.any_llc_miss Offcore request = all data, response = any LLC miss Offcore demand data requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4003 offcore_response.demand_rfo.any_llc_miss Offcore demand RFO requests that missed the LLC offcore_response.pf_data_rd.any_llc_miss offcore_response.pf_ifetch.any_dram offcore_response.pf_ifetch.remote_dram Offcore prefetch RFO requests satisfied by any DRAM offcore_response.pf_rfo.local_dram offcore_response.prefetch.any_dram Thread responded HIT to snoop br_inst_exec.any Indirect return branches executed br_misp_exec.indirect_non_call br_misp_exec.non_calls br_misp_exec.taken lsd.active Flag stall cycles Uops executed on port 2 (core count) uops_executed.port3_core event=0xe,any=1,cmask=1,inv=1,period=2000000,umask=0x1 event=0xe,any=1,cmask=1,period=2000000,umask=0x1 uops_retired.macro_fused l2_lines_out.useless_pref Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100001 offcore_response.demand_rfo.l3_hit_e.any_snoop offcore_response.demand_rfo.supplier_none.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C8000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0108000 offcore_response.other.l4_hit_local_l4.any_snoop offcore_response.other.l4_hit_local_l4.spl_hit Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event) Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) event=0x83,period=200003,umask=0x2 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ hle_retired.aborted_events offcore_response.demand_data_rd.l3_miss.snoop_hitm offcore_response.demand_data_rd.l4_hit_local_l4.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000002 Core crystal clock cycles when the thread is unhalted Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch 100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) Mem;MemoryBW;Offcore Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses) Big_Code Big_Code_SMT ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680003091 Counts any request that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000004 Counts data cacheline reads generated by L2 prefetchers that miss L2 rehabq.ld_block_st_forward Loads blocked due to store forward restriction (Precise event) Stalls due to Memory ordering JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) Counts the number of mispredicted taken JCC branch instructions retired (Precise event) This event counts the number of load ops retired that had DTLB miss (Precise event) event=0xd4,period=100007,umask=0x2 offcore_response.all_pf_code_rd.llc_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10040 Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram Actually retired uops. (Precise Event - PEBS) (Precise event) offcore_requests.demand.rfo event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff11 REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.data_in.all_local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x750 offcore_response.pf_rfo.local_dram_and_remote_cache_hit REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf822 REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM event=0xb3,cmask=1,period=2000000,umask=0x2 itlb_misses.walk_cycles Offcore data reads, RFOs, and prefetches satisfied by the remote DRAM Counts all demand & prefetch data reads that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0122 Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram Counts demand data reads that miss the L3 and the data is returned from local dram Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram offcore_response.pf_l3_data_rd.l3_miss.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00100 Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes L2Evicts;Mem;Server unc_m_act_count.wr event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x04 event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x04 unc_iio_data_req_of_cpu.mem_write.part3 event=0x50,umask=0x20 unc_cha_rxc_irq1_reject.pa_match event=0x19,umask=0x80 event=0x3d,umask=0x02 PCIe Completion Buffer Inserts of completions with data: Part 3 event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x01 Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2. Unit: uncore_iio event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x02 event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x04 Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU. Unit: uncore_iio event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x08 unc_i_coherent_ops.rfo event=0x10,umask=0x8 BL Ingress (from CMS) Allocations. Unit: uncore_m2m unc_upi_rxl_flits.all_data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0491 OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0490 OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000407F7 ocr.all_rfo.l3_hit.hitm_other_core OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS ocr.all_rfo.l3_hit_s.snoop_miss Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE ocr.demand_code_rd.l3_hit_s.hit_other_core_no_fwd Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080002 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040002 ocr.demand_rfo.l3_hit_m.no_snoop_needed ocr.demand_rfo.l3_hit_s.no_snoop_needed Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD ocr.other.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100208000 ocr.other.l3_hit_m.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100400 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP ocr.pf_l3_data_rd.l3_hit.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080100 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400120 offcore_response.all_reads.l3_hit_e.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit_f.hitm_other_core offcore_response.all_rfo.l3_hit_s.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.demand_rfo.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400010 This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_hit_f.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000491 ocr.all_pf_rfo.l3_miss.hit_other_core_fwd OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000004 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000002 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.other.l3_miss_local_dram.hitm_other_core Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.pf_l1d_and_sw.l3_miss.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000020 ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_none ocr.pf_l3_data_rd.l3_miss.snoop_miss Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_miss_local_dram.snoop_none ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.all_data_rd.l3_miss.hitm_other_core offcore_response.all_data_rd.l3_miss.hit_other_core_fwd offcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss offcore_response.all_pf_data_rd.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.all_pf_rfo.l3_miss.hit_other_core_no_fwd offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.all_reads.l3_miss_local_dram.snoop_miss offcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE ocr.all_pf_rfo.any_response ocr.all_reads.supplier_none.hit_other_core_no_fwd ocr.all_rfo.supplier_none.snoop_miss ocr.demand_code_rd.pmm_hit_local_pmm.snoop_not_needed ocr.demand_code_rd.supplier_none.hit_other_core_fwd ocr.demand_data_rd.supplier_none.hit_other_core_no_fwd ocr.demand_rfo.any_response Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc Regular reads(RPQ) commands for Intel Optane DC persistent memory. Unit: uncore_imc All dirty line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc event=0x48,cmask=1,period=1000003,umask=0x1 event=0x24,period=200003,umask=0xc8 event=0xd0,period=1000003,umask=0x83 Counts retired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event) event=0xd1,period=1000003,umask=0x1 ocr.demand_rfo.l3_hit.snoop_sent ocr.hwpf_l2_rfo.l3_hit.snoop_not_needed event=0x60,period=1000003,umask=0x4 event=0xf4,period=100003,umask=0x4 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element ocr.hwpf_l2_rfo.local_dram Counts streaming stores that DRAM supplied the request event=0xc5,period=50021,umask=0x1 Cycle counts are evenly distributed between active threads in the Core event=0xa3,cmask=12,period=1000003,umask=0xc inst_retired.stall_cycles Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources event=0,period=10000003,umask=0x4 Number of uops executed on port 4 and 9 Branches;InsType ocr.demand_code_rd.l3_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000004 Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode UOPS_RETIRED.SLOTS / INST_RETIRED.ANY Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally core_snoop_response.i_hit_fse Hit snoop reply without sending the data, line invalidated event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703000002 ocr.hwpf_l3.remote Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode unc_m_rpq_inserts.pch1 unc_m_rpq_occupancy_pch1 event=0x50,umask=0x0c event=0x35,umask=0xC80FFE01 TOR Inserts : All requests from IO Devices that missed the LLC. Unit: uncore_cha TOR Inserts : ItoMs issued by IO Devices that Hit the LLC. Unit: uncore_cha TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x01 event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x04 unc_iio_txn_req_of_cpu.mem_write.part4 event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x04 unc_iio_txn_req_of_cpu.cmpd.part7 event=0xc2,ch_mask=0x40,fc_mask=0x04,umask=0x03 Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches event=0x34,period=200003,umask=0x38 Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hitm Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis Counts the number of hardware interrupts received by the processor ocr.all_code_rd.any_response Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) ocr.prefetches.any_response event=0x74,period=1000003,umask=0x40 Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC. Unit: uncore_cha PCIe Completion Buffer Inserts of completions with data : Part 0-7 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault event=0x49,period=2000003,umask=0x20 Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle Instructions Per Cycle (per Logical Processor). Unit: cpu_core 100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS Cycles with L1D load Misses outstanding. Unit: cpu_core event=0x44,period=200003,umask=0x1 mem_uop_retired.any DEMAND_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD. Unit: cpu_core event=0x40,period=100003,umask=0x1 Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core event=0x79,cmask=6,period=2000003,umask=0x4 Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled. Unit: cpu_core ld_head.pgwalk_at_ret event=0x5,period=1000003,umask=0xa0 Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles Supports address when precise (Must be precise). Unit: cpu_core event=0x2d,cmask=1,period=1000003,umask=0x1 Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS. Unit: cpu_atom Instruction decoders utilized in a cycle. Unit: cpu_core uops_decoded.dec0_uops Uops executed on ports 2, 3 and 10. Unit: cpu_core Cycles with retired uop(s). Unit: cpu_core event=0xc2,period=2000003,umask=0x4,frontend=0x8 Retirement slots used. Unit: cpu_core unc_m_dram_page_hit_rd unc_m_dram_page_empty_rd Number of page walks outstanding for a demand load in the PMH each cycle. Unit: cpu_core event=0x13,period=100003,umask=0x10 event=0x26,period=200003,umask=0x1 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x4003C4477 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00004 This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE Number of all retired NOP instructions DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre. Unit: uncore_imc unc_m_cas_count.pch1 event=0x35,umask=0x00cc43ff04 TOR Inserts for DRd misses from local IA targeting remote memory. Unit: uncore_cha event=0x2,umask=0x0000000047 unc_upi_rxl_flits.slot0 Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode. Unit: uncore_upi unc_upi_rxl_basic_hdr_match.ncb_opc event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000080 event=0x32,umask=0x0000000104 unc_m2m_tracker_occupancy.ch0 Tracker Occupancy : Channel 1. Unit: uncore_m2m Data Prefetches Dropped. Unit: uncore_m2m Prefetch CAM Inserts : XPT - All Channels. Unit: uncore_m2m : XPT - All Channels. Unit: uncore_m2m FlowQ Generated Prefetch. Unit: uncore_m3upi event=0x50,umask=0x0000000003 unc_cha_tor_inserts.evict TOR Inserts : IRQ - Non iA. Unit: uncore_cha TOR Inserts : All from Local IO. Unit: uncore_cha event=0x35 event=0x35,umask=0x00c88ffe01 unc_cha_tor_occupancy.snps_from_rem event=0x36,umask=0x00c817fd01 event=0x36,umask=0x00c807fd01 event=0x36,umask=0x00c001ff04 event=0x36,umask=0x0000000008 unc_cha_tor_occupancy.wbq TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field. Unit: uncore_cha TOR Occupancy : Just NonCoherent. Unit: uncore_cha event=0x36,umask=0x00c887fe01 TOR Occupancy; DRd Opt Pref from local IA. Unit: uncore_cha event=0x36,umask=0x00c80fff01 event=0x35,umask=0x00ccd7fe01 event=0x35,umask=0x00C8670A01 event=0x36,umask=0x00c8978601 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_remote_ddr unc_cha_tor_occupancy.ia_miss_crd_pref_remote unc_cha_tor_occupancy.ia_hit_itom event=0x36,umask=0x00cc23ff04 unc_cha_tor_occupancy.io_miss_itomcachenear bp_l1_btb_correct l2_request_g1.ls_rd_blk_c_s event=0x60,umask=0xf9 event=0x64,umask=0x40 Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L2 l3_comb_clstr_state.other_l3_miss_typs event=0x90,umask=0x00 The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts event=0xc4 event=0x1cf,umask=0x01 event=0,umask=0x02 All FLOPS L1 DTLB Miss or Reload off all sizes event=0x76 100% L2 Cache Hits from L1 Data Cache Misses (xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typs Mixed SSE/AVX Stalls The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB page bp_l1_tlb_miss_l2_tlb_miss Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS Total number uOps assigned to pipe 3 fp_ret_sse_avx_ops.mult_flops fp_disp_faults.ymm_spill_fault ls_refills_from_sys.ls_mabresp_rmt_dram Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die event=0x43,umask=0x01 Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) event=0xaa,umask=0xff Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Taken branch buffer resource stall Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed ls_misal_loads.ma4k event=0x59,umask=0x04 event=0x44,umask=0x03 l1_data_cache_fills_from_external_ccx_cache Demand data cache fills from extension memory Any data cache fills from cache of another CCX when the address was in the same NUMA node Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node L2 cache requests: instruction cache reads L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stream (fetch additional sequential lines into L2 cache) l2_pf_miss_l2_hit_l3.l1_stride L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stream (fetch additional sequential lines into L1 cache) l3_xi_sampled_latency.near_cache event=0x25f,umask=0x7ff event=0x8df,umask=0x7fe event=0x81f,umask=0xbfe Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 2 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 4 remote_socket_inf0_inbound_data_beats_ccm1 remote_socket_inf0_outbound_data_beats_ccm4 event=0xc9f,umask=0xf3e fp_ret_x87_fp_ops.all fp_ops_retired_by_width.scalar_uops_retired Retired scalar floating-point divide ops event=0xa,umask=0x20 fp_ops_retired_by_type.vector_cmp event=0xa,umask=0x70 Retired vector floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) sse_avx_ops_retired.sse_avx_sha Retired 128-bit packed floating-point ops of other types Retired 256-bit packed floating-point convert ops packed_int_op_type.int128_mac Retired 128-bit packed integer multiply-accumulate ops event=0xd,umask=0x06 packed_int_op_type.int128_cmp event=0xd,umask=0xff L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages de_no_dispatch_per_slot.no_ops_from_frontend Fraction of dispatched ops that did not retire Fraction of dispatch slots used by ops that retired backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete) backend_bound_cpu Execution-time branch misprediction ratio (non-speculative) L1 demand data cache fills from DRAM or MMIO in the same NUMA node remote_socket_upstream_write_beats_iom0 + remote_socket_upstream_write_beats_iom1 + remote_socket_upstream_write_beats_iom2 + remote_socket_upstream_write_beats_iom3 local_socket_inf0_inbound_data_beats_ccm0 + local_socket_inf1_inbound_data_beats_ccm0 + local_socket_inf0_inbound_data_beats_ccm1 + local_socket_inf1_inbound_data_beats_ccm1 + local_socket_inf0_inbound_data_beats_ccm2 + local_socket_inf1_inbound_data_beats_ccm2 + local_socket_inf0_inbound_data_beats_ccm3 + local_socket_inf1_inbound_data_beats_ccm3 + local_socket_inf0_inbound_data_beats_ccm4 + local_socket_inf1_inbound_data_beats_ccm4 + local_socket_inf0_inbound_data_beats_ccm5 + local_socket_inf1_inbound_data_beats_ccm5 + local_socket_inf0_inbound_data_beats_ccm6 + local_socket_inf1_inbound_data_beats_ccm6 + local_socket_inf0_inbound_data_beats_ccm7 + local_socket_inf1_inbound_data_beats_ccm7 remote_socket_outbound_data_from_cpu local_socket_outbound_data_beats_link0 + local_socket_outbound_data_beats_link1 + local_socket_outbound_data_beats_link2 + local_socket_outbound_data_beats_link3 + local_socket_outbound_data_beats_link4 + local_socket_outbound_data_beats_link5 + local_socket_outbound_data_beats_link6 + local_socket_outbound_data_beats_link7 Memory controller data bus utilization DC_L1_DTLB_MISS_AND_L2_DTLB_HIT IC_REFILL_FROM_SYSTEM MEM_READ L2_CACHE_ACCESS EVENT_49H EVENT_5AH EVENT_5BH EVENT_5DH EVENT_6AH EVENT_ABH EVENT_BBH EVENT_BFH EVENT_C8H EVENT_CEH EVENT_EEH L1D_CACHE_WB BR_IMMED_RETIRED EVENT_141H EVENT_14DH EVENT_17AH EVENT_19EH EVENT_235H EVENT_27EH EVENT_283H EVENT_2A2H EVENT_2A9H EVENT_2B3H EVENT_2CFH EVENT_2D8H EVENT_2E4H EVENT_2F2H EVENT_30CH EVENT_33CH EVENT_33DH EVENT_35FH EVENT_380H EVENT_385H EVENT_3DFH EVENT_3EAH EVENT_3F3H EXC_DABORT DTLB_WALK STREX_SPEC hnf_pocq_addrhaz hnf_txrsp_stall hni_rdt_wr_occ_cnt_ovfl rni_txreq_flits_replayed cxra_ext_rsp_stall cxla_rx_cxs_link2 cxla_avg_sz_rx_cxs_dw_beat clkdiv2_prank_turnaround_activate VIU1_INSTR_WAIT_CYCLES L1_DATA_SNOOP_HIT_CASTOUT FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY DST_STREAM_1_CACHE_LINE_FETCHES FXU0_IDLE_FXU1_IDLE FXU_MARKED_INSTR_FINISHED ADDER BRANCHES_FINISHED BTB_BRANCH_MISPRED_FROM_DIRECTION CYCLES_DECODE_STALLED CYCLES_BRANCH_ISSUE_STALLED DECORATED_STORES K8- exclusive modified tag-snoop sse-reclass-microfaults XSCALE PPC7450 INTEL_SANDYBRIDGE_XEON %s:
%s
{"type": "sysexit" %s, "pid": "%d", "start": "0x%016jx", "end": "0x%016jx"}
GenuineIntel-6-45 bdwde metrics IpFLOP l1d_pend_miss.fb_full This event counts L2 fill requests that access L2 cache event=0x63,period=2000003,umask=0x2 Retired load uops with L2 cache misses as data sources. Uses PEBS Supports address when precise (Precise event) This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM Cycles with any input/output SSE or FP assist event=0xca,period=100003,umask=0x4 icache.ifdata_stall This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ idq.all_dsb_cycles_any_uops idq.mite_uops event=0x79,period=2000003,umask=0x4 event=0x9c,cmask=4,period=2000003,umask=0x1 Number of times HLE aborted and was not due to the abort conditions in subevents 3-6 event=0xcd,period=1009,umask=0x1,ldlat=0x80 This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache tx_exec.misc2 br_inst_exec.taken_indirect_jump_non_call_ret event=0x88,period=200003,umask=0xa0 event=0x89,period=200003,umask=0xc1 Mispredicted conditional branch instructions retired. (Precise Event - PEBS) (Precise event) event=0xd,any=1,cmask=1,period=2000003,umask=0x3 rs_events.empty_cycles uops_dispatched_port.port_3 Cycles per thread when uops are executed in port 7 Cycles at least 1 micro-op is executed from any thread on physical core Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread Memory controller clock ticks. Unit: uncore_imc event=0x2,umask=0x4 Store misses that miss the DTLB and hit the STLB (4K) Store misses in all DTLB levels that cause completed page walks (1G) Spec update: BDM69 event=0xbc,period=2000003,umask=0x11 This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3) Supports address when precise. Spec update: BDM100 (Precise event) offcore_response.all_pf_code_rd.supplier_none.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020001 offcore_response.pf_l2_data_rd.l3_hit.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0200 offcore_response.pf_l3_code_rd.l3_hit.snoop_none offcore_response.pf_l3_code_rd.supplier_none.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0100 offcore_response.all_data_rd.l3_miss_local_dram.snoop_hitm offcore_response.all_pf_data_rd.l3_hit.snoop_non_dram offcore_response.corewb.l3_hit.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0020 offcore_response.pf_l2_rfo.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000100 Taken branch instructions retired (Precise event) event=0x22,umask=0x44 L3 Lookup read request that access cache and found line in I-state unc_cbo_cache_lookup.read_mesi offcore_response.all_code_rd.llc_miss.any_response offcore_response.all_code_rd.llc_miss.local_dram Counts all prefetch (that bring data to LLC only) RFOs miss in the L3 l2_data_rqsts.self.e_state event=0x29,period=200000,umask=0x7f l2_ld_ifetch.self.m_state l2_ld_ifetch.self.s_state l2_lock.self.m_state Modified lines evicted from the L2 cache event=0x30,period=200000,umask=0x54 l2_rqsts.self.any.mesi event=0x2e,period=200000,umask=0x41 L2 cache demand requests from this core that missed the L2 l2_rqsts.self.demand.s_state CISC macro instructions decoded misalign_mem_ref.split Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed HITM signal asserted bus_trans_brd.self ext_snoop.this_agent.clean reissue.overlap_store.ar Cycles issue is stalled due to div busy DTLB misses due to store operations event=0xd1,period=200003,umask=0x10 Load uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_needed offcore_response.any_read.l2_hit Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module offcore_response.any_rfo.l2_miss.hit_other_core_no_fwd Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000010 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000010 offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_needed event=0xe9,period=200003,umask=0x1 Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear Counts near indirect call or near indirect jmp branch instructions retired (Must be precise) Retired mispredicted branch instructions (Precise event capable) (Must be precise) br_misp_retired.jcc Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise) Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count event=0xd0,period=200003,umask=0x11 Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault Counts all L2 code requests Demand Data Read requests that hit L2 cache Spec update: HSD78, HSM80 event=0xd3,period=100003,umask=0x1 offcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwd Number of uops delivered to IDQ from any path Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery event=0xcd,period=100003,umask=0x1,ldlat=0x20 Randomly selected loads with latency value being above 512 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) Randomly selected loads with latency value being above 8 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400122 Counts all prefetch (that bring data to LLC only) data reads miss in the L3 Cycles where at least 2 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 Cycles where at least 3 uops were executed per-thread Spec update: HSD144, HSD30, HSM31 Cycles per core when uops are executed in port 4 Cycles which a uop is dispatched on port 6 in this thread L3 Lookup external snoop request that access cache and found line in MESI-state. Unit: uncore_cbox Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M) Misses in all ITLB levels that cause completed page walks event=0xbc,period=2000003,umask=0x42 Counts the number of Extended Page Table walks from the ITLB that hit in memory event=0x28,period=200003,umask=0xf Not rejected writebacks from L1D to L2 cache lines in E state l2_rqsts.pf_hit fp_comp_ops_exe.sse_packed_single event=0x10,period=2000003,umask=0x40 Counts 256-bit packed double-precision floating-point instructions Cycles with pending L1 cache miss loads. Set AnyThread to count per core Cycles which a Uop is dispatched on port 1 Uops dispatched to port 2, loads and stores per core (speculative and retired) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0010 offcore_response.pf_l2_data_rd.llc_hit.snoop_miss event=0x35,umask=0x3,filter_opc=0x1e6 Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu unc_p_freq_ge_3000mhz_transitions All retired store uops (Precise event) This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end Cases of cancelling valid DSB fill not because of exceeding way limit event=0xb6,period=100003,umask=0x1 Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2 Retired instructions experiencing ITLB misses event=0x5b,period=2000003,umask=0xc event=0x36,umask=0x3 mem_uops_retired.l2_miss_loads Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002003091 Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.any_read.l2_hit_far_tile_e_f Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.bus_locks.l2_hit_far_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400400 Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000001 Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000080 offcore_response.pf_l1_data_rd.l2_hit_near_tile event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800401000 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000200 Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local offcore_response.any_code_rd.mcdram_far Counts any request that accounts for data responses from DRAM Local offcore_response.any_rfo.ddr_far offcore_response.any_rfo.ddr_near event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000001 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200040 Counts Software Prefetches that accounts for data responses from DRAM Far event=0xc5,period=200003,umask=0xfd This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire event=0x51,period=2000000,umask=0x8 l1d_cache_st.m_state event=0x41,period=2000000,umask=0x8 l1d_prefetch.miss l2_data_rqsts.prefetch.m_state l2_lines_out.prefetch_clean L2 instruction fetch hits l2_transactions.prefetch All L2 demand store RFOs event=0xb,period=2000000,umask=0x10,ldlat=0x0 mem_inst_retired.latency_above_threshold_64 Memory instructions retired above 8 clocks (Precise Event) event=0xb7,period=100000,umask=0x1,offcore_rsp=0x211 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1FF Offcore RFO requests satisfied by any cache or DRAM Offcore writebacks to any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8008 Offcore writebacks to the IO, CSR, MMIO unit Offcore writebacks that HIT in a remote cache Offcore code or data read requests satisfied by any cache or DRAM offcore_response.data_ifetch.remote_cache_hit offcore_response.data_in.remote_cache Offcore demand data requests satisfied by any cache or DRAM offcore_response.demand_data.any_location Offcore demand data requests satisfied by the LLC and not found in a sibling core Offcore demand data requests that HITM in a remote cache offcore_response.demand_data_rd.llc_hit_other_core_hit offcore_response.demand_rfo.remote_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x880 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8030 offcore_response.pf_ifetch.any_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x240 All offcore prefetch RFO requests Offcore code reads satisfied by the local DRAM Offcore requests satisfied by any DRAM Offcore writebacks to a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2033 offcore_response.demand_data.any_dram Offcore demand data requests satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6004 Offcore prefetch data reads that missed the LLC offcore_response.pf_ifetch.local_dram offcore_response.prefetch.local_dram l1i.hits L1I instruction fetch hits event=0xc4,period=200000,umask=0x1 event=0,period=2000000,umask=0x0 ild_stall.any Loops that can't stream from the instruction queue event=0xa2,period=2000000,umask=0x40 event=0xa2,period=2000000,umask=0x10 event=0xc7,period=200000,umask=0x8 event=0xd1,period=2000000,umask=0x8 uops_executed.port015_stall_cycles Cycles Uops are not retiring (Precise Event) DTLB load miss page walks complete DTLB misses Counts duration of L1D miss outstanding in cycles Counts the total number of requests from the L2 hardware prefetchers Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020004 Counts demand data readshave any response type offcore_response.demand_data_rd.l3_hit_m.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C0002 offcore_response.demand_rfo.l3_hit_m.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0020002 offcore_response.demand_rfo.supplier_none.spl_hit offcore_response.other.l3_hit_e.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80408000 Number of PREFETCHT1 or PREFETCHT2 instructions executed Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles event=0xc6,period=100007,umask=0x1,frontend=0x14 event=0xc6,period=100007,umask=0x1,frontend=0x420006 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event) Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event) event=0x83,period=200003,umask=0x1 event=0x60,cmask=1,period=2000003,umask=0x10 event=0x60,cmask=6,period=2000003,umask=0x10 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000080001 offcore_response.demand_rfo.l3_hit_m.snoop_non_dram Counts when there is a transition from ring 1, 2 or 3 to ring 0 Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty Retirement slots used Mem;MemoryTLB;_SMT Instruction_Fetch_BW 100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1) Fed;FetchBW Jump Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault itlb_misses.walk_active Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault Counts any rfo reads (demand & prefetch) that miss L2 Counts demand and DCU prefetch instruction cacheline that have any response type Counts DCU hardware prefetcher data read that miss L2 Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache Load uops that split cache line boundary (Precise event) The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers Duration of D-side page-walks in core cycles offcore_response.pf_l2_code_rd.llc_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0040 offcore_response.all_pf_code_rd.llc_miss.dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400200 Offcore demand data read requests REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM offcore_response.any_ifetch.any_dram_and_remote_fwd event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf844 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3001 REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM offcore_response.prefetch.other_local_dram snoopq_requests.data Outstanding snoop data requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0x27FF event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2740 event=0xd3,period=100007,umask=0x2 Counts all demand code reads that hit in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0080 Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache offcore_response.all_pf_data_rd.l3_miss.remote_hit_forward Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Counts all prefetch data reads that miss the L3 and the data is returned from remote dram Counts all demand code reads that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800400 offcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00080 Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram Power_License0_Utilization Power_License0_Utilization_SMT unc_m_wpq_inserts PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0. Unit: uncore_iio Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across Read request from a remote socket which hit in the HitMe Cache to a line In the E state. Unit: uncore_cha RspI Snoop Responses Received. Unit: uncore_cha unc_iio_comp_buf_occupancy.cmpd.part3 event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x04 unc_iio_data_req_by_cpu.peer_write.part2 event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x02 Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target. Unit: uncore_iio event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x02 unc_iio_txn_req_of_cpu.peer_read.part0 event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x08 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.peer_read.part3 Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP Multi-socket cacheline Directory update from S to I. Unit: uncore_m2m unc_m2m_imc_writes.partial Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory) OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.l3_hit_s.hit_other_core_fwd ocr.all_pf_data_rd.l3_hit.hit_other_core_fwd OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_hit.snoop_none ocr.all_pf_data_rd.l3_hit_e.hitm_other_core OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F802007F7 OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD ocr.all_reads.l3_hit_f.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F801007F7 ocr.all_rfo.l3_hit_f.hit_other_core_no_fwd OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_e.hitm_other_core ocr.demand_code_rd.l3_hit_f.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200004 Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE ocr.demand_rfo.l3_hit.hit_other_core_fwd ocr.demand_rfo.l3_hit.snoop_none Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.l3_hit_e.any_snoop ocr.pf_l2_data_rd.l3_hit.hit_other_core_fwd ocr.pf_l2_data_rd.l3_hit_f.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_f.hit_other_core_fwd ocr.pf_l2_rfo.l3_hit_m.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100020 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS ocr.pf_l3_data_rd.l3_hit_m.any_snoop Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0100 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP offcore_response.all_data_rd.l3_hit_f.hit_other_core_fwd offcore_response.all_data_rd.l3_hit_s.any_snoop This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020491 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.all_pf_data_rd.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS offcore_response.demand_code_rd.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.demand_data_rd.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020002 offcore_response.other.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_hit_m.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800028000 This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoop offcore_response.pf_l1d_and_sw.supplier_none.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020010 offcore_response.pf_l2_rfo.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020020 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400080 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.pf_l3_rfo.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400100 Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.l3_miss.no_snoop_needed OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_miss.remote_hit_forward event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC007F7 ocr.all_reads.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000122 ocr.demand_code_rd.l3_miss.remote_hitm ocr.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd ocr.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000001 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE ocr.demand_rfo.l3_miss_remote_hop1_dram.any_snoop ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_miss Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED ocr.other.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210008000 ocr.pf_l1d_and_sw.l3_miss.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000400 Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_none ocr.pf_l2_rfo.l3_miss.any_snoop Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_miss.snoop_none ocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.pf_l3_rfo.l3_miss_local_dram.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_core ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_miss offcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.all_rfo.l3_miss.hitm_other_core offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP ocr.all_data_rd.supplier_none.snoop_none OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD ocr.all_reads.supplier_none.snoop_none Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED ocr.pf_l2_data_rd.any_response Underfill reads unc_m_tagchk.hit All Clean line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc unc_m2m_tag_hit.nm_ufill_hit_dirty event=0xc7,period=100003,umask=0x40 Cycles when uops are being delivered to IDQ while MS is busy 1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) / INST_RETIRED.ANY C9_Pkg_Residency event=0x54,period=100003,umask=0x80 Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions ocr.hwpf_l1d_and_swpf.any_response Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request event=0xc1,period=100003,umask=0x7 br_misp_retired.cond_ntaken cpu_clk_unhalted.distributed Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons load_hit_prefetch.swpf TMA slots available for an unhalted logical processor. Fixed counter - architectural event event=0xc2,cmask=10,inv=1,period=1000003,umask=0x2 Counts all requests that miss L2 cache Flops Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data ocr.reads_to_core.snc_cache.hitm Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor ocr.reads_to_core.l3_miss_local Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster unc_m_dram_refresh.opportunistic unc_m_rpq_inserts.pch0 PMM Commands : All. Unit: uncore_imc event=0xea,umask=0x02 TOR Inserts : PCIRdCurs issued by IO Devices. Unit: uncore_cha Four byte data request of the CPU : Card reading from DRAM. Unit: uncore_iio event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x80 unc_iio_txn_req_of_cpu.cmpd.part6 event=0xc2,ch_mask=0x02,fc_mask=0x04,umask=0x03 unc_i_clockticks event=0x2d,umask=0x04 Counts the number of cycles a core is stalled due to a store buffer being full Counts the number of load ops retired that hit in DRAM Supports address when precise (Precise event) Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0040 Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded topdown_fe_bound.icache event=0xe6,period=200003,umask=0x4 Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache ocr.l2wb_m.l3_miss_local This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT Counts miscellaneous requests, such as I/O accesses, that have any type of response ocr.uc_rd.dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100184000000 cpu_clk_unhalted.ref_tsc_p Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider Counts the total number of instructions retired (Precise event) event=0x74,period=1000003 topdown_be_bound.non_mem_scheduler TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : WCiLs issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache Clockticks in the UBOX using a dedicated 48-bit Fixed Counter Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB (cycles / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 Fraction of Physical Core issue-slots utilized by this Logical Processor. Unit: cpu_core Actual per-core usage of the Floating Point execution units (regardless of the vector width). Unit: cpu_core UOPS_ISSUED.ANY / cpu_core@UOPS_ISSUED.ANY\,cmask\=1@ CLKS_P Fraction of cycles spent in Kernel mode. Unit: cpu_atom mem_scheduler_block.ld_buf event=0xd0,period=1000003,umask=0x5,ldlat=0x4 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise). Unit: cpu_atom Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise). Unit: cpu_atom This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD. Unit: cpu_core Counts all microcode FP assists. Unit: cpu_core Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases when load subsequently retires when load subsequently retires. Unit: cpu_atom Counts demand data reads that have any type of response. Unit: cpu_core Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations. Unit: cpu_atom Cycle counts are evenly distributed between active threads in the Core. Unit: cpu_core Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core. Unit: cpu_core Number of instructions retired. General Counter - architectural event (Precise event). Unit: cpu_core unc_m_dram_page_hit_wr event=0x1f incoming write request page status is Page Miss. Unit: uncore_imc unc_m_act_count_total event=0x13,period=100003,umask=0x8 event=0x11,period=100003,umask=0x10 Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 Supports address when precise Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM event=0x2a,period=100003,umask=0x1,offcore_rsp=0x12380 event=0xec,period=2000003,umask=0x20 event=0xad,period=1000003,umask=0x20 Uops executed on ports 2, 3 and 10 This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS event=0x5,umask=0x00000000f0 event=0x2,umask=0x00000000ff event=0x3,umask=0x0000000022 unc_m_pre_count.ufill event=0x5,umask=0x0000000040 DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1. Unit: uncore_imc Write request of 4 bytes made by IIO Part1 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000001 event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000002 event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000002 event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000002 event=0x35,umask=0x00c80ffe01 event=0x35,umask=0x00C896FE01 Valid Flits Received : LLCTRL. Unit: uncore_upi unc_upi_txl_basic_hdr_match.ncb event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000004 event=0xd5,fc_mask=0x04,umask=0x00000000ff event=0x19,umask=0x07 event=0x58,umask=0x0000000004 Read requests made into the CHA. Unit: uncore_cha event=0x53,umask=0x0000000001 unc_cha_tor_inserts.loc_ia TOR Inserts : All from Local iA. Unit: uncore_cha unc_cha_tor_inserts.hit unc_cha_tor_inserts.premorph_opc unc_cha_tor_inserts.noncoh unc_cha_tor_inserts.io_hit_rfo TOR Inserts;ItoM from Local IA. Unit: uncore_cha unc_cha_tor_occupancy.loc_all unc_cha_tor_occupancy.rem_all unc_cha_tor_occupancy.io_hit_pcirdcur TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_remote_wcilf_pmm event=0x36,umask=0x00cd47ff01 TOR Occupancy : DDR Access. Unit: uncore_cha l2_request_g1.rd_blk_l event=0x60,umask=0x04 event=0x60,umask=0x02 event=0x62,umask=0x01 l2_wcb_req.wcb_write Retired Branch Instructions Mispredicted fpu_pipe_assignment.dual3 fp_ret_sse_avx_ops.all event=0x3,umask=0x80 event=0x3,umask=0x40 event=0x5,umask=0x08 L1 DTLB Reload of a page of 4K size Total Page Table Walks on D-side ic_oc_mode_switch.oc_ic_mode_switch l2_cache_hits_from_ic_misses l2_cache_hits_from_l2_hwpf event=0xaa,umask=0x03 dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7 ls_hw_pf_dc_fill.ls_mabresp_rmt_cache ls_hw_pf_dc_fill.ls_mabresp_lcl_dram Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local) event=0x28f,umask=0x07 L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB ls_sw_pf_dc_fills.mem_io_remote Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node de_dis_dispatch_token_stalls1.store_queue_rsrc_stall de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch L2 branch prediction overrides existing prediction (speculative) event=0x43,umask=0xff ls_any_fills_from_sys.local_ccx ls_any_fills_from_sys.remote_cache ls_hw_pf_dc_fills.all L2 cache requests of all types Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2 event=0x71,umask=0x04 l2_pf_miss_l2_hit_l3.l1_region L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2NextLine (fetch the next line into L2 cache) L3 cache fill requests sourced from DRAM in the same NUMA node. Unit: amd_l3 event=0xd6,umask=0x01 Reference cycles (P0 frequency) not in halt event=0x1c2 remote_processor_read_data_beats_cs8 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 8 event=0x29f,umask=0xbfe event=0x41f,umask=0x7fe Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 5 local_socket_inf1_outbound_data_beats_ccm0 event=0x51f,umask=0xbff event=0x55f,umask=0xbff event=0xc5f,umask=0xf3e local_socket_outbound_data_beats_link6 Retired SSE and AVX floating-point bfloat multiply-accumulate ops (each operation is counted as 2 ops) Retired vector floating-point multiply ops Retired MMX integer pack ops event=0xb,umask=0x0f fp_pack_ops_retired.fp256_cvt event=0xc,umask=0xf0 Retired 128-bit packed integer multiply ops Retired 128-bit packed integer ops of other types fp_disp_faults.sse_avx_all umc_data_slot_clks.wr Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages bad_speculation_pipeline_restarts All L2 cache accesses L1 demand data cache fills from local L2 cache event=0xc0,umask=0x00 event=0x12 uncore_sys_ddr_pmu FR_RETIRED_NEAR_RETURNS FR_DECODER_EMPTY FR_FPU_EXCEPTIONS EVENT_1EH EVENT_3EH EVENT_48H EVENT_64H EVENT_74H EVENT_8AH EVENT_B3H EVENT_ECH EVENT_F8H COHERENT_LINEFILL_MISSC BUS_ACCESS_LD EVENT_108H EVENT_112H EVENT_184H EVENT_18FH EVENT_1AAH EVENT_1D6H EVENT_1D8H EVENT_1DCH EVENT_1F6H EVENT_1FEH EVENT_20EH EVENT_237H EVENT_238H EVENT_246H EVENT_265H EVENT_268H EVENT_26AH EVENT_278H EVENT_290H EVENT_295H EVENT_298H EVENT_2ECH EVENT_2EEH EVENT_331H EVENT_349H EVENT_39EH EVENT_3A6H EVENT_3B2H EVENT_3ECH EXC_SVC L2D_TLB_REFILL hnf_sf_evictions sbsx_rd_axi_trkr_occ_cnt_ovfl sbsx_cmo_axi_trkr_occ_cnt_ovfl sbsx_arvalid_no_arready rnd_rxdat_flits rnd_txreq_flits_retried rni_rdb_hybrid cxra_req_trk_occ cxra_rd_dat_buf_occ cxra_dat_pcrd_stalls_lnk1 cxla_avg_sz_tx_cxs_dw_beat L1_DATA_TOTAL_HITS SUCCESSFUL_DST_TABLE_SEARCHES LSU_MISALIGN_STALL FP_ONE_QUARTER_FPSCR_RENAMES_BUSY FP_ONE_HALF_FPSCR_RENAMES_BUSY LOAD_INSTR_COMPLETED BUS_READS_WRITES_NOT_RETRIED ONE_PLUS_INSTR_COMPLETED SNOOP_HITS DLFB_LOAD_MISS_CYCLES STASH_BUSY_1 L2_COHERENT_LINE_INVALIDATIONS FPU_DENORM_INPUT_CYCLES SOFT- nta postwrszbyte K8 CMN600_PMU INTEL_IVYBRIDGE TC frontend {"type": "thr_create" GenuineIntel-6-4F GenuineIntel-6-4C GenuineIntel-6-2F GenuineIntel-6-55-[01234] This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward) Branch_Misprediction_Cost Branch_Misprediction_Cost_SMT Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor) Average data fill bandwidth to the L1 data cache [GB / sec] L3_Cache_Fill_BW L2 cache hits per kilo instruction for all demand loads (including speculative) Page_Walks_Utilization (cstate_pkg@c2\-residency@ / msr@tsc@) * 100 (cstate_pkg@c3\-residency@ / msr@tsc@) * 100 This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches All L2 requests event=0xf0,period=200003,umask=0x2 longest_lat_cache.reference Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) Supports address when precise (Precise event) event=0xd0,period=100003,umask=0x41 mem_uops_retired.split_stores Demand RFO requests including regular RFOs, locks, ItoM This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.
Note: Writeback pending FIFO has six entries Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: BDM76 This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.
Note: A prefetch promoted to Demand is counted from the promotion point Spec update: BDM76 event=0xc7,period=2000003,umask=0x10 This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable Spec update: BDM30 This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable Spec update: BDM30 icache.misses Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ event=0x79,cmask=1,edge=1,period=2000003,umask=0x30 idq_uops_not_delivered.core event=0xcd,period=101,umask=0x1,ldlat=0x200 Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) Taken speculative and retired indirect branches excluding calls and returns This event counts taken speculative and retired indirect calls including both register and memory indirect cpu_clk_thread_unhalted.ref_xclk event=0xa3,cmask=12,period=2000003,umask=0xc cycle_activity.stalls_l2_pending This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.
Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event.
Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: BDM11, BDM55 (Must be precise) event=0xa8,cmask=1,period=2000003,umask=0x1 Cycles per thread when uops are executed in port 6 uops_executed_port.port_3_core event=0xa1,any=1,period=2000003,umask=0x8 event=0xa1,any=1,period=2000003,umask=0x40 llc_misses.data_read LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox event=0x35,umask=0x3,filter_opc=0x19e (UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_DCLOCKTICKS) * 100. event=0x2,umask=0x1 dtlb_load_misses.walk_completed event=0x49,period=100003,umask=0x20 event=0x4f,period=2000003,umask=0x10 event=0xbc,period=2000003,umask=0x12 This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load Supports address when precise (Precise event) This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) Retired load uops that split across a cacheline boundary Supports address when precise (Precise event) event=0xb0,period=100003,umask=0x80 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0091 offcore_response.all_pf_data_rd.supplier_none.snoop_not_needed offcore_response.demand_code_rd.any_response offcore_response.demand_rfo.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C8000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80028000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020010 offcore_response.pf_l3_code_rd.supplier_none.any_snoop offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_no_fwd offcore_response.all_data_rd.l3_miss_local_dram.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0002 offcore_response.pf_l2_code_rd.l3_miss_local_dram.any_snoop offcore_response.pf_l3_data_rd.l3_miss.snoop_hit_no_fwd Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) This event counts return instructions retired (Precise event) unc_cbo_cache_lookup.read_m unc_cbo_cache_lookup.write_m L3 Lookup write request that access cache and found line in MESI-state Number of Core coherent Data Read entries allocated in DirectData mode offcore_response.pf_llc_rfo.llc_hit.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x087FC007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00002 L1 Data line replacements Cycles the L2 cache data bus is busy L2 cache misses l2_rqsts.self.demand.mesi simd_comp_inst_retired.scalar_single event=0xca,period=2000000,umask=0x2 simd_sat_uop_exec.ar simd_uop_type_exec.arithmetic.ar event=0xb3,period=2000000,umask=0xa0 simd_uop_type_exec.unpack.s event=0xaa,period=2000000,umask=0x3 misalign_mem_ref.rmw_bubble Bus cycles when a LOCK signal is asserted bus_trans_any.all_agents event=0x65,period=200000,umask=0x40 bus_trans_ifetch.all_agents event=0x6c,period=200000,umask=0xe0 event=0x67,period=200000,umask=0xe0 thermal_trip br_inst_decoded br_inst_retired.any br_inst_type_retired.cond Mispredicted cond branch instructions retired Mispredicted indirect calls, including both register and memory indirect event=0x12,period=2000000,umask=0x1 reissue.any.ar itlb.hit event=0xc,period=2000000,umask=0x2 event=0x2e,period=200003,umask=0x4f Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response Supports address when precise (Must be precise) Store uops retired (Precise event capable) Supports address when precise (Must be precise) Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.corewb.l2_miss.hit_other_core_no_fwd Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040001 offcore_response.demand_rfo.l2_miss.any event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000800 offcore_response.pf_l1_data_rd.l2_miss.hitm_other_core Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000010 References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture misalign_mem_ref.store_page_split event=0x3,period=200003,umask=0x2 MS uops retired (Precise event capable) (Must be precise) mem_uops_retired.dtlb_miss Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000004800 Instructions retired - using Reduced Skid PEBS feature (Must be precise) Page walk completed due to a demand data store to a 4K page Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache Spec update: HSD78, HSM80 Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 offcore_response.demand_code_rd.l3_hit.hitm_other_core Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX Speculative cache-line split load uops dispatched to L1D Number of times an RTM execution aborted due to incompatible memory type Spec update: HSD65 Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer Unhalted core cycles when the thread is not in ring 0 This event counts all mispredicted branch instructions retired. This is a precise event (Must be precise) Number of loads missed L2 Spec update: HSM63, HSM80 Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch Count cases of saving new LBR records by hardware event=0x34,umask=0x48 ITLB misses that hit STLB. No page walk event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400004 Counts the number of lines brought into the L1 data cache Dirty L2 cache lines evicted by the MLC prefetcher Requests from the L2 hardware prefetchers that hit L2 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10008 Loads with latency value being above 4 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x6004001b3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400001 Execution stalls while L2 cache miss load* is outstanding Cycles per thread when uops are dispatched to port 1 Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not unc_arb_trk_occupancy.cycles_over_half_full event=0x80,cmask=10,umask=0x01 event=0x81,umask=0x80 A snoop invalidates a non-modified line in some processor core LLC lookup request that access cache and found line in I-state. Unit: uncore_cbox unc_cbo_cache_lookup.extsnp_filter unc_cbo_cache_lookup.any_request_filter event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c03f7 Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0080 Counts all demand code reads that miss the LLC and the data forwarded from remote cache offcore_response.demand_data_rd.llc_miss.any_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f820001 event=0x35,umask=0x1,filter_opc=0x19c unc_p_freq_max_current_cycles Counts the number of cycles that the uncore was running at a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu dtlb_load_misses.demand_ld_walk_duration partial_rat_stalls.slow_lea_window Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path offcore_response.any_code_rd.l2_hit_this_tile_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000044 offcore_response.any_data_rd.l2_hit_this_tile_m offcore_response.any_pf_l2.l2_hit_near_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x08000832f7 Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x40000032f7 offcore_response.any_request.l2_hit_far_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000408000 offcore_response.any_request.l2_hit_near_tile_e_f offcore_response.any_request.l2_hit_this_tile_e offcore_response.any_request.l2_hit_this_tile_s offcore_response.demand_data_rd.l2_hit_near_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400002 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state offcore_response.partial_writes.l2_hit_far_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180100 offcore_response.partial_writes.l2_hit_this_tile_e event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000100 Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180040 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000401000 offcore_response.pf_software.l2_hit_this_tile_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080200 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100408000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800022 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800022 offcore_response.bus_locks.ddr_far Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far offcore_response.demand_rfo.mcdram_near event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000080 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181801000 Fixed Counter: Counts the number of unhalted core clock cycles Counts all nukes event=0x63,period=2000000,umask=0x1 event=0x41,period=2000000,umask=0x4 event=0x4e,period=200000,umask=0x1 L1 writebacks to L2 in I state (misses) All L2 data requests event=0x26,period=200000,umask=0x10 event=0x24,period=200000,umask=0x10 Memory instructions retired above 1024 clocks (Precise Event) event=0xcb,period=200000,umask=0x40 mem_load_retired.l1d_hit event=0xf,period=40000,umask=0x2 All offcore data reads offcore_response.any_data.io_csr_mmio Offcore code reads satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3844 Offcore requests satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x38FF event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1008 offcore_response.data_ifetch.remote_cache offcore_response.demand_data.io_csr_mmio Offcore demand data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F01 All offcore demand code reads offcore_response.demand_ifetch.llc_hit_no_other_core Offcore demand RFO requests satisfied by a remote cache or remote DRAM Offcore other requests satisfied by the LLC and HIT in a sibling core Offcore prefetch data requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1040 event=0x10,period=2000000,umask=0x4 Offcore prefetch data reads satisfied by any DRAM io_transactions load_dispatch.rs cpu_clk_unhalted.total_cycles Instructions written to instruction queue Cycles instructions are written to the instruction queue uops_decoded.stall_cycles event=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1f event=0xb1,any=1,period=2000000,umask=0x4 event=0xc8,period=200000,umask=0x20 Retired stores that miss the DTLB (Precise Event) event=0xf2,period=200003,umask=0x4 Counts L2 writebacks that access L2 cache Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB) Supports address when precise (Precise event) Retired load instructions missed L1 cache as data sources Supports address when precise (Precise event) Counts retired load instructions with at least one uop that missed in the L1 cache Supports address when precise (Precise event) Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C0004 offcore_response.demand_code_rd.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0100001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0020001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40040002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400108000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200108000 Number of PREFETCHW instructions executed frontend_retired.latency_ge_2_bubbles_ge_2 event=0xc6,period=100007,umask=0x1,frontend=0x402006 icache_64b.iftag_hit hle_retired.aborted_mem Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles Supports address when precise (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000080004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000002 offcore_response.other.l3_miss.any_snoop Number of times an RTM execution aborted due to uncommon conditions Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution Spec update: SKL091, SKL044 (Must be precise) Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7 INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES Fraction of branches that are taken conditionals CallRet FB_HPKI Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.
Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events rehabq.any_ld The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks Retired load uops with locked access. (Precise Event - PEBS) (Precise event) Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.pf_llc_rfo.llc_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10200 offcore_response.pf_l2_data_rd.llc_miss.dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400010 This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued Cycles offcore demand code read busy offcore_requests_outstanding.demand.rfo_not_empty REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f02 offcore_response.demand_rfo.local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8050 REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM offcore_response.pf_data_rd.local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5020 offcore_response.prefetch.all_local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf810 REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS event=0xb4,period=100000,umask=0x4 DTLB miss large page walks event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2733 mem_uncore_retired.remote_hitm event=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3f Retired load instructions whose data sources was remote HITM Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0002 OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD event=0xc7,period=2000003,umask=0x40 Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd offcore_response.all_rfo.l3_miss.snoop_miss_or_no_fwd Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache Power_SMT Power_License2_Utilization_SMT event=0x4,umask=0x1 event=0x37,umask=0x08 event=0x50,umask=0x10 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x08 Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit. Unit: uncore_iio unc_iio_txn_req_by_cpu.peer_read.part1 unc_i_cache_total_occupancy.mem Total IRP occupancy of inbound read and write requests. Unit: uncore_irp event=0x24 Counts cycles when direct to core mode (which bypasses the CHA) was disabled unc_m2m_directory_update.s2a event=0x38,umask=0x10 BL Ingress (from CMS) Occupancy. Unit: uncore_m2m event=0x3,umask=0x0F event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080490 ocr.all_pf_data_rd.l3_hit_f.snoop_none OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.l3_hit_m.snoop_none OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.SNOOP_NONE ocr.all_rfo.l3_hit.no_snoop_needed OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS ocr.all_rfo.l3_hit_s.hit_other_core_fwd OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_e.snoop_miss ocr.demand_code_rd.l3_hit_f.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200004 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100002 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100010 ocr.pf_l2_rfo.l3_hit_e.any_snoop ocr.pf_l2_rfo.l3_hit_s.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0080 ocr.pf_l3_data_rd.l3_hit_e.no_snoop_needed ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100080 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP ocr.pf_l3_rfo.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE offcore_response.all_data_rd.l3_hit_e.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400491 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.all_pf_data_rd.supplier_none.hit_other_core_fwd offcore_response.all_pf_rfo.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.all_reads.supplier_none.hit_other_core_no_fwd offcore_response.all_rfo.l3_hit_f.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.all_rfo.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400004 This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.demand_rfo.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS offcore_response.other.l3_hit_f.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020400 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches ocr.all_data_rd.l3_miss.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000491 ocr.all_pf_data_rd.l3_miss.any_snoop ocr.all_pf_data_rd.l3_miss.hit_other_core_fwd OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000490 ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwd OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F840007F7 ocr.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd ocr.all_rfo.l3_miss.remote_hitm ocr.all_rfo.l3_miss_local_dram.hit_other_core_fwd ocr.demand_code_rd.l3_miss.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000004 ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_none Counts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOP ocr.other.l3_miss.snoop_none ocr.other.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.pf_l1d_and_sw.l3_miss.any_snoop ocr.pf_l1d_and_sw.l3_miss.remote_hit_forward Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE offcore_response.all_reads.l3_miss.snoop_none This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.demand_data_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.pf_l2_rfo.l3_miss.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.pf_l3_rfo.l3_miss_local_dram.hitm_other_core OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.ANY_RESPONSE have any response type OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED ocr.demand_data_rd.supplier_none.snoop_none ocr.demand_rfo.supplier_none.hitm_other_core Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwd ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_none Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts. Unit: uncore_imc UNC_M_PMM_BANDWIDTH.TOTAL unc_m_tagchk.miss_clean event=0x2c,umask=0x08 Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3 event=0xd1,period=100021,umask=0x4 ocr.demand_data_rd.l3_hit.any ocr.demand_data_rd.l3_hit.snoop_hitm Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required Counts memory transactions sent to the uncore Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) event=0xa3,cmask=2,period=1000003,umask=0x2 Counts Unfriendly TSX abort triggered by a vzeroupper instruction Counts demand data reads that DRAM supplied the request Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations Counts taken conditional branch instructions retired (Precise event) Indirect near branch instructions retired (excluding returns) (Precise event) All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event) event=0xec,period=2000003,umask=0x2 lsd.cycles_ok topdown.backend_bound_slots Number of uops executed on port 0 uops_dispatched.port_4_9 Number of page walks outstanding for a demand load in the PMH each cycle mem_load_l3_hit_retired.xsnp_fwd Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches ocr.hwpf_l3.l3_miss_local Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster Counts hardware prefetch (which bring data to L2) that have any type of response ocr.reads_to_core.remote_dram ocr.reads_to_core.snc_pmm event=0x10,umask=0x01 event=0x35,umask=0xC80FFD01 unc_cha_tor_inserts.ia_miss_crd TOR Inserts : All requests from IO Devices that hit the LLC. Unit: uncore_cha TOR Occupancy : All requests from IO Devices that hit the LLC. Unit: uncore_cha TOR Occupancy : All requests from IO Devices that missed the LLC. Unit: uncore_cha event=0x35,umask=0xC897FD01 event=0x35,umask=0xCCC7FF01 TOR Inserts : SpecItoMs issued by iA Cores. Unit: uncore_cha event=0x35,umask=0xC8168601 unc_cha_llc_lookup.data_read Clockticks of the integrated IO (IIO) traffic controller. Unit: uncore_iio event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x80 event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x01 event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x04 event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x01 event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x04 unc_iio_comp_buf_inserts.cmpd.part4 PCIe Completion Buffer Occupancy of completions with data : Part 1. Unit: uncore_iio unc_cha_tor_inserts.io_itom_remote Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache ocr.l2wb_m.l3_hit ocr.reads_to_core.l3_hit.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x101F803C0000 Counts the number of misaligned load uops that are 4K page splits (Precise event) ocr.corewb_m.l3_miss Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis Counts all code reads that have any type of response ocr.hwpf_l2_code_rd.outstanding Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) topdown_fe_bound.branch_resteer Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0x35,umask=0xC8A7FD01 TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_wil PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page ept.epde_miss Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache Instructions per (near) call (lower number means higher occurrence rate). Unit: cpu_core Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Unit: cpu_core L2 cache hits per kilo instruction for all demand loads (including speculative). Unit: cpu_core event=0xd0,period=1000003,umask=0x5,ldlat=0x8 Number of cycles a demand request has waited due to L1D due to lack of L2 resources. Unit: cpu_core L2 cache hits when fetching instructions, code reads. Unit: cpu_core Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event). Unit: cpu_core event=0x21,period=100003,umask=0x8 event=0x40,period=100003,umask=0x4 event=0xc6,period=100007,umask=0x1,frontend=0x601006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core machine_clears.slow Number of near branch instructions retired that were mispredicted and taken (Precise event). Unit: cpu_core Reference cycles when the core is not in halt state. Unit: cpu_core inst_retired.macro_fused Number of Uops delivered by the LSD. Unit: cpu_core event=0xe0,period=400009,umask=0x20 event=0xb2,period=2000003,umask=0x4 incoming read request page status is Page Miss. Unit: uncore_imc Code miss in all TLB levels causes a page walk that completes. (2M/4M). Unit: cpu_core Code miss in all TLB levels causes a page walk that completes. (4K). Unit: cpu_core Completed demand load uops that miss the L1 d-cache Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data FP_ARITH_INST_RETIRED2.SCALAR_HALF event=0x2a,period=100003,umask=0x1,offcore_rsp=0x730000001 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C004477 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations All DRAM read CAS commands issued (does not include underfills). Unit: uncore_imc event=0x5,umask=0x00000000c2 event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000001 event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000002 event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000002 unc_iio_txn_req_of_cpu.peer_write.part5 TOR Inserts for ItoMCacheNears from IO devices. Unit: uncore_cha Valid Flits Sent : Protocol Header. Unit: uncore_upi unc_upi_txl_basic_hdr_match.ncb_opc event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000004 event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000001 event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000001 event=0x21,umask=0x0310 unc_m2m_prefcam_demand_drops.ch0_xpt event=0x55,umask=0x0000000001 OSB Snoop Broadcast : Local InvItoE. Unit: uncore_cha TOR Inserts : WBQ. Unit: uncore_cha unc_cha_tor_inserts.local_tgt TOR Inserts; RFO from local IA. Unit: uncore_cha event=0x35,umask=0x00c897ff01 unc_cha_tor_inserts.ia_clflushopt TOR Occupancy : SF/LLC Evictions. Unit: uncore_cha TOR Occupancy; ITOM hits from local IO. Unit: uncore_cha event=0x36,umask=0x00c827ff01 unc_cha_tor_inserts.ia_miss_drd_pref_pmm unc_cha_tor_inserts.ia_miss_drd_pref_local_ddr unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddr event=0x35,umask=0x00cc27ff01 event=0x35,umask=0x00C87FDE01 unc_cha_tor_inserts.ia_miss_wcilf_pmm TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC. Unit: uncore_cha event=0x36,umask=0x00c80f7e01 unc_cha_tor_occupancy.ia_itomcachenear TOR Occupancy : WCiLs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.pmm unc_cha_tor_inserts.ddr PCU PCLK Clockticks. Unit: uncore_pcu The number of 32B fetch windows tried to read the L1 IC and missed in the full tag All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads l2_request_g2.smc_inval LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requests event=0x63,umask=0x04 Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2 Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2 event=0xc9 remote_outbound_data_controller_2 event=0x87,umask=0x38 Total number multi-pipe uOps assigned to pipe 2 fpu_pipe_assignment.dual1 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipes fpu_pipe_assignment.total3 event=0x2,umask=0x07 fp_ret_sse_avx_ops.dp_mult_flops ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit branch_prediction L3 Accesses. Unit: amd_l3 All TLBs Flushed ls_bad_status2.stli_other event=0x37 event=0x43,umask=0x10 event=0xae,umask=0x04 ex_ret_msprd_brnch_instr_dir_msmtch Retired Mispredicted Branch Instructions due to Direction Mismatch ls_dmnd_fills_from_sys.ext_cache_remote ls_sw_pf_dc_fills.ext_cache_local de_dis_dispatch_token_stalls1.load_queue_rsrc_stall ls_any_fills_from_sys.local_all ls_any_fills_from_sys.far_all Any data cache fills from extension memory ls_sw_pf_dc_fills.local_l2 Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2 Core to L2 cache requests (not including L2 prefetch) for instruction cache hits Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses event=0x64,umask=0xff L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fetch additional sequential lines into L2 cache) l2_pf_miss_l2_hit_l3.l2_next_line event=0x71,umask=0x20 l2_pf_miss_l2_l3.l2_burst local_processor_read_data_beats_cs10 event=0x9f,umask=0x7ff Read data beats (64 bytes) for remote processor at Coherent Station (CS) 2 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 4 Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1 local_socket_inf1_inbound_data_beats_ccm1 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 5 remote_socket_inf0_inbound_data_beats_ccm4 remote_socket_inf1_inbound_data_beats_ccm4 remote_socket_inf0_outbound_data_beats_ccm7 local_socket_outbound_data_beats_link7 Retired x87 floating-point add and subtract ops event=0xa,umask=0x06 event=0xa,umask=0x07 event=0xa,umask=0x09 fp_ops_retired_by_type.scalar_other Retired scalar floating-point ops of other types fp_ops_retired_by_type.scalar_all Retired vector floating-point square root ops Retired MMX integer MOV ops sse_avx_ops_retired.sse_avx_shuffle sse_avx_ops_retired.sse_avx_logical event=0xc,umask=0xff event=0xd,umask=0x02 Retired 128-bit packed integer subtract ops event=0xd,umask=0x90 packed_int_op_type.int256_mov event=0xd,umask=0xf0 Floating-point dispatch faults for XMM fills memory controller L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages de_dis_ops_from_decoder.disp_op_type.any_integer_dispatch d_ratio((6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@), total_dispatch_slots) L2 cache accesses from L1 instruction cache misses (including prefetch) dram_write_data_for_local_processor Local socket upstream DMA read data cycles FR_RETIRED_BRANCHES_MISPREDICTED EVENT_0CH EVENT_2DH EVENT_3DH EVENT_56H EVENT_77H EVENT_8CH EVENT_A9H EVENT_B1H EVENT_C3H EVENT_C5H EVENT_D3H EVENT_F1H WRITE_STALL L2D_CACHE BR_RETURN_RETIRED UNALIGNED_LDST_RETIRED EVENT_114H EVENT_12BH EVENT_135H EVENT_163H EVENT_164H EVENT_172H EVENT_1AFH EVENT_1BEH EVENT_224H EVENT_24EH EVENT_253H EVENT_2D2H EVENT_2E5H EVENT_2EBH EVENT_2FEH EVENT_31DH EVENT_323H EVENT_330H EVENT_342H EVENT_3C6H EVENT_3F8H L1D_CACHE_ST ST_SPEC EXC_UNDEF hni_wvalid_no_wready cxla_tx_cxs_link0 TLBIE_SNOOPS L1_INSTR_CACHE_RELOADS GPR_ISSUE_QUEUE_STALLED MISPREDICTED_BRANCHES L3_INSTR_CACHE_MISSES RUN_CYCLES CYCLES BUS_HIGH BRANCH_INSTRS_COMPLETED STORE_UOPS_COMPLETED CYCLES_LRU_SCHED_STALLED CRIT_INPUT_INTR_TAKEN L2_CACHE_DATA_DIRTY_HITS FPU_FINISH edge cycles-to-complete EDGE TAGGING CASCADE INTEL_SKYLAKE l3_slice_mask {"type": "proc_create" GenuineIntel-6-6A The ratio of Executed- by Issued-Uops CoreIPC_SMT Ret;SMT;TmaL1_SMT DSB;Fed;FetchBW L1 cache true misses per kilo instruction for retired demand loads 1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY C3_Pkg_Residency l2_demand_rqsts.wb_hit l2_lines_in.s This event counts L2 or L3 HW prefetches that access L2 cache including rejects mem_load_uops_l3_hit_retired.xsnp_hitm This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) event=0xd1,period=100003,umask=0x40 Retired load uops misses in L1 cache as data sources. Uses PEBS Supports address when precise (Precise event) Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) Supports address when precise (Precise event) offcore_requests.demand_code_rd event=0xb0,period=100003,umask=0x4 offcore_requests_outstanding.demand_code_rd offcore_requests_outstanding.demand_rfo event=0x60,period=2000003,umask=0x4 fp_arith_inst_retired.256b_packed_single Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports event=0x79,cmask=1,period=2000003,umask=0x18 This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ This event counts loads with latency value being above 64 Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_8 Speculative and retired macro-conditional branches This event counts both taken and not taken speculative and retired macro-conditional branch instructions event=0x88,period=200003,umask=0xc8 This event counts taken speculative and retired macro-conditional branch instructions event=0xc4,period=400009,umask=0x20 event=0x89,period=200003,umask=0x81 This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired (Precise event) This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: BDM61 event=0xa8,cmask=4,period=2000003,umask=0x1 lsd.cycles_active This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread uops_executed.thread Cycles per core when uops are exectuted in port 1 Actually retired uops. (Precise Event - PEBS) Supports address when precise (Precise event) uops_retired.stall_cycles 1 llc_misses.pcie_non_snoop_write event=0x1,umask=0x3 event=0x4 Counts the number of cycles when temperature is the upper limit on frequency. Unit: uncore_pcu Counts the number of cycles when the OS is the upper limit on frequency. Unit: uncore_pcu dtlb_store_misses.miss_causes_a_walk dtlb_store_misses.walk_completed_4k itlb_misses.stlb_hit Code misses that miss the DTLB and hit the STLB (2M) Misses in all ITLB levels that cause completed page walks Spec update: BDM69 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020240 Counts prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020122 offcore_response.corewb.supplier_none.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004 offcore_response.demand_code_rd.supplier_none.snoop_miss offcore_response.demand_data_rd.supplier_none.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080028000 offcore_response.pf_l2_code_rd.l3_hit.any_snoop offcore_response.pf_l2_code_rd.l3_hit.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0020 offcore_response.pf_l2_rfo.supplier_none.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020080 offcore_response.pf_l3_data_rd.supplier_none.snoop_miss Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000122 offcore_response.all_rfo.l3_miss.snoop_miss offcore_response.corewb.l3_miss.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000008 offcore_response.demand_code_rd.l3_miss.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000010 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_not_needed offcore_response.pf_l3_code_rd.l3_miss_local_dram.any_snoop offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hitm number of near branch instructions retired that were mispredicted and taken (Precise event) L3 Lookup any request that access cache and found line in MESI-state Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts all demand data writes (RFOs) hit in the L3 L1 Cacheable Data Reads event=0x40,period=2000000,umask=0xa2 Cycles L2 address bus is in use event=0x30,period=200000,umask=0x78 l2_reject_busq.self.prefetch.mesi l2_rqsts.self.demand.e_state event=0x2a,period=200000,umask=0x44 event=0x2a,period=200000,umask=0x42 event=0xcb,period=200000,umask=0x1 Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions misalign_mem_ref.ld_split Nonzero segbase ld-op-st 1 bubble Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed Any Software prefetch event=0x7f,period=200000,umask=0x40 event=0x60,period=200000,umask=0xe0 event=0x69,period=200000,umask=0xe0 event=0x6b,period=200000,umask=0x40 bus_trans_pwr.all_agents br_inst_retired.any1 All indirect branches that have a return mnemonic br_missp_type_retired.ind_call cpu_clk_unhalted.core_p event=0x3,period=200000,umask=0x7f event=0xc,period=200000,umask=0x3 event=0xd0,period=200003,umask=0x42 Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x10000032b7 Counts requests to the uncore subsystem that hit the L2 cache Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000002 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000002 offcore_response.partial_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed event=0x86,period=200003 br_inst_retired.ind_call Retired mispredicted conditional branch instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0xfe Cycles a divider is busy cycles_div_busy.idiv Instructions retired (Fixed event) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000400 offcore_response.bus_locks.outstanding Counts demand cacheable data reads of full cache lines hit the L2 cache Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000010 event=0xc3,period=20003 Integer divide uops retired (Precise Event Capable) (Must be precise) Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks offcore_response.demand_rfo.l3_hit.hit_other_core_no_fwd Randomly selected loads with latency value being above 64 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01004007F7 offcore_response.demand_code_rd.l3_miss.local_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00010 offcore_response.pf_l2_rfo.l3_miss.any_response Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer Number of integer move elimination candidate uops that were not eliminated Cycles allocation is stalled due to resource related reason Spec update: HSD135 Counts number of cycles no uops were dispatched to be executed on this thread Spec update: HSD144, HSD30, HSM31 Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles (Precise event) uncore other Load misses in all DTLB levels that cause page walks Counts the number of Extended Page Table walks from the DTLB that hit in the L3 offcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwd hsx metrics event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00010 l2_l1d_wb_rqsts.all Any MLC or LLC HW prefetch accessing L2, including rejects offcore_response.demand_data_rd.llc_hit.no_snoop_needed Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses ivb metrics uops_dispatched_port.port_2_core Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC unc_cbo_cache_lookup.m Remote cache HITM offcore_response.other.portio_mmio_uc event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0080 ivt metrics event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400004 offcore_response.demand_code_rd.llc_miss.remote_hit_forward Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC Cycles where receiving QPI link is in half-width mode. Unit: uncore_qpi Memory page conflicts. Unit: uncore_imc freq_ge_1200mhz_cycles % l1d.eviction offcore_response.all_demand_mlc_pref_reads.llc_miss.any_response insts_written_to_iq.insts Resource stalls2 control structures full for physical registers Occupancy counter for memory read queue. Unit: uncore_imc Counts the total number of L2 cache references mem_uops_retired.l1_miss_loads offcore_response.any_code_rd.l2_hit_far_tile_e_f offcore_response.any_code_rd.l2_hit_near_tile offcore_response.any_data_rd.l2_hit_this_tile_e Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000022 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000022 Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode offcore_response.partial_writes.any_response Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response offcore_response.pf_l1_data_rd.l2_hit_this_tile_f Counts any Prefetch requests that accounts for data responses from DRAM Far offcore_response.any_request.ddr_far offcore_response.any_request.ddr_near offcore_response.any_rfo.mcdram event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800001 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far) Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.pf_l1_data_rd.ddr_far This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once event=0x1,umask=0x01 mcdram bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk l1d_all_ref.any L1 data cache stores in S state l2_data_rqsts.prefetch.i_state l2_rqsts.loads L2 RFO transactions l2_write.rfo.i_state Memory instructions retired above 0 clocks (Precise Event) event=0xb,period=50,umask=0x10,ldlat=0x800 Offcore code or data read requests satisfied by a remote cache Offcore request = all data, response = remote cache or dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x833 offcore_response.demand_data.remote_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3803 offcore_response.demand_data_rd.llc_hit_no_other_core offcore_response.demand_ifetch.any_location event=0xb7,period=100000,umask=0x1,offcore_rsp=0x802 Offcore other requests satisfied by the IO, CSR, MMIO unit offcore_response.pf_data_rd.any_location offcore_response.pf_data_rd.remote_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1010 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8020 offcore_response.prefetch.any_location event=0x6,period=200000,umask=0x8 offcore_response.any_ifetch.any_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF8FF offcore_response.any_request.remote_dram offcore_response.corewb.any_llc_miss Offcore other requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4030 event=0xe8,period=2000000,umask=0x2 Branch instructions executed br_inst_exec.indirect_near_call event=0x89,period=2000,umask=0x4 event=0x17,period=2000000,umask=0x1 inst_retired.mmx ROB read port stalls cycles ROB full stall cycles Reservation Station full stall cycles uops_decoded.esp_folding L1D miss outstandings duration in cycles l2_lines_out.useless_hwpf Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache Counts the RFO (Read-for-Ownership) requests that miss L2 cache Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3 Spec update: SKL057 Core-originated cacheable demand requests that refer to L3 Spec update: SKL057 Retired store instructions that split across a cacheline boundary Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040004 offcore_response.demand_code_rd.l3_hit_s.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40080001 offcore_response.demand_rfo.l3_hit_s.any_snoop offcore_response.other.l3_hit_s.snoop_not_needed offcore_response.other.l4_hit_local_l4.snoop_miss Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc6,period=100007,umask=0x1,frontend=0x13 Number of times we entered an HLE region. Does not count nested transactions Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles Supports address when precise (Must be precise) event=0xb0,period=100003,umask=0x10 offcore_response.demand_code_rd.l3_hit_s.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C400004 offcore_response.demand_rfo.l3_hit_s.snoop_non_dram offcore_response.other.l3_miss_local_dram.spl_hit This event counts taken branch instructions retired Spec update: SKL091 (Precise event) exe_activity.1_ports_util Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1 1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD) Total pipeline cost of (external) Memory Bandwidth related bottlenecks Memory_Latency Branching_Overhead L3_Cache_Access_BW Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault Loads missed L2 (Precise event) offcore_response.any_code_rd.l2_miss.any event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000044 Any reissued store uops Cycles the divider is busy. Does not imply a stall waiting for the divider event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0100 Outstanding offcore demand code reads Cycles offcore demand data read busy event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5044 REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5033 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff03 REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE offcore_response.demand_data.local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f01 REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x850 REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD offcore_response.pf_rfo.any_dram_and_remote_fwd event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3020 Outstanding snoop code requests event=0x8,period=200000,umask=0x4 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2744 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2703 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF850 Load instructions retired local dram and remote cache HIT data sources (Precise Event) Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0122 OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100 offcore_response.pf_l3_rfo.l3_hit.no_snoop_needed Counts all prefetch data reads that miss the L3 and the data is returned from local dram Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram Counts prefetch RFOs that miss the L3 and the data is returned from remote dram Counts demand data reads that miss the L3 and the data is returned from remote dram Counts all demand data writes (RFOs) that miss in the L3 offcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram offcore_response.pf_l2_data_rd.l3_miss.remote_hitm offcore_response.pf_l2_data_rd.l3_miss.snoop_miss_or_no_fwd Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) ) Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions IoBW;Mem;SoC;Server event=0x4,umask=0xF MMIO writes. Unit: uncore_cha read requests from home agent. Unit: uncore_cha UPI interconnect send bandwidth for payload. Unit: uncore_upi PCI Express bandwidth reading at IIO. Unit: uncore_iio Normal priority reads issued to the memory controller from the CHA. Unit: uncore_cha unc_cha_llc_victims.total_f event=0x39,umask=0x08 event=0xd5,fc_mask=0x04,umask=0x02 Read request for 4 bytes made by the CPU to IIO Part0. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x02 Read request for up to a 64 byte transaction is made by the CPU to IIO Part2. Unit: uncore_iio event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x01 unc_iio_txn_req_of_cpu.peer_read.part2 Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken Multi-socket cacheline Directory update from I to A. Unit: uncore_m2m unc_m2m_directory_update.s2i AD Ingress (from CMS) Queue Inserts. Unit: uncore_m2m AD Ingress (from CMS) Occupancy Clocks of the Intel Ultra Path Interconnect (UPI). Unit: uncore_upi Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200491 ocr.all_pf_data_rd.l3_hit.snoop_hit_with_fwd ocr.all_pf_rfo.l3_hit.snoop_hit_with_fwd ocr.all_pf_rfo.l3_hit_e.hit_other_core_fwd OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED ocr.all_reads.l3_hit_e.hitm_other_core OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ocr.demand_rfo.l3_hit_e.snoop_none ocr.demand_rfo.l3_hit_f.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200002 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800048000 ocr.other.l3_hit_m.no_snoop_needed Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080010 ocr.pf_l2_rfo.l3_hit.snoop_miss Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200080 ocr.pf_l3_data_rd.l3_hit_m.no_snoop_needed ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_data_rd.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.all_pf_rfo.l3_hit_s.snoop_none offcore_response.all_pf_rfo.supplier_none.hitm_other_core offcore_response.all_reads.l3_hit_e.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP offcore_response.all_reads.supplier_none.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000207F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800207F7 offcore_response.all_rfo.l3_hit_f.hit_other_core_no_fwd offcore_response.all_rfo.l3_hit_f.snoop_none This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE offcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE offcore_response.demand_data_rd.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS offcore_response.other.l3_hit.hitm_other_core offcore_response.other.l3_hit_e.no_snoop_needed offcore_response.other.l3_hit_m.no_snoop_needed offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.pf_l2_data_rd.l3_hit_m.snoop_none offcore_response.pf_l2_data_rd.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd offcore_response.pf_l2_rfo.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l3_rfo.l3_hit_f.no_snoop_needed offcore_response.pf_l3_rfo.l3_hit_s.any_snoop ocr.all_data_rd.l3_miss.remote_hit_forward event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000120 ocr.all_reads.l3_miss.hitm_other_core OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONE ocr.all_reads.l3_miss_local_dram.hit_other_core_no_fwd OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS ocr.all_rfo.l3_miss.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000122 Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000001 ocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.demand_rfo.l3_miss.remote_hit_forward ocr.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000400 ocr.pf_l2_data_rd.l3_miss.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000080 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.all_rfo.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE ocr.all_data_rd.supplier_none.any_snoop OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type ocr.all_reads.pmm_hit_local_pmm.snoop_none ocr.demand_code_rd.pmm_hit_local_pmm.any_snoop ocr.demand_rfo.pmm_hit_local_pmm.any_snoop Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP ocr.other.pmm_hit_local_pmm.any_snoop ocr.other.pmm_hit_local_pmm.snoop_not_needed Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.pf_l3_data_rd.supplier_none.any_snoop l2_rqsts.swpf_hit Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0400 ocr.hwpf_l2_data_rd.l3_hit.snoop_miss Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor Counts the number of PREFETCHNTA instructions executed assists.fp event=0xc7,period=100003,umask=0x20 Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events event=0xc6,period=100007,umask=0x1,frontend=0x500806 BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES ( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED ) event=0xc9,period=100003,umask=0x80 Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request Counts demand data reads that have any type of response Counts conditional branch instructions retired (Precise event) Far branch instructions retired (Precise event) Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch (Precise event) Counts number of near branch instructions retired that were mispredicted and taken (Precise event) event=0xa3,cmask=16,period=1000003,umask=0x10 event=0xa3,cmask=5,period=1000003,umask=0x5 int_misc.all_recovery_cycles topdown.slots Number of uops executed on port 2 and 3 Page walks completed due to a demand data store to a 4K page Cycles the superQ cannot take any more entries event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000004 Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode icx metrics event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F04400477 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703C00001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000002 2LM Tag Check : Miss, existing data may be evicted to Far Memory. Unit: uncore_imc event=0xea,umask=0x01 event=0x35,umask=0xC817FD01 TOR Inserts : All requests from iA Cores that Missed the LLC. Unit: uncore_cha TOR Inserts : RFO_Prefs issued by iA Cores. Unit: uncore_cha event=0x35,umask=0xC8170A01 unc_cha_tor_occupancy.ia_miss_drd_ddr event=0x36,umask=0xC8178601 event=0x35,umask=0xC8F3FF04 TOR Occupancy : PCIRdCurs issued by IO Devices. Unit: uncore_cha event=0x34,umask=0x1BC1FF event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x80 unc_iio_txn_req_by_cpu.mem_read.part6 PCIe Completion Buffer Occupancy of completions with data : Part 2. Unit: uncore_iio event=0x17 TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0x34,period=200003,umask=0x10 event=0x34,period=200003,umask=0x1 Counts the number of retired loads that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core Supports address when precise (Precise event) Counts the number of load uops retired that miss in the L2 cache Supports address when precise (Precise event) ocr.all_code_rd.l3_hit.snoop_hitm Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded baclears.indirect Counts the number of BACLEARS due to a direct, unconditional jump This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS ocr.l2wb_m.l3_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003000000000000 Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response ocr.l2wb_m.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000100000000000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200000010000 Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU Counts the number of machine clears due typically to program modifying data (self modifying code) within 1K of a recently fetched code page event=0x73,period=1000003,umask=0x4 topdown_retiring.all DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels TOR Inserts : DRd_Opt_Prefs issued by iA Cores. Unit: uncore_cha TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Counts the number of page walks completed due to store DTLB misses to any page size Counts the number of page walks completed due to store DTLB misses to a 4K page Counts the number of Extended Page Directory Pointer Entry hits Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches Counts the number of page walks completed due to instruction fetch misses to a 1G page Counts the number of BACLEARS due to a non-indirect, non-conditional jump Instructions per Branch (lower number means higher occurrence rate). Unit: cpu_atom Ratio of all branches which mispredict. Unit: cpu_atom 100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL event=0x4,period=20003,umask=0x1 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0001 Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. Unit: cpu_core Number of switches from DSB or MITE to the MS. Unit: cpu_core event=0x47,cmask=9,period=1000003,umask=0x9 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10001 Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls. Unit: cpu_atom Direct and indirect near call instructions retired (Precise event). Unit: cpu_core inst_retired.rep_iteration Uops that RAT issues to RS. Unit: cpu_core Cycles without actually retired uops. Unit: cpu_core unc_m_dram_page_miss_wr unc_mc0_rdcas_count_freerun unc_mc0_wrcas_count_freerun event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104000004 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708000001 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x700C04477 CPU_CLK_UNHALTED.PAUSE_INST INT_MISC.UNKNOWN_BRANCH_CYCLES event=0x5,umask=0x00000000c4 event=0xe4,umask=0x0000000002 Precharge due to write on page miss. Unit: uncore_imc unc_m_pmm_rpq_occupancy.no_gnt_sch0 event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000002 event=0x36,umask=0x00c8178a01 Valid Flits Sent : Slot NULL or LLCRD Empty. Unit: uncore_upi event=0x2,umask=0x0000000027 unc_upi_rxl_basic_hdr_match.ncb event=0xc2,ch_mask=0x04,fc_mask=0x07,umask=0x0000000004 event=0x21,umask=0x0308 unc_m2m_prefcam_demand_drops.xpt_allch TOR Inserts; DRd hits from local IA. Unit: uncore_cha TOR Inserts : PRQ - Non IOSF. Unit: uncore_cha TOR Inserts : All from Remote. Unit: uncore_cha unc_cha_tor_inserts.miss TOR Inserts : MMIO Access. Unit: uncore_cha TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field. Unit: uncore_cha TOR Inserts; CRd Pref hits from local IA. Unit: uncore_cha event=0x35,umask=0x00cc43fd04 TOR Inserts; DRd Opt from local IA. Unit: uncore_cha event=0x36,umask=0x00c88ffe01 unc_cha_tor_occupancy.ia_rfo_pref event=0x36,umask=0x00c8a7ff01 TOR Inserts : DRd PTEs issued by iA Cores. Unit: uncore_cha event=0x35,umask=0x00c8168a01 event=0x35,umask=0x00C8970A01 unc_cha_tor_inserts.ia_hit_itom event=0x36,umask=0x00c80efe01 TOR Occupancy : ItoMs issued by iA Cores. Unit: uncore_cha The number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event event=0x61,umask=0x20 event=0xca ex_ret_mmx_fp_instr.sse_instr The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions event=0x847,umask=0x02 event=0x7,umask=0x38 dram_channel_data_controller_3 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision add/subtract FLOPS Number of Scalar Ops optimized fp_num_mov_elim_scal_op.sse_mov_ops fp_retired_ser_ops.sse_ctrl_ret LS MAB allocates by type - DC prefetcher ls_pref_instr_disp.load_prefetch_w event=0x52,umask=0x01 de_dis_dispatch_token_stalls0.retire_token_stall l3_accesses The number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8 event=0xe,umask=0x08 Floating Point Dispatch Faults. YMM fill fault Retired lock instructions. High speculative cacheable lock speculation succeeded ls_ret_cpuid L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line in L2 ic_tag_hit_miss.instruction_cache_hit event=0x9a,umask=0xff event=0x1c7 All Allocations. Counts when a LS pipe allocates a MAB entry event=0x47,umask=0x02 Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node event=0xab,umask=0x08 Any FP dispatch. Types of Oops Dispatched from Decoder L2 Cache Hits from L2 Cache HWPF L3 Cache Accesses. Unit: amd_l3 L1 Data Cache Fills: All Macro-ops Dispatched Demand data cache fills from local L2 cache ls_dmnd_fills_from_sys.alternate_memories Any data cache fills from local L2 cache Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket) ls_sw_pf_dc_fills.alternate_memories L2 cache requests of common types from L1 data cache (including prefetches) l2_cache_req_stat.ic_hit_in_l2 l2_pf_hit_l2.l2_stride event=0x70,umask=0x80 l3_lookup_state.l3_miss ls_not_halted_p0_cyc.p0_freq_cyc Write data beats (64 bytes) for local processor at Coherent Station (CS) 5 remote_processor_read_data_beats_cs2 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 3 event=0x19f,umask=0xbff Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2 event=0x55e,umask=0x7ff local_socket_inf1_outbound_data_beats_ccm3 remote_socket_inf0_outbound_data_beats_ccm2 Retired SSE and AVX floating-point add and subtract ops fp_ret_sse_avx_ops.bfloat_mac_flops fp_ops_retired_by_type.scalar_add event=0xb,umask=0x03 Retired MMX integer multiply-accumulate ops Retired SSE and AVX integer SHA ops fp_pack_ops_retired.fp128_cvt fp_pack_ops_retired.fp256_mul event=0xd,umask=0x01 event=0xd,umask=0x05 Retired 256-bit packed integer add ops event=0xd,umask=0xa0 L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x85,umask=0x0f total_dispatch_slots Local socket inbound data to the CPU (e.g. read data) remote_socket_inbound_data_to_cpu Estimated memory write bandwidth FP_DISPATCHED_FPU_FAST_FLAG_OPS LS_RETIRED_CFLUSH_INSTRUCTIONS BU_FILL_REQUEST_L2_MISS IC_L1_ITLB_MISS_AND_L2_ITLB_HIT IC_L1_ITLB_MISS_AND_L2_ITLB_MISS FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED FR_DISPATCH_STALL_FOR_SERIALIZATION NB_SIZED_COMMANDS INSTR_SPEC L1_DCACHE_HASH_MISS EVENT_06H EVENT_0EH EVENT_1DH EVENT_42H EVENT_55H EVENT_5EH EVENT_78H EVENT_7EH EVENT_A7H EVENT_A8H EVENT_C1H EVENT_D0H EVENT_D9H EVENT_F2H INSTR_CACHE_DEPENDENT_STALL FLOATING_POINT_INSTR_RENAMED ISB L1D_CACHE L1D_TLB_REFILL EVENT_19AH EVENT_1BFH EVENT_1DEH EVENT_1E2H EVENT_202H EVENT_24FH EVENT_264H EVENT_26DH EVENT_27CH EVENT_2B1H EVENT_2E8H EVENT_2F3H EVENT_329H EVENT_3A0H EVENT_3B1H EVENT_3BAH EVENT_3BBH EVENT_3D4H EXC_HVC xp_txflit_stall sbsx_txrsp_retryack cxra_chi_dat_upload_stalls cxla_rx_cxs_link1 VPU_INSTR_COMPLETED DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD LSU_ALIAS_VS_CSQ FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU LSU_MISALIGN_STORE_COMPLETED CACHEABLE_STORE_MERGE_TO_32_BYTES SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY L3SQ_FULL_CYCLES RAQ_FULL_CYCLES FXU0_BUSY_FXU1_BUSY UOPS_DECODED STASH_REQUESTS_L2 packed-sse-sse2 THRESHOLD SYSWIDE INTEL_SKYLAKE_XEON INTEL_ICELAKE HygonGenuine LLC_REFERENCE %s, "pmcid": "0x%08x", "event": "%d", "flags": "0x%08x", "evname": "%s"}
GenuineIntel-6-8[CD] HygonGenuine-24-00 This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU Retiring ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) Branches;Fed;FetchBW;Frontend;PGO IpArith_AVX128 Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings Branches;OS event=0x51,period=2000003,umask=0x1 event=0x24,period=200003,umask=0xe1 Core-originated cacheable demand requests missed L3 This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU mem_load_uops_l3_hit_retired.xsnp_none event=0xd1,period=2000003,umask=0x1 event=0xd0,period=2000003,umask=0x82 event=0xd0,period=100003,umask=0x11 event=0x60,period=2000003,umask=0x8 offcore_requests_outstanding.demand_data_rd_ge_6 Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.scalar Cycles where a code fetch is stalled due to L1 instruction-cache miss idq.empty This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ Loads with latency value being above 256 Spec update: BDM100, BDM35 (Must be precise) event=0xcd,period=2003,umask=0x1,ldlat=0x40 Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region Number of times we could not allocate Lock Buffer event=0xc4,period=400009 This event counts far branch instructions retired Spec update: BDW98 br_inst_retired.near_call Speculative and retired mispredicted macro conditional branches This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz Cycles while L2 cache miss demand load is outstanding move_elimination.int_not_eliminated uops_dispatched_port.port_1 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1 Number of uops executed from any thread uops_executed.core_cycles_ge_4 event=0xb1,cmask=4,period=2000003,umask=0x2 uops_executed.stall_cycles Number of Multiply packed/scalar single precision uops allocated event=0xe,cmask=1,inv=1,period=2000003,umask=0x1 event=0x35,umask=0x3,filter_opc=0x182 (UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCKTICKS) * 100. power_state_occupancy.cores_c3 % dtlb_load_misses.stlb_hit_2m dtlb_store_misses.walk_completed_1g event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020090 offcore_response.all_pf_rfo.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010008 offcore_response.corewb.supplier_none.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C8000 offcore_response.other.supplier_none.snoop_none offcore_response.pf_l2_code_rd.any_response Counts all prefetch (that bring data to LLC only) code reads have any response type offcore_response.pf_l3_data_rd.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000091 offcore_response.all_data_rd.l3_miss_local_dram.any_snoop offcore_response.all_pf_code_rd.l3_miss.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004008000 offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000040 offcore_response.pf_l2_data_rd.l3_miss.snoop_miss offcore_response.pf_l2_data_rd.l3_miss.snoop_none offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000010 offcore_response.pf_l2_data_rd.supplier_none.snoop_non_dram offcore_response.pf_l2_rfo.l3_hit.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020200 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_non_dram A cross-core snoop resulted from L3 Eviction which misses in some processor core unc_cbo_xsnp_response.hitm_xcore A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core. Unit: uncore_cbox unc_cbo_cache_lookup.any_i uncore_arb ( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) ) Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_rfo.llc_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00244 offcore_response.all_data_rd.llc_miss.any_response Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache offcore_response.all_rfo.llc_miss.any_response Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram Counts all demand data writes (RFOs) miss in the L3 uncore_qpi l1d_cache.all_cache_ref l2_dbus_busy.self l2_ld.self.prefetch.e_state event=0x29,period=200000,umask=0x54 event=0x2e,period=200000,umask=0x78 event=0x2e,period=200000,umask=0x54 event=0x2e,period=200000,umask=0x51 Retired Streaming SIMD Extensions (SSE) scalar-single instructions simd_sat_uop_exec.s event=0x10,period=2000000,umask=0x81 Load splits event=0x5,period=200000,umask=0x94 misalign_mem_ref.split.ar Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed Deferred bus transactions event=0x77,period=200000,umask=0x21 All non-indirect calls br_inst_type_retired.uncond uops_retired.stalled_cycles event=0x8,period=200000,umask=0x5 event=0x30,period=200003 event=0xd0,period=200003,umask=0x83 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000003091 Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.any event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200008000 Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_needed Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000004000 Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000042000 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000001000 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events event=0x86,period=200003,umask=0x1 machine_clears.all event=0xc2,period=2000003,umask=0x10 event=0x5,period=200003,umask=0x3 Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module offcore_response.bus_locks.l2_hit Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0x49,period=2000003,umask=0x8 Page walk completed due to an instruction fetch in a 2M or 4M page Demand code read requests sent to uncore offcore_response.all_code_rd.l3_hit.hit_other_core_no_fwd hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded hsw metrics ( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD Number of times an HLE execution aborted due to incompatible memory type Spec update: HSD65 This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available Cycles which a uop is dispatched on port 2 in this thread Cycles which a uop is dispatched on port 4 in this thread unc_cbo_cache_lookup.extsnp_mesi A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core event=0x22,umask=0x24 Load miss in all TLB levels causes a page walk that completes. (1G) This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses page_walker_loads.ept_itlb_l3 event=0xd3,period=100003,umask=0x20 offcore_response.pf_l2_data_rd.llc_miss.any_response Retired load uops which data sources were data hits in LLC without snoops required (Precise event) offcore_response.all_reads.any_response Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Number of transitions from AVX-256 to legacy SSE when penalty applicable offcore_response.data_in_socket.llc_miss.local_dram Cycles with pending L2 cache miss loads Number of loads missed L2 Number of flags-merge uops being allocated event=0x22,umask=0x10 Filter on cross-core snoops initiated by this Cbox due to processor core memory request. Unit: uncore_cbox unc_cbo_xsnp_response.eviction_filter dtlb_load_misses.large_page_walk_completed event=0x5f,period=100003,umask=0x4 Counts demand data reads that miss the LLC and the data forwarded from remote cache event=0xd,filter_band2=30 Not rejected writebacks from L1D to L2 cache lines in S state Retired load uops which data sources were data hits in LLC without snoops required Mispredicted not taken branch instructions retired (Precise event) event=0x3,period=100003,umask=0x1 Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu offcore_response.any_code_rd.l2_hit_this_tile_e event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000044 Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 offcore_response.any_read.l2_hit_far_tile Counts any Read request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180400 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080004 offcore_response.demand_code_rd.l2_hit_this_tile_e Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400001 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000002 offcore_response.partial_reads.any_response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400080 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000100 offcore_response.pf_l2_code_rd.l2_hit_this_tile_e Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state offcore_response.uc_code_reads.l2_hit_this_tile_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000200 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600070 Counts any request that accounts for responses from DDR (local and far) offcore_response.any_rfo.mcdram_near Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local offcore_response.demand_data_rd.mcdram_near Counts Software Prefetches that accounts for responses from MCDRAM (local and far) Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready rs_full_stall.all event=0x4e,period=200000,umask=0x4 l2_lines_out.prefetch_dirty l2_transactions.load event=0x27,period=100000,umask=0xe0 mem_inst_retired.latency_above_threshold_16384 mem_inst_retired.stores event=0xb2,period=100000,umask=0x1 Offcore data reads satisfied by a remote cache offcore_response.any_request.any_cache_dram Offcore requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x122 Offcore RFO requests satisfied by the LLC or local DRAM offcore_response.any_rfo.remote_cache_hit offcore_response.data_ifetch.remote_cache_dram offcore_response.data_in.remote_cache_dram offcore_response.demand_data.llc_hit_other_core_hitm Offcore demand data requests satisfied by a remote cache or remote DRAM offcore_response.demand_data_rd.local_cache_dram Offcore demand data reads that HITM in a remote cache offcore_response.demand_ifetch.llc_hit_other_core_hit Offcore demand RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF80 offcore_response.pf_data.llc_hit_other_core_hitm Offcore prefetch data reads that HIT in a remote cache offcore_response.prefetch.io_csr_mmio Offcore prefetch requests satisfied by the LLC and not found in a sibling core event=0x10,period=2000000,umask=0x10 event=0x12,period=200000,umask=0x1 simd_int_64.packed_arith offcore_response.any_data.local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2011 Offcore writebacks to the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6001 offcore_response.other.remote_dram offcore_response.pf_data_rd.remote_dram Offcore prefetch RFO requests satisfied by the local DRAM L1I instruction fetch stall cycles event=0x80,period=2000000,umask=0x2 baclear.clear event=0x88,period=200000,umask=0x1 event=0x88,period=200000,umask=0x40 event=0x89,period=2000,umask=0x20 ild_stall.regen Regen stall cycles inst_queue_writes Cycles when uops were delivered by the LSD Cycles machine clear asserted event=0xa2,period=2000000,umask=0x2 resource_stalls.mxcsr resource_stalls.rs_full Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches mem_inst_retired.all_loads All retired load instructions Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0040004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0100004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100001 offcore_response.demand_rfo.l4_hit_local_l4.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000108000 offcore_response.other.l3_hit_s.snoop_none offcore_response.other.l3_hit_s.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400408000 Number of PREFETCHNTA instructions executed event=0x32,period=2000003,umask=0x2 Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events Retired Instructions who experienced DSB miss (Precise event) Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x404006 hle_retired.aborted_memtype offcore_response.demand_code_rd.l3_miss.any_snoop offcore_response.demand_data_rd.l3_miss.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000040002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x44008000 Conditional branch instructions retired Spec update: SKL091 (Precise event) exe_activity.2_ports_util event=0xd,any=1,period=2000003,umask=0x1 Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector) other_assists.any event=0xe,period=2000003,umask=0x2 event=0xc2,period=2000003,umask=0x4 Memory_Bandwidth_SMT 100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) L1 cache true misses per kilo instruction for all demand loads (including speculative) 1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY Counts demand and DCU prefetch data read that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000100 Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache This event counts the number of store uops reissued from Rehabq rehabq.ld_splits This event counts the number of retired stores that are delayed because there is not a store address buffer available Store uops that split cache line boundary This event counts the number of retire stores that experienced cache line boundary splits This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS) (Precise event) All retired load uops. (Precise Event - PEBS) (Precise event) offcore_response.all_pf_code_rd.llc_hit.hit_other_core_no_fwd Counts all demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0002 offcore_response.demand_rfo.llc_hit.snoop_miss Counts all prefetch (that bring data to L2) data reads that hit in the LLC Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_l2_rfo.llc_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400200 Offcore RFO requests offcore_requests_outstanding.demand.read_code_not_empty Cycles offcore demand RFOs busy REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM offcore_response.any_request.local_dram_and_remote_cache_hit REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1050 REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf811 offcore_response.any_rfo.other_local_dram REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS offcore_response.pf_data.other_local_dram REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10490 offcore_response.demand_data_rd.l3_hit.no_snoop_needed offcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800491 Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram Counts prefetch RFOs that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000400 Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00010 Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache Core cycles the core was throttled due to a pending power level request event=0xfe,period=100003,umask=0x2 Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions 1000000000 * ( UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS ) / imc_0@event\=0x0@ Mem;MemoryLat;SoC;Server Average IO (network or disk) Bandwidth Use for Reads [GB / sec] event=0x4,umask=0x2 read requests from local home agent. Unit: uncore_cha 4Bytes PCI Express bandwidth writing at IIO, part 3. Unit: uncore_iio event=0x5b,umask=0x01 Snoop filter capacity evictions for E-state entries. Unit: uncore_cha PCIe Completion Buffer Inserts of completions with data: Part 2 unc_iio_data_req_by_cpu.peer_read.part0 Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x02 Read request for up to a 64 byte transaction is made by the CPU to IIO Part3. Unit: uncore_iio event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x02 Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit. Unit: uncore_iio event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x04 unc_iio_txn_req_of_cpu.peer_read.part1 Multi-socket cacheline Directory lookups (cacheline found in A state). Unit: uncore_m2m event=0x2e,umask=0x8 event=0x56 AD Egress (to CMS) Occupancy unc_m3upi_upi_prefetch_spawn unc_upi_direct_attempts.d2u Null FLITs received from any slot. Unit: uncore_upi Valid Flits Sent; Data. Unit: uncore_upi ocr.all_data_rd.l3_hit_f.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200491 OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100490 OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080120 OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000407F7 ocr.all_reads.l3_hit_s.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080122 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED ocr.demand_code_rd.l3_hit_m.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0001 Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP ocr.demand_data_rd.l3_hit_f.hit_other_core_fwd ocr.demand_data_rd.l3_hit_f.snoop_miss ocr.demand_data_rd.l3_hit_s.snoop_none ocr.demand_rfo.l3_hit_m.hit_other_core_fwd Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE ocr.other.l3_hit_f.hitm_other_core ocr.other.l3_hit_f.no_snoop_needed Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_hit_s.snoop_miss ocr.pf_l1d_and_sw.l3_hit_s.snoop_none ocr.pf_l2_data_rd.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_hit_e.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200080 ocr.pf_l3_data_rd.l3_hit_m.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE ocr.pf_l3_rfo.l3_hit_f.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200100 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020490 offcore_response.all_pf_rfo.l3_hit.hit_other_core_fwd offcore_response.all_pf_rfo.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.all_reads.pmm_hit_local_pmm.snoop_none offcore_response.all_reads.supplier_none.snoop_miss This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.all_rfo.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020001 This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.other.l3_hit_s.no_snoop_needed offcore_response.other.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.pf_l1d_and_sw.l3_hit_f.no_snoop_needed offcore_response.pf_l1d_and_sw.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l3_rfo.l3_hit_s.snoop_none offcore_response.pf_l3_rfo.supplier_none.hit_other_core_fwd OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE ocr.all_data_rd.l3_miss.remote_hitm ocr.all_pf_data_rd.l3_miss_local_dram.hitm_other_core OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE ocr.all_pf_rfo.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000120 ocr.all_reads.l3_miss_local_dram.hit_other_core_fwd ocr.all_reads.l3_miss_local_dram.no_snoop_needed OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000122 ocr.all_rfo.l3_miss_local_dram.no_snoop_needed ocr.all_rfo.l3_miss_remote_hop1_dram.snoop_miss Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.demand_rfo.l3_miss.hit_other_core_no_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED ocr.other.l3_miss.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC008000 Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd ocr.pf_l2_data_rd.l3_miss.remote_hitm ocr.pf_l2_data_rd.l3_miss_local_dram.any_snoop ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.pf_l2_rfo.l3_miss.hit_other_core_fwd ocr.pf_l2_rfo.l3_miss_local_dram.hitm_other_core Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss.remote_hit_forward ocr.pf_l3_rfo.l3_miss.hit_other_core_fwd ocr.pf_l3_rfo.l3_miss.no_snoop_needed ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD offcore_response.all_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwd offcore_response.all_reads.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_data_rd.pmm_hit_local_pmm.snoop_not_needed OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE ocr.demand_data_rd.pmm_hit_local_pmm.any_snoop ocr.pf_l1d_and_sw.supplier_none.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_needed Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP ocr.pf_l3_rfo.supplier_none.any_snoop unc_m_pmm_wpq_inserts Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory. Unit: uncore_imc TOR Occupancy : DRds issued by iA Cores that Missed the LLC. Unit: uncore_cha Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event) Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not idq.mite_cycles_ok Cycles MITE is delivering optimal number of Uops Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache event=0x54,period=100003,umask=0x20 Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request ocr.hwpf_l2_data_rd.any_response Number of occurrences where a microcode assist is invoked by hardware event=0xc5,period=50021,umask=0x11 br_misp_retired.indirect_call TMA slots where uops got dropped Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products event=0x56,period=1000003,umask=0x1 event=0x8,period=100003,umask=0x20 Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x830000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000477 event=0xef,period=1000003,umask=0x2 Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode ocr.hwpf_l3.any_response ocr.reads_to_core.local_dram event=0x2,umask=0x04 unc_cha_tor_inserts.ia_hit_llcprefrfo event=0x35,umask=0xCCC7FE01 unc_cha_tor_inserts.ia_miss_rfo_pref TOR Inserts; WCiL misses from local IA. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha event=0x35,umask=0xC8F3FD04 unc_cha_tor_inserts.io_pcirdcur event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x80 event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x80 event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x04 unc_iio_data_req_of_cpu.mem_write.part5 event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x04 event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x80 unc_iio_comp_buf_inserts.cmpd.part7 unc_iio_comp_buf_occupancy.cmpd.part5 event=0xf,umask=0x04 FAF RF full. Unit: uncore_irp event=0x37,umask=0x0720 unc_m2p_clockticks CMS Clockticks. Unit: uncore_m2pcie core_reject_l2q.any Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis ocr.demand_data_and_l1pf_rd.l3_hit.snoop_not_needed ocr.full_streaming_wr.l3_hit ocr.hwpf_l2_code_rd.l3_hit.snoop_miss ocr.uc_wr.l3_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002184000000 ocr.full_streaming_wr.any_response Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response event=0x73,period=1000003,umask=0x6 topdown_bad_speculation.mispredict event=0x35,umask=0xC001FE01,config1=0x40e33 event=0x35,umask=0xC827FD01 TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC. Unit: uncore_cha TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0x36,umask=0xC827FD01 TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Counts the number of page walks outstanding in the page miss handler (PMH) for loads every cycle Counts the number of page walks due to storse that miss the PDE (Page Directory Entry) cache Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache INST_RETIRED.ANY / cycles event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2104000001 The ratio of Executed- by Issued-Uops. Unit: cpu_core Core actual clocks when any Logical Processor is active on the Physical Core. Unit: cpu_core Instructions per Store (lower number means higher occurrence rate). Unit: cpu_core Measured Average Frequency for unhalted processors [GHz]. Unit: cpu_core Giga Floating Point Operations Per Second. Unit: cpu_core 100 * SERIALIZATION.NON_C01_MS_SCB / ( 5 * CPU_CLK_UNHALTED.CORE ) Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]. Unit: cpu_core Retired instructions with at least 1 uncacheable load or lock Supports address when precise (Precise event). Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles Supports address when precise (Must be precise). Unit: cpu_core core_power.license_2 Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS. Unit: cpu_atom Cycles while L2 cache miss demand load is outstanding. Unit: cpu_core Cycles where the Store Buffer was full and no loads caused an execution stall. Unit: cpu_core Precise instruction retired with PEBS precise-distribution (Precise event). Unit: cpu_core uops_dispatched.port_2_3_10 Read CAS command sent to DRAM. Unit: uncore_imc Load miss in all TLB levels causes a page walk that completes. (All page sizes). Unit: cpu_core event=0x13,period=100003,umask=0xe Number of page walks outstanding for a store in the PMH each cycle. Unit: cpu_core Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. Unit: cpu_core event=0x11,period=100003,umask=0xe Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.MISS] event=0x2a,period=100003,umask=0x1,offcore_rsp=0x830004477 fp_arith_inst_retired2.scalar_half Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility Supports address when precise (Must be precise) event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FFC4477 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired (Precise event) Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources Number of uops dispatch to execution port 0 Number of uops dispatch to execution ports 5 and 11 event=0x3,umask=0x00000000ff unc_m_pre_count.rd_pch1 Write request of 4 bytes made by IIO Part3 to Memory. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_write.part4 event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000002 unc_iio_txn_req_of_cpu.peer_write.part4 TOR Inserts for DRd misses from local IA targeting local memory. Unit: uncore_cha unc_upi_txl_flits.slot2 unc_upi_txl_flits.llcrd Valid Flits Sent : LLCTRL. Unit: uncore_upi RxQ Flit Buffer Bypassed : Slot 1. Unit: uncore_upi event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000001 event=0xc1,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000001 event=0xc2,ch_mask=0x40,fc_mask=0x07,umask=0x0000000004 D2U Sent. Unit: uncore_m3upi D2C Sent. Unit: uncore_m3upi TOR Inserts : All. Unit: uncore_cha event=0x35,umask=0x00c803fe04 TOR Inserts; DRd Opt Pref misses from local IA. Unit: uncore_cha TOR Inserts;CLFlush from Local IA. Unit: uncore_cha unc_cha_tor_occupancy.local_tgt TOR Occupancy; DRd Opt misses from local IA. Unit: uncore_cha TOR Occupancy; RFO prefetch misses from local IA. Unit: uncore_cha TOR Occupancy; RFO hits from local IO. Unit: uncore_cha TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_llcprefdata TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_local_wcilf_pmm TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_pmm unc_cha_tor_occupancy.ia_miss_crd_remote TOR Occupancy : WbMtoIs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_itom unc_cha_tor_occupancy.ia_miss_wcil_ddr unc_cha_tor_inserts.pmm The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses) All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state l2_wcb_req.wcb_close l2_cache_req_stat.ls_rd_blk_cs Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2 event=0x70,umask=0xff The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction event=0xcb,umask=0x04 Single-precision divide/square root FLOPS fp_ret_sse_avx_ops.sp_add_sub_flops Counts the number of stores dispatched to the LS unit. Unit Masks ADDed event=0x45,umask=0x08 event=0x4b,umask=0x01 All L2 Cache Misses event=0x64,umask=0x06 fp_ret_sse_avx_ops.add_sub_flops LS MAB Allocates by Type. Stores L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote) event=0xae,umask=0x08 Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2. Use l2_cache_misses_from_ic_miss instead The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for >4K Coalesced page op_cache_hit_miss.op_cache_hit The number of macro-ops retired Retired Indirect Branch Instructions. The number of indirect branches retired Counts the number of interrupts taken ls_any_fills_from_sys.mem_io_local L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node L3 Misses (includes cacheline state change requests). Unit: amd_l3 ls_any_fills_from_sys.dram_io_far Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable) ls_sw_pf_dc_fills.local_ccx event=0x5a,umask=0x80 l2_cache_req_stat.dc_access_in_l2 L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) l2_pf_miss_l2_l3.l2_next_line l2_pf_miss_l2_l3.l2_up_down Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node. Unit: amd_l3 l3_xi_sampled_latency.all Cycles with no retire while the oldest op is waiting to be executed Retired fused instructions Read data beats (64 bytes) for remote processor at Coherent Station (CS) 3 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 6 remote_processor_write_data_beats_cs7 local_socket_upstream_read_beats_iom0 local_socket_upstream_read_beats_iom2 local_socket_upstream_write_beats_iom0 Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 1 event=0x5df,umask=0xbfe Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 2 event=0x5df,umask=0xbff Retired MMX floating-point ops event=0x8,umask=0x20 event=0xa,umask=0x10 sse_avx_ops_retired.mmx_shift Retired SSE and AVX integer AES ops packed_int_op_type.int128_mul event=0xd,umask=0x07 packed_int_op_type.int256_add umc_cas_cmd.all Number of memory store operations dispatched to the load-store unit event=0x96 de_src_op_disp.op_cache L2 cache hits from L1 instruction cache misses l1_demand_data_cache_fills_from_far_memory L2 data TLB misses and data page walks local_socket_outbound_data_from_all_links IC_INSTRUCTION_FETCH_STALL FR_DISPATCH_STALLS FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT TTBR_WRITE EVENT_0FH EVENT_21H EVENT_63H EVENT_76H EVENT_85H EVENT_8BH EVENT_C7H EVENT_CCH EVENT_EFH DSB PLE_REQUEST_COMPLETED L1I_TLB_REFILL EVENT_13BH EVENT_149H EVENT_16BH EVENT_1A1H EVENT_1C6H EVENT_1E1H EVENT_210H EVENT_212H EVENT_21AH EVENT_228H EVENT_24CH EVENT_25EH EVENT_281H EVENT_297H EVENT_2BEH EVENT_2D3H EVENT_30AH EVENT_325H EVENT_340H EVENT_35AH EVENT_37CH EVENT_3FFH L2D_CACHE_WB_VICTIM L3D_CACHE ITLB_WALK dn_rxreq_dvmop_vmid_filtered hnf_pocq_reqs_recvd hnf_ld_st_swp_adq_full hnf_stash_snp_sent rni_s1_rdata_beats clkdiv2_queue_depth clkdiv2_activate INSTR_DISPATCHED UNRESOLVED_BRANCHES MTSPR_INSTR_COMPLETED FPU_DENORMALIZATION LD_ST_TRUE_ALIAS_STALL L1_DATA_TOTAL_MISSES VTQ_LINE_FETCH VR_STALLS WAQ_FULL_CYCLES EXTERNAL_INTERVENTIONS MARKED_GROUP_COMPLETE_TIMEOUT TIMEBASE_EVENT GCT_EMPTY_BY_ICACHE_MISS STASH_BUSY_2 L2_CACHE_DIRTY_DATA_ALLOCATIONS LOAD_RETRIES cycles-in-request sse-retype-microfaults page-miss probe-miss k8-dc-miss k8-fr-taken-hardware-interrupts DOMWIDE INTEL_CORE ARMV7_CORTEX_A15 /usr/src/lib/libpmc/libpmc_pmu_util.c unit: %s
%s, "pmcid": "0x%08x", "pid": "%d"}
GenuineIntel-6-1E AuthenticAMD-23-[[:xdigit:]]+ This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU Cor;Flops;HPC_SMT Flops;FpVector;InsType C3_Core_Residency C7 residency percent per core l1d_pend_miss.pending Not rejected writebacks that hit L2 cache l2_lines_in.all event=0xf1,period=100003,umask=0x2 event=0x24,period=200003,umask=0x27 event=0x24,period=200003,umask=0x21 This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on event=0xf0,period=200003,umask=0x4 event=0xd3,period=100007,umask=0x10 mem_load_uops_retired.l1_hit Demand and prefetch data reads Demand Data Read requests sent to uncore offcore_requests.demand_rfo event=0x60,cmask=6,period=2000003,umask=0x1 other_assists.sse_to_avx uop_dispatches_cancelled.simd_prf idq.ms_switches idq_uops_not_delivered.cycles_le_2_uop_deliv.core hle_retired.aborted_misc2 mem_trans_retired.load_latency_gt_512 Unfriendly TSX abort triggered by a nest count that is too deep tx_mem.abort_hle_elision_buffer_not_empty This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects This event counts not taken macro-conditional branch instructions event=0x88,period=200003,umask=0x90 event=0xc4,period=100007,umask=0x2 event=0x89,period=200003,umask=0xa0 event=0xa3,cmask=2,period=2000003,umask=0x2 cycle_activity.cycles_mem_any inst_retired.any_p event=0x4c,period=100003,umask=0x2 This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register This event counts cycles during which the reservation station (RS) is empty for the thread.
Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues uops_dispatched_port.port_0 Cycles where at least 3 uops were executed per-thread llc_misses.data_llc_prefetch llc_references.pcie_read event=0x1,umask=0x2 power_channel_ppd % event=0xa Counts the number of cycles when power is the upper limit on frequency. Unit: uncore_pcu Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI) Supports address when precise. Spec update: BDE70, BDM100 (Precise event) offcore_response.all_data_rd.supplier_none.snoop_hit_no_fwd Counts all demand code reads have any response type offcore_response.demand_code_rd.supplier_none.any_snoop offcore_response.demand_code_rd.supplier_none.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0002 offcore_response.pf_l2_code_rd.supplier_none.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0200 offcore_response.pf_l3_rfo.supplier_none.snoop_none Randomly selected loads with latency value being above 256 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) Counts randomly selected loads with latency value being above 64 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000080 offcore_response.pf_l3_rfo.l3_miss.snoop_none unc_cbo_xsnp_response.miss_xcore A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox event=0x34,umask=0x21 L3 Lookup write request that access cache and found line in M-state. Unit: uncore_cbox unc_cbo_cache_lookup.read_es event=0x80,umask=0x02 Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case. Unit: uncore_arb event=0x81,umask=0x20 event=0,umask=0x01 event=0x29,period=200000,umask=0x78 l2_lock.self.e_state l2_lock.self.s_state l2_m_lines_out.self.demand event=0x30,period=200000,umask=0x72 event=0x2e,period=200000,umask=0x58 l2_rqsts.self.prefetch.s_state event=0xc7,period=2000000,umask=0x8 simd_uop_type_exec.arithmetic.s simd_uop_type_exec.pack.ar event=0xb3,period=2000000,umask=0x84 simd_uop_type_exec.shift.ar FXCH uops executed event=0xe6,period=2000000,umask=0x1 Cycles during which instruction fetches are stalled icache.accesses Nonzero segbase 1 bubble event=0x5,period=200000,umask=0x8a Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed event=0xc4,period=200000,umask=0x2 All macro conditional branch instructions Multiply operations executed Periods no micro-ops retired page_walks.cycles Cycles code-fetch stalled due to an outstanding ICache miss mem_load_uops_retired.wcb_hit Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.demand_code_rd.l2_hit Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache offcore_response.demand_rfo.l2_miss.hitm_other_core event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040800 offcore_response.streaming_stores.l2_hit Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache offcore_response.sw_prefetch.l2_hit Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result MS decode starts event=0xc4,period=200003,umask=0xfb event=0xc5,period=200003,umask=0xfb mem_uops_retired.dtlb_miss_loads Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.outstanding event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000022 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000012000 Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Instructions retired (Fixed event) (Must be precise) itlb_misses.walk_pending Demand Data Read requests Spec update: HSD78, HSM80 Demand data read requests sent to uncore Spec update: HSD78, HSM80 offcore_response.all_requests.l3_hit.any_response offcore_response.all_data_rd.l3_miss.any_response Stall cycles because IQ is full Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact Cycles which a uop is dispatched on port 3 in this thread Number of multiply packed/scalar single precision uops allocated L3 Lookup external snoop request that access cache and found line in E or S-state Store misses in all DTLB levels that cause completed page walks. (1G) event=0xbc,period=2000003,umask=0x48 event=0xbc,period=2000003,umask=0x81 Number of ITLB page walker loads from memory Spec update: HSD25 offcore_response.pf_l2_rfo.llc_hit.any_response Retired load uops with L1 cache hits as data sources (Precise event) Retired load uops which data sources following L1 data-cache miss (Precise event) Retired load uops with L2 cache hits as data sources (Precise event) offcore_response.all_code_rd.llc_hit.no_snoop_needed Counts all demand & prefetch RFOs that hit in the LLC offcore_response.demand_code_rd.llc_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0002 Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines Number of instructions at retirement Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise) event=0xc1,period=100003,umask=0x80 event=0xa1,period=2000003,umask=0xc Counts the number of allocated write entries, include full, partial, and LLC evictions A snoop hits a modified line in some processor core. Unit: uncore_cbox A snoop hits a modified line in some processor core event=0x22,umask=0x40 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20040 rxl0p_power_cycles % unc_q_txl0p_power_cycles unc_p_freq_ge_2000mhz_cycles Counts the number of cycles that the uncore was running at a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu event=0xac,period=2000003,umask=0xa idq_uops_not_delivered.cycles_ge_1_uop_deliv.core event=0x4e,period=2000003,umask=0x2 Resource stalls due to Rob being full, FCSW, MXCSR and OTHER event=0x5b,period=2000003,umask=0x4f event=0x8,period=100003,umask=0x10 This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles Counts the loads retired that get the data from the other core in the same tile in M state Supports address when precise (Precise event) mem_uops_retired.utlb_miss_loads Counts any Prefetch requests that accounts for any response offcore_response.any_pf_l2.l2_hit_far_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400070 Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.any_rfo.l2_hit_this_tile_m Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000400 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080002 offcore_response.partial_reads.l2_hit_this_tile_s Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000020020 Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x01004032f7 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00802032f7 offcore_response.any_request.mcdram_near Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800004 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600001 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800080 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600100 Counts L1 data HW prefetches that accounts for responses from DDR (local and far) Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts the number of near indirect CALL branch instructions retired (Precise event) br_misp_retired.far_branch l1d_cache_ld.m_state L1 data cache load locks in E state event=0x52,period=2000000,umask=0x1 l2_data_rqsts.demand.mesi l2_lines_in.any L2 lines evicted L2 lines evicted by a demand request event=0x24,period=200000,umask=0x4 event=0xf0,period=200000,umask=0x10 l2_write.rfo.hit event=0xb,period=10,umask=0x10,ldlat=0x2000 mem_inst_retired.loads mem_uncore_retired.local_dram mem_uncore_retired.uncacheable event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4711 Offcore data reads that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1044 offcore_response.any_request.local_cache offcore_response.any_request.remote_cache Offcore writebacks to the LLC Offcore writebacks to a remote cache offcore_response.data_ifetch.local_cache_dram offcore_response.data_in.io_csr_mmio Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1003 offcore_response.demand_data_rd.local_cache offcore_response.demand_data_rd.remote_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF04 Offcore demand code reads satisfied by a remote cache or remote DRAM Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core offcore_response.other.remote_cache_dram offcore_response.pf_data.local_cache offcore_response.pf_ifetch.local_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1070 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x870 event=0xfd,period=200000,umask=0x4 offcore_response.any_request.local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x40FF event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6033 Offcore demand code reads satisfied by the local DRAM Offcore demand RFO requests satisfied by any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF880 offcore_response.pf_data.any_dram event=0xb8,period=100000,umask=0x4 baclear.bad_target br_inst_exec.direct_near_call event=0x89,period=20000,umask=0x40 inst_decoded.dec0 event=0xa8,cmask=1,inv=1,period=2000000,umask=0x1 lsd_overflow event=0xa2,period=2000000,umask=0x80 ssex_uops_retired.scalar_single uops_executed.port015 Cycles no Uops were issued Cycles Uops are being retired (Precise event) Retired instructions that missed the ITLB (Precise Event) Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache mem_inst_retired.any mem_inst_retired.lock_loads Retired store instructions that miss the STLB Supports address when precise (Precise event) Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event) mem_load_retired.l3_hit Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore Counts all demand code readshave any response type offcore_response.demand_code_rd.l3_hit_m.snoop_hit_no_fwd offcore_response.demand_code_rd.l4_hit_local_l4.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40100001 offcore_response.demand_rfo.supplier_none.snoop_hitm offcore_response.other.l3_hit_e.any_snoop offcore_response.other.l3_hit_s.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0028000 event=0xc6,period=100007,umask=0x1,frontend=0x408006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_256 event=0xc6,period=100007,umask=0x1,frontend=0x15 Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles Supports address when precise (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000080002 offcore_response.demand_rfo.l3_miss.snoop_hitm offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000002 offcore_response.demand_rfo.l4_hit_local_l4.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000088000 This event counts return instructions retired Spec update: SKL091 (Precise event) Core crystal clock cycles when at least one thread on the physical core is unhalted event=0xa6,period=2000003,umask=0x1 Mem;MemoryLat;Offcore Branching_Overhead_SMT Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault Counts any request that have any response type Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000040 Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0) CALL counts the number of near CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time offcore_response.all_code_rd.llc_hit.snoop_miss offcore_response.all_pf_rfo.llc_hit.any_response Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_llc_rfo.llc_hit.hitm_other_core REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS) (Precise event) Outstanding offcore demand RFOs event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5022 REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f33 REQUEST = DATA_IN and RESPONSE = ANY_LOCATION REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.pf_ifetch.local_dram_and_remote_cache_hit REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f20 event=0x5,period=200000,umask=0x2 REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf850 REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD snoopq_requests.invalidate event=0x85,period=200000,umask=0x80 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5811 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2750 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5850 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0122 offcore_response.demand_rfo.l3_hit.no_snoop_needed offcore_response.pf_l3_data_rd.l3_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0080 offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000004 Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram event=0x28,period=200003,umask=0x40 event=0xfe,period=100003,umask=0x4 Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate) Rate of non silent evictions from the L2 cache per Kilo instruction Fraction of Core cycles where the core was running with power-delivery for baseline license level 0 Average IO (network or disk) Bandwidth Use for Writes [GB / sec] unc_m_cas_count.rd_reg All DRAM Read CAS Commands issued (does not include underfills). Unit: uncore_imc unc_m_wpq_occupancy uncore_cha unc_cha_requests.reads_local PCI Express bandwidth reading at IIO, part 3. Unit: uncore_iio event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x01 Lines Victimized; Lines in E state. Unit: uncore_cha event=0x11,umask=0x01 event=0x5c,umask=0x40 PCIe Completion Buffer Inserts of completions with data: Part 0-3 PCIe Completion Buffer Inserts of completions with data: Part 3. Unit: uncore_iio event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x01 Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x01 unc_iio_txn_req_of_cpu.peer_write.part0 unc_iio_txn_req_of_cpu.peer_write.part3 event=0x2d,umask=0x8 event=0x2e,umask=0x1 event=0x31,umask=0x2 OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040491 OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP ocr.all_pf_data_rd.l3_hit_e.snoop_miss ocr.all_pf_data_rd.l3_hit_f.no_snoop_needed OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040490 ocr.all_pf_data_rd.l3_hit_s.hit_other_core_fwd ocr.all_pf_rfo.l3_hit.hit_other_core_fwd ocr.all_pf_rfo.l3_hit_m.no_snoop_needed OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000407F7 ocr.all_reads.l3_hit_s.any_snoop OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080122 ocr.all_rfo.l3_hit_f.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040122 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS ocr.demand_code_rd.l3_hit_e.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200004 ocr.demand_code_rd.l3_hit_s.snoop_miss ocr.demand_data_rd.l3_hit_e.any_snoop Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED ocr.demand_data_rd.l3_hit_m.hit_other_core_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED ocr.demand_rfo.l3_hit_f.snoop_none ocr.demand_rfo.l3_hit_s.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_hit_s.snoop_miss Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200080 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD ocr.pf_l3_rfo.l3_hit_f.snoop_none This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_f.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020490 offcore_response.all_pf_rfo.l3_hit_e.snoop_miss offcore_response.all_pf_rfo.l3_hit_f.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE offcore_response.all_reads.l3_hit_f.hit_other_core_no_fwd offcore_response.all_reads.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.all_rfo.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP offcore_response.all_rfo.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS offcore_response.demand_data_rd.l3_hit_f.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS offcore_response.other.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE offcore_response.pf_l2_data_rd.l3_hit_e.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE offcore_response.pf_l3_data_rd.l3_hit_f.hitm_other_core offcore_response.pf_l3_data_rd.l3_hit_s.snoop_none offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_fwd offcore_response.pf_l3_rfo.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD fp_arith_inst_retired2.256bit_packed_bf16 ocr.all_data_rd.l3_miss.snoop_none ocr.all_data_rd.l3_miss_local_dram.hit_other_core_fwd ocr.all_data_rd.l3_miss_local_dram.snoop_miss OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000120 ocr.all_pf_rfo.l3_miss.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F900007F7 OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000122 OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000004 ocr.demand_data_rd.l3_miss.snoop_none Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000100 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP offcore_response.all_reads.l3_miss_local_dram.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.demand_rfo.l3_miss_local_dram.hitm_other_core offcore_response.demand_rfo.l3_miss_local_dram.no_snoop_needed offcore_response.demand_rfo.l3_miss_remote_hop1_dram.any_snoop offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.pf_l1d_and_sw.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_pf_data_rd.pmm_hit_local_pmm.any_snoop OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS ocr.all_pf_rfo.supplier_none.any_snoop ocr.all_pf_rfo.supplier_none.hitm_other_core OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE ocr.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed ocr.demand_rfo.pmm_hit_local_pmm.snoop_none ocr.pf_l1d_and_sw.supplier_none.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP ocr.pf_l2_rfo.supplier_none.hitm_other_core Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE ocr.pf_l3_data_rd.supplier_none.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE unc_m_pmm_cmd1.all Writes UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 event=0x36,umask=0x21,config1=0x40433 unc_m2m_tag_hit.nm_ufill_hit_clean event=0xd1,period=100021,umask=0x10 ocr.demand_data_rd.l3_hit.snoop_sent Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0010 event=0x60,cmask=1,period=1000003,umask=0x4 event=0xc7,period=100003,umask=0x2 event=0xab,period=100003,umask=0x2 event=0xc6,period=100007,umask=0x1,frontend=0x500106 event=0xc6,period=100007,umask=0x1,frontend=0x500206 CPU_CLK_UNHALTED.DISTRIBUTED event=0xc8,period=100003,umask=0x8 Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall misc_retired.lbr_inserts resource_stalls.scoreboard Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD ocr.demand_data_rd.l3_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000001 Counts cacheable and non-cacheable code reads to the core Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400400 Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache Hit snoop reply with data, line invalidated ocr.demand_rfo.pmm event=0xd3,umask=0x01 event=0xd3,umask=0x10 Clockticks of the uncore caching and home agent (CHA). Unit: uncore_cha TOR Occupancy : CRds issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_rfo unc_cha_tor_inserts.io_hit_itom event=0x35,umask=0xC816FE01 unc_cha_tor_inserts.ia_miss_rfo_local unc_cha_tor_inserts.ia_specitom unc_cha_tor_inserts.io_hit_pcirdcur event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x80 event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x80 unc_iio_txn_req_of_cpu.mem_read.part6 PCIe Completion Buffer Inserts of completions with data: Part 4. Unit: uncore_iio event=0xd5,fc_mask=0x04,umask=0x80 Total IRP occupancy of inbound read and write requests to coherent memory. Unit: uncore_irp Clockticks in the UBOX using a dedicated 48-bit Fixed Counter. Unit: uncore_ubox Number of kfclks. Unit: uncore_upi event=0x34,period=200003,umask=0x20 Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0004 Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line ocr.full_streaming_wr.l3_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000020 ocr.l1wb_m.l3_miss_local event=0x63,period=200003,umask=0x2 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3000000010000 Counts modified writebacks from L1 cache and L2 cache that have any type of response ocr.hwpf_l2_rfo.outstanding Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops event=0x71,period=1000003 TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_inserts.ia_miss_drd_opt_pref FAF allocation -- sent to ADQ Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk) ld_blocks.dtlb_miss Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M Counts the number of memory ordering machine clears triggered by a snoop from an external agent Fraction of branches that are non-taken conditionals. Unit: cpu_core UOPS_RETIRED.ALL / INST_RETIRED.ANY Store_Fwd_Blocks 100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS INST_RETIRED.ANY / ( BR_INST_RETIRED.FAR_BRANCH / 2 ) BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES Microcode_Uop_Ratio Percentage of all uops which are IDiv uops. Unit: cpu_atom event=0xd0,period=1000003,umask=0x5,ldlat=0x200 RFO requests that miss L2 cache. Unit: cpu_core Retired load instructions with locked access Supports address when precise (Precise event). Unit: cpu_core Retired Instructions who experienced DSB miss (Precise event). Unit: cpu_core Retired instructions after front-end starvation of at least 2 cycles (Precise event). Unit: cpu_core event=0x79,cmask=1,edge=1,period=100003,umask=0x20 Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles Supports address when precise (Must be precise). Unit: cpu_core Counts the number of near CALL branch instructions retired (Precise event). Unit: cpu_atom Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs (Precise event). Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions. Unit: cpu_atom event=0xad,period=500009,umask=0x1 event=0xa8,cmask=6,period=2000003,umask=0x1 event=0xb2,period=2000003,umask=0x40 Any Rank at Warm state. Unit: uncore_imc unc_m_pre_count_page_miss Counts all L2 requests.[This event is alias to L2_RQSTS.REFERENCES] Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches Retired memory uops for any access event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008000004 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1030000001 fp_arith_inst_retired2.scalar FRONTEND_RETIRED.MS_FLOWS (Precise event) event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FC00002 exe.amx_busy Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode AMX_OPS_RETIRED.BF16 event=0xec,period=2000003,umask=0x70 Uops executed on ports 4 and 9 unc_m_pre_count.ufill_pch1 unc_m_pmm_rpq_occupancy.gnt_wait_sch1 unc_iio_txn_req_of_cpu.peer_write.part7 event=0x36,umask=0x00c817fe01 TOR Occupancy for DRd misses from local IA. Unit: uncore_cha event=0x36,umask=0x00c8178601 unc_upi_rxl_flits.null Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode. Unit: uncore_upi event=0xc0,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000001 Number Transactions requested by the CPU : Core writing to Cards MMIO space. Unit: uncore_iio event=0x21,umask=0x0340 Tracker Occupancy : Channel 0. Unit: uncore_m2m event=0x56,umask=0x0000000005 unc_cha_tor_inserts.irq_ia event=0x35,umask=0x0000000080 unc_cha_tor_inserts.rem_all TOR Inserts; DRd Pref hits from local IA. Unit: uncore_cha TOR Inserts; LLCPrefRFO from local IA. Unit: uncore_cha event=0x35,umask=0x00c8077e01 TOR Occupancy; ITOM misses from local IO. Unit: uncore_cha TOR Occupancy; DRd Opt hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.io_rfo TOR Occupancy; CRd Pref from local IA. Unit: uncore_cha TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs. Unit: uncore_cha event=0x36,umask=0x00cccffe01 TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally. Unit: uncore_cha TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha TOR Occupancy : WiLs issued by iA Cores that Missed LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_remote_wcil_pmm unc_cha_tor_occupancy.ddr event=0x84 l2_request_g2.ls_rd_sized All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates event=0x61,umask=0x01 LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests event=0x64,umask=0x08 ex_ret_brn_ind_misp event=0xc7,umask=0x38 event=0x147,umask=0x38 event=0,umask=0x04 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8 fp_ret_sse_avx_ops.sp_mult_flops Number of Ops that are candidates for optimization (have Z-bit either set or pass) ls_inef_sw_pref.data_pipe_sw_pf_dc_hit Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable l2_cache l3_read_miss_latency all_remote_links_outbound ls_locks.spec_lock_hi_spec de_dis_uops_from_decoder Cycles where a dispatch group is valid but does not get dispatched due to a token stall. SC AGU dispatch stall Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ3_0_TokenStall ic_tag_hit_miss.all_instruction_cache_accesses Add/subtract FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent SSE/AVX control word mispredict traps. The number of serializing Ops retired L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB event=0x78,umask=0xff l1_data_cache_fills_from_memory Retired conditional branch instructions Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations ls_any_fills_from_sys.near_cache ls_inef_sw_pref.all event=0x70,umask=0x40 Average sampled latency from all data sources. Unit: amd_l3 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 0 remote_processor_write_data_beats_cs5 event=0x1df,umask=0xbff event=0x2df,umask=0xbff local_socket_inf0_inbound_data_beats_ccm6 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 6 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 7 event=0x59e,umask=0x7ff event=0x4df,umask=0x7ff event=0x55f,umask=0x7ff event=0x5df,umask=0x7ff remote_socket_inf1_inbound_data_beats_ccm3 event=0x49f,umask=0xbff remote_socket_inf1_outbound_data_beats_ccm3 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 6 local_socket_outbound_data_beats_link3 Retired scalar floating-point subtract ops Retired scalar floating-point ops of all types Retired floating-point ops of all types event=0xb,umask=0x04 sse_avx_ops_retired.mmx_shuffle event=0xc,umask=0x07 packed_int_op_type.int128_aes event=0xd,umask=0xb0 Retired 256-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xe,umask=0x0f Number of PRECHARGE commands sent for writes L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages event=0x1a0,umask=0x01 event=0x1a0,umask=0x60 d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - (6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@), total_dispatch_slots) PipelineL2;bad_speculation_group L2 cache hits from L1 data cache misses Op cache miss ratio for all fetches L1 data cache fills from DRAM or MMIO in any NUMA node DDRC write commands Total cache hits. Unit: uncore_imc FP_CYCLES_WITH_NO_FPU_OPS_RETIRED LS_SEGMENT_REGISTER_LOAD LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE LS_LOCKED_OPERATION DC_REFILL_FROM_SYSTEM FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES FR_DISPATCH_STALL_WHEN_LS_IS_FULL PC_PROC_RETURN MEM_ERROR EVENT_01H EVENT_1CH EVENT_37H EVENT_50H EVENT_7BH EVENT_91H EVENT_A2H EVENT_C2H EVENT_E6H EVENT_107H EVENT_109H EVENT_11DH EVENT_12CH EVENT_133H EVENT_13EH EVENT_1F3H EVENT_1F9H EVENT_1FAH EVENT_220H EVENT_22FH EVENT_241H EVENT_244H EVENT_269H EVENT_313H EVENT_346H EVENT_351H EVENT_372H EVENT_382H EVENT_39FH EVENT_3B7H EVENT_3D1H EVENT_3DEH EVENT_3E2H L1D_CACHE_INVAL L2D_CACHE_WB_CLEAN L1D_TLB_RD hnf_slc_eviction hnf_qos_hh_retry hni_rdt_rd_occ_cnt_ovfl rnd_rdb_ord clkdiv2_waiting_for_mi STORE_INSTR_COMPLETED LS_LM_INSTR_PIECES ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD FAST_BTIC_HIT L2_TOUCH_HITS L3_CACHE_CASTOUTS DTQ_FULL_CYCLES BUS_RETRY_DUE_TO_INTERVENTION_ORDERING VPU_MARKED_INSTR_COMPLETED FPU_LONG_INSTR_COMPLETION_STALL GCT_EMPTY_BY_BRANCH_MISS_PREDICT LOAD_MISS_LDQ_FULL ADDRESS_COLLISION_CYCLES DATA_MMU_VSP_RELOADS L2_CACHE_DATA_ACCESSES multiply-pipe-junk-ops instructions k8-fr-retired-x86-instructions WRITE ARMV7 INTEL_WESTMERE INTEL_WESTMERE_EX state error BRANCH_MISSES_RETIRED = GenuineIntel-6-56 v9 v15 pme_test_soc_sys Bad_Speculation ( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES Load_Miss_Real_Latency Mem;MemoryBound;MemoryLat L2MPKI_All L2 cache hits per kilo instruction for all request types (including speculative) Page_Walks_Utilization_SMT HPC;Mem;MemoryBW;SoC SoC (cstate_pkg@c6\-residency@ / msr@tsc@) * 100 Cycles a demand request was blocked due to Fill Buffers inavailability l2_lines_out.demand_clean Clean L2 cache lines evicted by demand Demand Data Read miss L2, no rejects l2_rqsts.references event=0x24,period=200003,umask=0xff l2_trans.all_requests event=0x2e,period=100003,umask=0x4f event=0xd0,period=100003,umask=0x42 This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore Offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: BDM76 Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.packed Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ? Number of X87 assists due to input value event=0xca,period=100003,umask=0x2 Cycles Decode Stream Buffer (DSB) is delivering 4 Uops idq.all_mite_cycles_any_uops idq.dsb_cycles idq.ms_mite_uops idq_uops_not_delivered.cycles_fe_was_ok event=0x9c,cmask=3,period=2000003,umask=0x1 event=0xc9,period=2000003,umask=0x10 Number of times a RTM caused a fault Number of times RTM aborted and was not due to the abort conditions in subevents 3-6 event=0x5d,period=2000003,umask=0x2 event=0x54,period=2000003,umask=0x20 Number of intervals between processor halts while thread is in ring 0 This event counts when there is a transition from ring 1,2 or 3 to ring0 This event counts taken speculative and retired direct near calls br_misp_retired.conditional cpu_clk_unhalted.ref_tsc Core cycles when the thread is not in halt state This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time event=0xa3,cmask=8,period=2000003,umask=0x8 cycle_activity.cycles_l2_pending cycle_activity.stalls_total Number of instructions retired. General Counter - architectural event Spec update: BDM61 event=0x3,period=100003,umask=0x8 uops_executed.cycles_ge_1_uop_exec Cycles per core when uops are dispatched to port 3 uops_executed_port.port_4_core event=0xa1,any=1,period=2000003,umask=0x80 This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used (Precise event) LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox event=0x35,umask=0x3,filter_opc=0x191 unc_p_clockticks event=0x8,period=2000003,umask=0x10 This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 event=0x49,period=100003,umask=0x2 event=0xae,period=100007,umask=0x1 Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages page_walker_loads.dtlb_l2 This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on) offcore_response.all_data_rd.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0091 offcore_response.all_data_rd.supplier_none.any_snoop Counts all prefetch code reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0240 offcore_response.all_pf_code_rd.supplier_none.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020090 offcore_response.demand_rfo.l3_hit.snoop_not_needed offcore_response.pf_l2_rfo.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0080 offcore_response.pf_l3_rfo.l3_hit.snoop_miss Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000090 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000090 offcore_response.all_rfo.l3_miss.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000008 offcore_response.other.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.pf_l2_rfo.l3_miss.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000100 This event counts mispredicted conditional branch instructions retired (Precise event) L3 Lookup write request that access cache and found line in M-state unc_arb_trk_occupancy.cycles_with_any_request Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_llc_code_rd.llc_hit.any_response offcore_response.all_data_rd.llc_miss.local_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x087FC00091 l1d_cache.st l2_ld_ifetch.self.e_state l2_ld_ifetch.self.mesi event=0x2b,period=200000,umask=0x41 event=0x32,period=200000,umask=0x40 L2 cache demand requests from this core l2_st.self.i_state fp_assist.ar SIMD packed multiply micro-ops retired simd_uop_type_exec.pack.s decode_stall.iq_full Nonzero segbase store 1 bubble event=0x5,period=200000,umask=0xa prefetch.prefetcht0 event=0x7,period=200000,umask=0x84 event=0x63,period=200000,umask=0x40 event=0x68,period=200000,umask=0xe0 cycles_int_masked.cycles_int_pending_and_masked event=0xc6,period=2000000,umask=0x2 ext_snoop.all_agents.any event=0x3c,period=200000,umask=0x1 event=0x13,period=2000000,umask=0x1 Duration of page-walks in core cycles fetch_stall.icache_fill_pending_cycles Counts load uops retired that miss in the L2 cache Supports address when precise (Must be precise) event=0xd0,period=200003,umask=0x81 Memory uops retired that split a cache-line (Precise event capable) Supports address when precise (Must be precise) Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000022 Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000004 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000001 offcore_response.full_streaming_stores.l2_hit event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600002000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040010 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_needed Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_pf_data_rd.any_response Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.bus_locks.l2_miss.snoop_miss_or_no_snoop_needed offcore_response.demand_code_rd.l2_miss.hitm_other_core event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010001 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010800 Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xc3,period=20003,umask=0x1 Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle Spec update: HSD62, HSD61, HSM63 Counts all prefetch (that bring data to LLC only) code reads hit in the L3 Instruction Decode Queue (IDQ) empty cycles Spec update: HSD135 event=0x14,period=2000003,umask=0x2 Branch instructions at retirement This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle (Precise event) event=0x34,umask=0x28 An external snoop hits a non-modified line in some processor core offcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00020 event=0x28,period=200003,umask=0x1 Not rejected writebacks that missed LLC event=0xf2,period=100003,umask=0x2 Clean L2 cache lines evicted by L2 prefetch event=0x24,period=200003,umask=0x40 RFOs that hit cache lines in M state Retired load uops which data sources missed LLC but serviced from local dram offcore_response.all_code_rd.llc_hit.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010001 Counts all demand data reads that hit in the LLC Cycles per thread when load or STA uops are dispatched to port 3 offcore_response.all_data_rd.llc_hit.snoop_miss Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts all demand code reads that miss the LLC and the data returned from remote dram offcore_response.demand_data_rd.llc_miss.remote_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20080 Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode.streaming_full. Unit: uncore_cbox Memory page activates for reads and writes. Unit: uncore_imc Memory controller clock ticks. Use to generate percentages for memory controller CYCLES events. Unit: uncore_imc unc_p_freq_band1_transitions event=0xe,edge=1,filter_band3=40 Retired load uops that split across a cacheline boundary (Precise event) Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit dsb_fill.other_cancel All (macro) branch instructions retired. (Precise Event - PEBS) (Must be precise) Direct and indirect mispredicted near call instructions retired (Precise event) This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued event=0xa2,period=2000003,umask=0xa uops_dispatched.thread event=0x36,umask=0xa,filter_opc=0x182 event=0x86,period=200003,umask=0x4 Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800083091 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000132f7 offcore_response.any_read.l2_hit_this_tile_s event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400022 offcore_response.any_rfo.l2_hit_far_tile_m offcore_response.any_rfo.l2_hit_this_tile_f Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400001 offcore_response.demand_data_rd.l2_hit_this_tile_e event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400002 Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.partial_reads.l2_hit_near_tile_e_f offcore_response.partial_streaming_stores.any_response offcore_response.pf_l2_code_rd.l2_hit_this_tile_f offcore_response.pf_l2_rfo.l2_hit_far_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180020 offcore_response.pf_l2_rfo.l2_hit_this_tile_f offcore_response.pf_software.l2_hit_far_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800044 Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far) offcore_response.any_pf_l2.mcdram_far offcore_response.any_read.mcdram event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000002 Counts Demand cacheable data writes that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400002 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200100 offcore_response.pf_l1_data_rd.mcdram_far offcore_response.pf_l2_code_rd.ddr offcore_response.pf_software.mcdram_far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200200 recycleq.ld_block_std_notready rs_full_stall.mec All references to the L1 data cache L2 requests event=0x24,period=200000,umask=0xaa L2 writeback to LLC transactions l2_write.lock.mesi event=0xb,period=5000,umask=0x10,ldlat=0x20 Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) mem_uncore_retired.remote_cache_local_home_hit offcore_response.any_ifetch.io_csr_mmio offcore_response.any_ifetch.local_cache offcore_response.any_ifetch.remote_cache offcore_response.any_request.llc_hit_other_core_hit offcore_response.any_request.remote_cache_dram Offcore requests satisfied by a remote cache or remote DRAM offcore_response.any_rfo.any_location Offcore RFO requests that HIT in a remote cache offcore_response.data_ifetch.llc_hit_other_core_hit offcore_response.data_in.local_cache Offcore demand data requests satisfied by the IO, CSR, MMIO unit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1803 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x701 Offcore demand RFO requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3880 All offcore prefetch data requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8010 Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4720 offcore_response.pf_rfo.remote_cache_hitm offcore_response.prefetch.llc_hit_other_core_hit event=0x6,period=200000,umask=0x4 fp_assist.all event=0x12,period=200000,umask=0x4 event=0x12,period=200000,umask=0x20 simd_int_128.unpack SIMD integer 64 bit arithmetic operations macro_insts.decoded event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6008 offcore_response.demand_data.remote_dram offcore_response.demand_rfo.local_dram Offcore prefetch code reads satisfied by any DRAM Offcore prefetch code reads satisfied by the local DRAM Offcore prefetch requests that missed the LLC Super Queue full stall cycles event=0xe6,period=2000000,umask=0x2 Call branches executed Retired near call instructions (Precise Event) br_misp_exec.any event=0xd2,period=2000000,umask=0xf All RAT stall cycles FPU control word write stall cycles Cycles Uops executed on any port (core count) Macro-fused Uops retired (Precise Event) Uop unfusions due to FP exceptions DTLB load misses event=0x85,period=200000,umask=0x1 Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB) Supports address when precise (Precise event) Counts retired load instructions with at least one uop that missed in the L3 cache Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0020004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020004 offcore_response.demand_data_rd.l4_hit_local_l4.any_snoop offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020002 offcore_response.other.l3_hit_s.snoop_miss Retired Instructions who experienced iTLB true miss (Precise event) Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) hle_retired.aborted_timer event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C0001 Number of hardware interrupts received by the processor Cycles total of 1 uop is executed on all ports and Reservation Station was not empty Number of all retired NOP instructions Spec update: SKL091, SKL044 (Precise event) Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events Uops inserted at issue-stage in order to preserve upper bits of vector registers Ret_SMT IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) ( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) ) Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed offcore_response.any_code_rd.l2_miss.snoop_miss Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000002 Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000080 Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response D-side page-walks event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0122 offcore_response.pf_ifetch.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80408fff offcore_response.demand_rfo.llc_miss.dram Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram Outstanding offcore demand data reads event=0xb7,period=100000,umask=0x1,offcore_rsp=0xffff event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5008 REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f08 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f77 REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM offcore_response.demand_data.all_local_dram_and_remote_cache_hit REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM load_block.overlap_store Mispredicted retired branch instructions (Precise Event) event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5801 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5840 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2720 Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0491 offcore_response.all_pf_data_rd.l3_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10010 offcore_response.pf_l2_rfo.l3_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00120 offcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00100 Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions. SMT version; use when SMT is enabled and measuring per logical CPU event=0x35,umask=0x21,config1=0x40040e33 Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline Rsp*Fwd*WB Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership unc_iio_comp_buf_inserts.cmpd.part2 event=0xc2,ch_mask=0x08,fc_mask=0x4,umask=0x03 unc_iio_data_req_by_cpu.mem_write.part0 Write request of 4 bytes made to IIO Part2 by the CPU. Unit: uncore_iio event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x08 unc_iio_data_req_by_cpu.peer_read.part2 unc_iio_txn_req_by_cpu.mem_read.part0 event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x01 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_iio_txn_req_of_cpu.mem_write.part3 event=0x10,umask=0x10 Inbound read requests received by the IRP and inserted into the FAF queue. Unit: uncore_irp unc_m2m_direct2core_taken Multi-socket cacheline Directory update from/to Any state. Unit: uncore_m2m Counts cycles when the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP ocr.all_data_rd.l3_hit_e.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_hit_f.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040490 ocr.all_pf_data_rd.l3_hit_m.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0120 OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800407F7 OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0004 ocr.demand_code_rd.l3_hit_e.hit_other_core_fwd ocr.demand_code_rd.l3_hit_s.any_snoop ocr.demand_code_rd.l3_hit_s.snoop_none Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP ocr.demand_data_rd.l3_hit_f.hitm_other_core Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200001 Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit_m.snoop_none Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_hit_e.hitm_other_core ocr.demand_rfo.l3_hit_f.hit_other_core_fwd ocr.demand_rfo.l3_hit_s.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C8000 Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_m.no_snoop_needed Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS ocr.pf_l2_rfo.l3_hit_s.hit_other_core_fwd ocr.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd ocr.pf_l3_data_rd.l3_hit_f.hitm_other_core ocr.pf_l3_data_rd.l3_hit_f.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080100 ocr.pf_l3_rfo.l3_hit_e.snoop_miss Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE ocr.pf_l3_rfo.l3_hit_m.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE offcore_response.all_reads.l3_hit_m.any_snoop offcore_response.all_reads.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE offcore_response.all_rfo.l3_hit_s.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020122 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_hit_f.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.other.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_hit_e.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.pf_l2_rfo.l3_hit_f.snoop_miss offcore_response.pf_l2_rfo.supplier_none.hit_other_core_no_fwd offcore_response.pf_l3_data_rd.l3_hit_s.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020080 offcore_response.pf_l3_rfo.l3_hit.hit_other_core_fwd IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS) Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events ocr.all_pf_data_rd.l3_miss.hit_other_core_no_fwd ocr.all_pf_data_rd.l3_miss.remote_hit_forward OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwd OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000120 ocr.all_reads.l3_miss.hit_other_core_fwd ocr.all_rfo.l3_miss.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000122 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_miss.hit_other_core_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP ocr.demand_rfo.l3_miss_local_dram.hitm_other_core Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90008000 ocr.other.l3_miss_remote_hop1_dram.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90008000 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM ocr.pf_l3_rfo.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000100 offcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_fwd offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoop offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.pf_l1d_and_sw.l3_miss_local_dram.any_snoop offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwd offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED ocr.all_pf_data_rd.supplier_none.hit_other_core_no_fwd OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP ocr.pf_l2_data_rd.supplier_none.any_snoop unc_m_pmm_rpq_occupancy.all 6000000000ns event=0xea,umask=0x1 TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts l2_rqsts.swpf_miss ocr.hwpf_l2_rfo.l3_hit.snoop_hit_no_fwd Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request event=0x32,period=100003,umask=0x1 Counts the number of PREFETCHT0 instructions executed event=0xc7,period=100003,umask=0x80 Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events Retired instructions after front-end starvation of at least 2 cycles (Precise event) Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled event=0x9c,cmask=1,inv=1,period=1000003,umask=0x1 icl metrics (cstate_pkg@c8\-residency@ / msr@tsc@) * 100 Counts the number of times HLE commit succeeded Counts streaming stores that was not supplied by the L3 cache Counts hardware prefetch RFOs (which bring data to L2) that have any type of response ocr.streaming_wr.dram Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists cpu_clk_unhalted.ref_distributed Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder topdown.br_mispredict_slots uops_dispatched.port_2_3 Counts the cycles for which the thread is active and the superQ cannot take any more entries Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket ocr.reads_to_core.remote_cache.snoop_hitm Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent. Unit: uncore_cha event=0x50,umask=0x08 TOR Inserts : All requests from iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_llcprefrfo unc_cha_tor_inserts.ia_miss_rfo event=0x35,umask=0xCC43FE04 event=0xc0 unc_cha_tor_inserts.ia_rfo_pref TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_remote event=0x36,umask=0xC8177E01 event=0x35,umask=0xC8F3FE04 unc_iio_data_req_of_cpu.cmpd.part2 unc_iio_data_req_by_cpu.mem_write.part4 unc_iio_txn_req_of_cpu.mem_read.part5 event=0xc2,ch_mask=0x20,fc_mask=0x04,umask=0x03 event=0xd5,fc_mask=0x04,umask=0x40 event=0x2d,umask=0x01 event=0x35,umask=0xCC42FF04 event=0x35,umask=0xCC437F04 Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0477 ocr.uc_rd.l3_hit.snoop_hit_with_fwd c0_stalls.load_llc_hit Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response Counts the total number of branch instructions retired for all branch types (Precise event) ld_blocks.all Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts topdown_fe_bound.frontend_bandwidth event=0x35,umask=0xC001FE01,config1=0x40041e33 TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0x35,umask=0xC8A7FE01 event=0x35,umask=0xC87FDE01 TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 event=0x8,period=200003,umask=0xe cycles:k / cycles ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED Instructions per Branch (lower number means higher occurrence rate). Unit: cpu_core Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Unit: cpu_atom Cycle cost per DRAM hit. Unit: cpu_atom Percent of instruction miss cost that hit in DRAM. Unit: cpu_atom mem_scheduler_block.st_buf Counts the number of cycles that uops are blocked due to a store buffer full condition. Unit: cpu_atom Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise). Unit: cpu_atom event=0xc1,period=1000003,umask=0x10 memory_activity.stalls_l1d_miss Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC). Unit: cpu_core Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses. Unit: cpu_atom Return instructions retired (Precise event). Unit: cpu_core event=0xe7,period=1000003,umask=0x13 TMA slots wasted due to incorrect speculations. Unit: cpu_core Uops executed on ports 7 and 8. Unit: cpu_core unc_m_prefetch_rd unc_m_dram_thermal_warm Write CAS command sent to DRAM. Unit: uncore_imc Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels). Unit: uncore_imc event=0x5,period=1000003,umask=0x90 Page walks completed due to a demand data load to a 2M/4M page. Unit: cpu_core event=0x13,cmask=1,period=100003,umask=0x10 Page walks completed due to a demand data store to a 1G page. Unit: cpu_core event=0x11,period=100003,umask=0x20 MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM Supports address when precise event=0x2a,period=100003,umask=0x1,offcore_rsp=0x4003C0001 Counts the total number of uops delivered by the Microcode Sequencer (MS) Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM This event is deprecated. Refer to new event ARITH.DIV_ACTIVE cpu_clk_unhalted.c0_wait Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0 (Precise event) unc_m_cas_count.rd_pre_underfill unc_m_pre_count.pgt_pch1 event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000001 event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000002 TOR Inserts for DRd Pref misses from local IA targeting local memory. Unit: uncore_cha Valid Flits Received : Slot 2. Unit: uncore_upi Valid Flits Received : Slot NULL or LLCRD Empty. Unit: uncore_upi event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000004 event=0xc2,ch_mask=0x01,fc_mask=0x07,umask=0x0000000004 TOR Inserts; LLCPrefRFO hits from local IA. Unit: uncore_cha TOR Inserts; misses from Local IA. Unit: uncore_cha TOR Inserts : MMCFG Access. Unit: uncore_cha TOR Inserts; DRd Opt Pref hits from local IA. Unit: uncore_cha TOR Occupancy; Hits from local IA. Unit: uncore_cha TOR Occupancy : All from Local IO. Unit: uncore_cha unc_cha_tor_occupancy.miss unc_cha_tor_occupancy.mmio event=0x36,umask=0x00c887ff01 event=0x36,umask=0x00C896FE01 event=0x36,umask=0x00ccd7ff01 TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally. Unit: uncore_cha event=0x35,umask=0x00CD47FF01 unc_cha_tor_inserts.io_wbmtoi unc_cha_tor_occupancy.ia_miss_drd_pref_local_pmm TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC. Unit: uncore_cha TOR Inserts : PMM Access. Unit: uncore_cha ic_fetch_stall.ic_stall_any l2_cache_req_stat.ls_rd_blk_x Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types) event=0x64,umask=0xf6 event=0x1,umask=0x80 ex_ret_brn_tkn amd_df The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1 fp_ret_sse_avx_ops.sp_div_flops event=0x29,umask=0x04 ls_l1_d_tlb_miss.all Total Page Table Walks IC Type 1 Cycles not in Halt OC Mode Switch. OC to IC mode switch event=0x29,umask=0x07 l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 tlb uops_retired L2 Branch Prediction Overrides Existing Prediction (speculative) ex_ret_cond_misp event=0xe,umask=0x02 ls_ret_cl_flush Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed Count of dispatched Ops from Decoder The number of times the instruction decoder overrides the predicted target ic_tag_hit_miss.instruction_cache_miss event=0x44,umask=0x02 event=0x44,umask=0x01 The number of 64B misaligned (i.e., cacheline crossing) loads Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node ls_hw_pf_dc_fills.mem_io_local de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc de_dis_dispatch_token_stalls2.int_sch3_token_stall event=0x44,umask=0xff decoder Retired taken branch instructions mispredicted l2_request_g1.all event=0x70,umask=0x01 L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all types l2_pf_miss_l2_hit_l3.l1_stream L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node. Unit: amd_l3 local_processor_read_data_beats_cs3 local_processor_read_data_beats_cs8 local_processor_write_data_beats_cs0 local_processor_write_data_beats_cs5 event=0x1df,umask=0x7ff Write data beats (64 bytes) for remote processor at Coherent Station (CS) 9 local_socket_upstream_read_beats_iom3 event=0x81f,umask=0x7ff Read data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0 local_socket_inf1_inbound_data_beats_ccm6 remote_socket_inf0_inbound_data_beats_ccm3 remote_socket_inf0_inbound_data_beats_ccm7 event=0x5de,umask=0xbfe remote_socket_inf0_outbound_data_beats_ccm1 remote_socket_inf1_outbound_data_beats_ccm2 local_socket_outbound_data_beats_link5 event=0x8,umask=0x02 Retired vector floating-point blend ops event=0xb,umask=0x07 event=0xc,umask=0x02 event=0xc,umask=0x50 fp_pack_ops_retired.fp256_logical Retired 128-bit packed integer add ops Retired 256-bit packed integer logical ops Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full Number of cycles dispatch is stalled for integer scheduler queue 2 tokens Number of cycles dispatch is stalled for retire queue tokens de_no_dispatch_per_slot.smt_contention L2 cache accesses from L2 cache hardware prefetcher l1_demand_data_cache_fills_from_same_ccx Outbound data from all links (local socket) umc_data_bus_utilization umc_cas_cmd_read_ratio umc_cas_cmd_write_ratio d_ratio(umc_act_cmd.all * 1000, umc_mem_clk) uncore_imc_free_running.cache_miss L1_DCACHE_REFILL PC_IMM_BRANCH EVENT_07H EVENT_26H EVENT_2EH EVENT_8DH EVENT_93H EVENT_ADH EVENT_B7H EVENT_E8H EVENT_FEH EVENT_120H EVENT_12DH EVENT_12FH EVENT_13FH EVENT_155H EVENT_165H EVENT_1A9H EVENT_28DH EVENT_2BCH EVENT_2E0H EVENT_31CH EVENT_326H EVENT_344H EVENT_358H EVENT_375H EVENT_38BH EVENT_3DCH EVENT_3EBH EVENT_3F9H BR_MIS_PRED_RETIRED L2D_TLB_WR hnf_cache_miss hnf_slc_fill_invalid_way hni_wdb_alloc sbsx_awvalid_no_awready cxla_tx_tlp_link2 WRITE_THROUGH_STORES LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1 LSU_INSTR_COMPLETED BRANCH_LINK_STACK_MISPREDICTED FOLDED_BRANCHES L2SQ_FULL_CYCLES GROUP_COMPLETED DVT0_DETECTED DVT4_DETECTED UCP SOFT INTEL_ATOM_SILVERMONT INTEL_BROADWELL unknown event desc: %s
ex_ret_brn RESOURCE_STALL GenuineIntel-6-1C v18 GenuineIntel-6-97 testcpu Bad_Speculation_SMT 1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) Instruction per taken branch Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear) Bad;BrMispredicts_SMT Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE ) L2 cache misses per kilo instruction for all request types (including speculative) CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k DRAM_BW_Use cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182\,thresh\=1@ event=0x48,cmask=1,period=2000003,umask=0x2 l1d_pend_miss.pending_cycles_any event=0xf2,period=100003,umask=0x5 This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted All requests that miss L2 cache This event counts Demand Data Read requests that access L2 cache, including rejects event=0xf0,period=200003,umask=0x10 This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache Supports address when precise. Spec update: BDM35 (Precise event) This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS Spec update: BDM76 event=0x60,cmask=1,period=2000003,umask=0x4 event=0xe6,period=100003,umask=0x1f This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop.
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer Loads with latency value being above 16 Spec update: BDM100, BDM35 (Must be precise) mem_trans_retired.load_latency_gt_32 Loads with latency value being above 4 Spec update: BDM100, BDM35 (Must be precise) This event counts loads with latency value being above 512 Spec update: BDM100, BDM35 (Must be precise) Loads with latency value being above 8 Spec update: BDM100, BDM35 (Must be precise) event=0x54,period=2000003,umask=0x2 tx_mem.abort_hle_elision_buffer_unsupported_alignment This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode event=0x5c,period=2000003,umask=0x2 br_inst_retired.conditional This event counts both taken and not taken speculative and retired mispredicted branch instructions br_misp_exec.taken_conditional Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate) Cycles Uops delivered by the LSD, but didn't come from the decoder lsd.uops This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6 Cycles where at least 4 uops were executed per-thread uops_retired.total_cycles M line forwarded from remote cache along with writeback to memory. Unit: uncore_ha M line forwarded from remote cache with no writeback to memory. Unit: uncore_ha event=0x86 event=0x80,occ_sel=3 (UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCKTICKS) * 100. power_state_occupancy.cores_c6 % (UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKTICKS) * 100. unc_p_freq_max_os_cycles dtlb_load_misses.walk_completed_2m_4m Store misses in all DTLB levels that cause completed page walks Spec update: BDM69 event=0x85,period=100003,umask=0x20 page_walker_loads.dtlb_memory event=0xbc,period=2000003,umask=0x22 Miss in last-level (L3) cache. Excludes Unknown data-source Supports address when precise. Spec update: BDM100, BDE70 (Precise event) offcore_requests.all_requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020091 offcore_response.all_pf_code_rd.supplier_none.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0090 offcore_response.all_pf_data_rd.l3_hit.snoop_hit_no_fwd offcore_response.corewb.supplier_none.snoop_hitm offcore_response.demand_code_rd.supplier_none.snoop_not_needed Counts demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020001 offcore_response.other.l3_hit.snoop_hitm Counts all prefetch (that bring data to LLC only) code reads Counts prefetch (that bring data to L2) data reads offcore_response.pf_l2_rfo.l3_hit.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0080 offcore_response.pf_l3_data_rd.supplier_none.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020100 offcore_response.all_pf_code_rd.l3_miss_local_dram.any_snoop offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss offcore_response.all_pf_rfo.l3_miss.snoop_hit_no_fwd offcore_response.all_rfo.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0004 offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000040 offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoop offcore_response.pf_l2_rfo.l3_miss.snoop_not_needed offcore_response.pf_l3_code_rd.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000080 offcore_response.pf_l3_rfo.l3_miss.snoop_not_needed offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoop A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core L3 Lookup read request that access cache and found line in I-state. Unit: uncore_cbox Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC bdx metrics event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C07F7 Counts all data/code/rfo reads (demand & prefetch)miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x063BC007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC08FFF qpi_ctl_bandwidth_tx (UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100. event=0x29,period=200000,umask=0x74 event=0x29,period=200000,umask=0x48 event=0x29,period=200000,umask=0x51 event=0x29,period=200000,umask=0x52 All read requests from L1 instruction and data caches event=0x25,period=200000,umask=0x40 Retired computational Streaming SIMD Extensions (SSE) packed-single instructions event=0xb0,period=2000000,umask=0x0 SIMD packed arithmetic micro-ops executed Floating point computational micro-ops retired (Must be precise) event=0x10,period=2000000,umask=0x2 event=0x80,period=200000,umask=0x3 This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ event=0x5,period=200000,umask=0x91 Invalidate bus transactions bus_trans_wb.self event=0x3a,period=200000,umask=0x0 event=0x77,period=200000,umask=0x8 br_inst_retired.taken All indirect calls, including both register and memory indirect event=0x89,period=200000,umask=0x4 cpu_clk_unhalted.ref Reference cycles when core is not halted event=0x3,period=200000,umask=0x1 Duration of D-side only page walks Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback Counts memory requests originating from the core that reference a cache line in the L2 cache mem_load_uops_retired.hitm event=0xb7,period=100007,umask=0x1 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200003091 Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000020 Counts data cache lines requests by software prefetch instructions that miss the L2 cache Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module event=0xc2,period=2000003,umask=0x8 Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches baclears.return Counts the number of taken branch instructions retired (Must be precise) br_inst_retired.jcc Counts near return branch instructions retired (Must be precise) Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000014800 Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired (Must be precise) l1d_pend_miss.request_fb_full Demand requests to L2 cache Spec update: HSD78, HSM80 Counts all L2 store RFO requests Retired load uops missed L2. Unknown data source excluded Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired load uops missed L3. Excludes unknown data source Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently offcore_response.demand_data_rd.l3_miss.local_dram Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling Execution stalls due to memory subsystem This events counts the cycles where at least three uop were executed. It is counted per thread Spec update: HSD144, HSD30, HSM31 unc_cbo_xsnp_response.hitm_external This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks page_walker_loads.ept_dtlb_l2 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400122 offcore_response.demand_rfo.llc_miss.local_dram Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache (Precise event) Retired load uops with L2 cache misses as data sources (Precise event) Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.all_data_rd.llc_hit.no_snoop_needed event=0x10,period=2000003,umask=0x10 Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle event=0x10,period=2000003,umask=0x20 event=0x10,period=2000003,umask=0x1 other_assists.avx_store simd_fp_256.packed_double event=0xab,period=2000003,umask=0x1 Counts LLC replacements event=0xa1,any=1,period=2000003,umask=0x30 Filter on processor core initiated cacheable read requests Filter on external snoop requests. Unit: uncore_cbox event=0x8,period=100003,umask=0x81 Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0040 Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0010 Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800010 offcore_response.pf_l2_data_rd.llc_miss.remote_hit_forward Counts prefetch (that bring data to LLC only) data reads that miss in the LLC llc_references.pcie_ns_read unc_c_tor_occupancy.miss_local event=0xe,edge=1 Retired store uops that split across a cacheline boundary (Precise event) Number of AVX-256 Computational FP double precision uops issued this cycle This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual offcore_response.any_pf_l2.any_response Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x10000832f7 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400022 offcore_response.bus_locks.l2_hit_this_tile_s Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400004 Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.demand_code_rd.l2_hit_this_tile_f offcore_response.demand_rfo.l2_hit_near_tile offcore_response.demand_rfo.l2_hit_this_tile_f offcore_response.partial_reads.outstanding offcore_response.partial_writes.l2_hit_this_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800402000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004002000 offcore_response.pf_software.l2_hit_far_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000200 offcore_response.uc_code_reads.outstanding This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00808032f7 Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far) offcore_response.any_rfo.mcdram_far Counts Bus locks and split lock requests that accounts for data responses from DRAM Far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600400 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000004 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600004 offcore_response.demand_data_rd.mcdram offcore_response.partial_reads.ddr event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600080 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200080 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600200 recycleq.any_ld Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full cache_lock_cycles.l1d_l2 L1 data cache read in S state event=0x42,period=2000000,umask=0x4 L2 data prefetches in the S state L2 lines alloacated L2 modified lines evicted by a demand request mem_inst_retired.latency_above_threshold_0 event=0xb,period=1000,umask=0x10,ldlat=0x80 Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) event=0xf,period=4000,umask=0x80 Offcore data reads satisfied by the LLC and HIT in a sibling core Offcore data reads satisfied by the LLC or local DRAM offcore_response.any_ifetch.llc_hit_other_core_hit offcore_response.any_ifetch.local_cache_dram Offcore code reads satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4FF event=0xb7,period=100000,umask=0x1,offcore_rsp=0x222 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x422 Offcore RFO requests satisfied by a remote cache offcore_response.data_in.local_cache_dram Offcore demand code reads that HIT in a remote cache All offcore demand RFO requests offcore_response.demand_rfo.io_csr_mmio event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1802 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x180 offcore_response.other.llc_hit_other_core_hit Offcore other requests that HIT in a remote cache offcore_response.pf_data.remote_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x810 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8070 Offcore prefetch requests satisfied by the LLC and HIT in a sibling core Cacheable loads delayed with L1D block code SSE2 integer Uops 128 bit SIMD integer logical operations simd_int_128.shuffle_move macro_insts.fusions_decoded Offcore data reads that missed the LLC Offcore demand data reads satisfied by any DRAM event=0x6c,period=2000000,umask=0x1 load_dispatch.mob br_misp_exec.cond br_misp_exec.indirect_near_call Partial register stall cycles event=0xc7,period=200000,umask=0x2 uops_executed.core_active_cycles Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 Counts the RFO (Read-for-Ownership) requests that hit L2 cache Retired load instructions with L3 cache hits as data sources Supports address when precise (Precise event) Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40040001 offcore_response.demand_rfo.l3_hit_s.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C8000 offcore_response.other.l3_hit_e.snoop_hit_no_fwd offcore_response.other.l3_hit_m.snoop_hitm Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) frontend_retired.latency_ge_64 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event) icache_64b.iftag_miss Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB) Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) Counts the number of machine clears due to memory order conflicts Spec update: SKL089 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C400004 offcore_response.demand_data_rd.l3_miss.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C400002 offcore_response.demand_rfo.l3_miss_local_dram.snoop_non_dram Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions partial_rat_stalls.scoreboard event=0xcc,period=2000003,umask=0x40 Counts the number of x87 uops dispatched ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) / BR_INST_RETIRED.ALL_BRANCHES 64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time Fill Buffer (FB) true hits per kilo instructions for retired demand loads Page walk completed due to a demand data load to a 1G page dtlb_store_misses.walk_active All Loads This event counts the number of load ops retired offcore_response.any_request.l2_miss.snoop_miss Counts DCU hardware prefetcher data read that have any response type Uops with lock semantics This event counts the number of load uops retired (Precise Event) (Precise event) Retired load uops that miss the STLB. (Precise Event - PEBS) (Precise event) offcore_response.all_pf_code_rd.llc_hit.snoop_miss offcore_response.all_pf_rfo.llc_hit.hit_other_core_no_fwd Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0xb0,period=100000,umask=0x8 REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5002 offcore_response.other.local_dram_and_remote_cache_hit REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE sq_misc.lru_hints event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf808 offcore_response.corewb.other_local_dram REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2702 offcore_response.all_pf_rfo.l3_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001 Counts L1 data cache hardware prefetch requests and software prefetch requests that have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10020 offcore_response.all_pf_rfo.l3_miss.snoop_miss_or_no_fwd offcore_response.demand_code_rd.l3_miss.remote_hitm offcore_response.pf_l3_rfo.l3_miss.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000100 Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes. SMT version; use when SMT is enabled and measuring per logical CPU Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request) event=0x20 MMIO writes. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x01 event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x01,ch_mask=0x1f UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 unc_cha_llc_victims.total_e Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in Lines Victimized; Lines in F State. Unit: uncore_cha Lines Victimized; Lines in S State. Unit: uncore_cha RspCnflct* Snoop Responses Received. Unit: uncore_cha event=0x5c,umask=0x01 Counts clockticks of the 1GHz trafiic controller clock in the IIO unit PCIe Completion Buffer occupancy of completions with data: Part 3. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_read.part2 unc_iio_data_req_by_cpu.mem_read.part3 Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit. Unit: uncore_iio Write request of up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio event=0x25 Multi-socket cacheline Directory update from I to S. Unit: uncore_m2m unc_m2m_txc_bl_occupancy.all unc_upi_direct_attempts.d2c unc_upi_rxl_bypassed.slot0 Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event Supports address when precise (Precise event) ocr.all_data_rd.l3_hit.hit_other_core_no_fwd ocr.all_data_rd.l3_hit_e.hitm_other_core OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE ocr.all_pf_data_rd.l3_hit.no_snoop_needed ocr.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200490 ocr.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd ocr.all_pf_rfo.l3_hit_f.hitm_other_core OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000807F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x802007F7 OCR.ALL_READS.L3_HIT_M.SNOOP_NONE ocr.all_rfo.l3_hit_e.any_snoop ocr.all_rfo.l3_hit_m.any_snoop OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100122 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE ocr.demand_code_rd.l3_hit_m.any_snoop ocr.demand_code_rd.l3_hit_m.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200001 ocr.demand_data_rd.l3_hit_m.hit_other_core_no_fwd ocr.demand_rfo.l3_hit_m.any_snoop Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD ocr.demand_rfo.l3_hit_m.snoop_none Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C8000 Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80208000 Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_hit.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040080 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0100 ocr.pf_l3_rfo.l3_hit.snoop_miss ocr.pf_l3_rfo.l3_hit_e.hit_other_core_fwd Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_e.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_hit_m.any_snoop offcore_response.all_reads.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.all_reads.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020122 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP offcore_response.demand_code_rd.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.demand_data_rd.l3_hit_e.hit_other_core_fwd offcore_response.demand_data_rd.l3_hit_f.no_snoop_needed offcore_response.demand_data_rd.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.other.l3_hit.snoop_hit_with_fwd This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.pf_l1d_and_sw.l3_hit_e.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400020 offcore_response.pf_l3_data_rd.l3_hit_e.any_snoop offcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000490 OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000122 ocr.demand_code_rd.l3_miss_local_dram.no_snoop_needed ocr.demand_code_rd.l3_miss_remote_hop1_dram.any_snoop ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000002 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000400 ocr.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000080 offcore_response.all_data_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE offcore_response.demand_code_rd.l3_miss.hit_other_core_fwd offcore_response.demand_code_rd.l3_miss.hit_other_core_no_fwd offcore_response.demand_rfo.l3_miss.hit_other_core_fwd offcore_response.other.l3_miss.hitm_other_core offcore_response.other.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_fwd offcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED ocr.all_pf_data_rd.supplier_none.no_snoop_needed OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD ocr.all_pf_rfo.supplier_none.snoop_miss OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD ocr.all_rfo.pmm_hit_local_pmm.snoop_none ocr.demand_code_rd.supplier_none.hitm_other_core Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.pmm_hit_local_pmm.any_snoop ocr.pf_l3_rfo.supplier_none.hitm_other_core Cycles where DRAM ranks are in power down (CKE) mode+C37. Unit: uncore_imc Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc event=0x37,umask=0x8 Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Cache lines that have been L2 hardware prefetched but not used by demand accesses Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3) Counts retired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event) ocr.demand_rfo.l3_hit.snoop_hitm ocr.hwpf_l1d_and_swpf.l3_hit.snoop_miss Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0x32,period=100003,umask=0x8 event=0xc7,period=100003,umask=0x4 Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE Number of switches from DSB or MITE to the MS (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts) Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture ocr.hwpf_l2_data_rd.l3_miss Counts demand data read requests that miss the L3 cache Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184008000 Cycles when divide unit is busy executing divide or square root operations Counts not taken branch instructions retired (Precise event) br_misp_retired.indirect event=0xd,period=500009,umask=0x80 Counts cycles where the pipeline is stalled due to serializing operations Counts cycles when at least 3 micro-ops are executed from any thread on physical core event=0xa6,period=1000003,umask=0x80 Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3) ocr.demand_code_rd.snc_cache.hit_with_fwd Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor ( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / 1000000000 / duration_time Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F04400002 Counts streaming stores that missed the local socket's L1, L2, and L3 caches ocr.demand_code_rd.snc_dram ocr.demand_data_rd.remote_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703000001 ocr.reads_to_core.local_socket_pmm Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent. Unit: uncore_cha TOR Inserts : CRds issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_crd event=0x35,umask=0xC88FFD01 unc_cha_tor_inserts.ia_hit_rfo_pref event=0x36,umask=0xC80FFF01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_remote_pmm unc_cha_tor_inserts.io_miss_pcirdcur TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC. Unit: uncore_cha event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x80 unc_iio_txn_req_of_cpu.cmpd.part3 unc_iio_data_req_of_cpu.mem_write.part4 event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x04 unc_m2m_clockticks Clockticks of the mesh to PCI (M2P). Unit: uncore_m2pcie event=0x35,umask=0xCD437F04 Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0044 ocr.all_code_rd.l3_hit.snoop_not_needed Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache ocr.reads_to_core.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0477 ocr.partial_streaming_wr.l3_miss Counts all hardware and software prefetches that were not supplied by the L3 cache bus_lock.all event=0x63,period=200003,umask=0x1 Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000477 Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired (Precise event) Counts the number of retired loads that are blocked because its address partially overlapped with an older store (Precise event) topdown_be_bound.register Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls) TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 Clockticks of the mesh to PCI (M2P) Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache Counts the number of page walks completed due to load DTLB misses to a 1G page Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward). Unit: cpu_core Backend_Bound_Aux 100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL Percentage of all uops which are x87 uops. Unit: cpu_atom Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM). Unit: cpu_atom Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full. Unit: cpu_atom event=0xd0,period=1000003,umask=0x5,ldlat=0x20 Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise). Unit: cpu_atom This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS. Unit: cpu_core Retired load instructions that miss the STLB Supports address when precise (Precise event). Unit: cpu_core Number of PREFETCHNTA instructions executed. Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles Supports address when precise (Must be precise). Unit: cpu_core event=0x73,period=1000003,umask=0x3 Cycles while memory subsystem has an outstanding load. Unit: cpu_core Cycles total of 1 uop is executed on all ports and Reservation Station was not empty. Unit: cpu_core event=0x75,period=2000003,umask=0x1 event=0xa4,period=10000003,umask=0x4 Uops executed on port 6. Unit: cpu_core Incoming VC1 read request. Unit: uncore_imc Page walks completed due to a demand data load to a 4K page. Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F003C4477 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FC04477 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response ocr.reads_to_core.remote_memory This event counts the cycles the integer divider is busy Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case event=0x10,umask=0x0000000001 event=0x3,umask=0x0000000004 unc_iio_data_req_of_cpu.peer_write.part7 TOR Inserts for DRd misses from local IA. Unit: uncore_cha Valid Flits Received : LLCRD Not Empty. Unit: uncore_upi unc_upi_txl_basic_hdr_match.ncs_opc event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000004 event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000001 AD Ingress (from CMS) : AD Ingress (from CMS) Allocations. Unit: uncore_m2m event=0x35,umask=0x00c817fd01 event=0x35,umask=0x00c807fe01 TOR Inserts : SF/LLC Evictions. Unit: uncore_cha TOR Inserts : RRQ. Unit: uncore_cha TOR Inserts : Just Misses. Unit: uncore_cha event=0x36,umask=0x00c001ff01 unc_cha_tor_occupancy.ia_hit_drd TOR Occupancy; RFO hits from local IA. Unit: uncore_cha TOR Occupancy; RFO misses from local IO. Unit: uncore_cha TOR Occupancy; ITOM from local IO. Unit: uncore_cha event=0x36,umask=0x00ccc7ff01 unc_cha_tor_occupancy.ia_drd_pref unc_cha_tor_occupancy.ia_miss_rfo_pref_local event=0x35,umask=0x00ccd7ff01 TOR Inserts; LLCPrefCode misses from local IA. Unit: uncore_cha TOR Inserts : ItoMs issued by iA Cores that Missed LLC. Unit: uncore_cha TOR Inserts : WCiLF issued by iA Cores. Unit: uncore_cha event=0x35,umask=0x00C86FFF01 event=0x36,umask=0x00c8968a01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely. Unit: uncore_cha event=0x36,umask=0x00c86e8601 branch event=0x94 ic_fetch_stall.ic_stall_back_pressure l2_pf_miss_l2_hit_l3 amd_l3 Other L3 Miss Request Types. Unit: amd_l3 L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask. Unit: amd_l3 xi_ccx_sdp_req1.all_l3_miss_req_typs Retired Taken Branch Instructions event=0xc6 The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1 event=0,umask=0x0f event=0x2,umask=0x02 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply FLOPS The number of serializing Ops retired. SSE bottom-executing uOps retired Counts the number of loads dispatched to the LS unit. Unit Masks ADDed L1 DTLB Miss of a page of 32K size de_dis_dispatch_token_stalls0.alsq1_token_stall event=0xaf,umask=0x01 All L1 Data Cache Accesses All L2 Cache Accesses L2 Cache Misses from L2 HWPF L2 Cache Hits from L1 Instruction Cache Misses ic_fetch_miss_ratio L1 DTLB Misses The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB page event=0xd2 event=0xe,umask=0x01 event=0x59,umask=0x40 Software Prefetch Data Cache Fills by Data Source. Local L2 hit event=0xa9 event=0x90 ls_hw_pf_dc_fills.lcl_l2 This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events] l1_data_cache_fills_from_within_same_ccx Retired near returns (RET or RET Iw) ls_dmnd_fills_from_sys.far_cache Any data cache fills from cache of another CCX when the address was in a different NUMA node Software prefetch data cache fills from extension memory L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks) l2_pf_hit_l2.l2_burst l2_pf_miss_l2_hit_l3.l2_stream L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses) Op cache hits l3_xi_sampled_latency_requests.dram_near Retired microcoded instructions local_processor_read_data_beats_cs7 event=0x2df,umask=0x7ff event=0x5f,umask=0xbfe event=0x11f,umask=0xbff Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 1 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 6 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 2 local_socket_inf1_outbound_data_beats_ccm5 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 7 event=0x41f,umask=0xbff event=0xb9f,umask=0xf3e Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 2 Retired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in exception mask bits Retired scalar floating-point convert ops fp_ops_retired_by_type.vector_blend Retired MMX integer add Retired MMX integer ops of all types event=0xb,umask=0x30 sse_avx_ops_retired.sse_avx_all event=0xc,umask=0x08 fp_pack_ops_retired.fp256_shuffle packed_int_op_type.int128_mov Unit: uncore_umcpmc Number of memory clock cycles L1 DTLB misses with L2 DTLB hits for 4k pages L1 DTLB misses with L2 DTLB hits for 2M pages de_no_dispatch_per_slot.backend_stalls d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots) d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots) d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots) Fraction of dispatch slots used by fastpath ops that retired l2_cache_misses_from_l1_dc_miss l2_cache_hits_from_l1_ic_miss L2 cache hits from L2 cache hardware prefetcher L1 demand data cache fills from another CCX cache in the same NUMA node Remote socket inbound data to the CPU (e.g. read data) d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk) LS_BUFFER2_FULL LS_MICROARCHITECTURAL_LATE_CANCEL FR_RETIRED_FAR_CONTROL_TRANSFERS NB_PROBE_RESULT L1_CACHE_ACCESS_NOCP15 EVENT_70H EVENT_B8H EVENT_F3H EVENT_F9H JAVA_BYTECODE INSTR_MAIN_TLB_MISS_STALL PLE_CACHE_LINE_REQ_SKIPPED BR_MIS_PRED L2D_CACHE_WB EXC_IRQ EVENT_13AH EVENT_15AH EVENT_169H EVENT_1EDH EVENT_23FH EVENT_2C3H EVENT_2CEH EVENT_2D4H EVENT_2DEH EVENT_2E6H EVENT_315H EVENT_322H EVENT_333H EVENT_33AH EVENT_3CAH EVENT_3CEH EVENT_3E4H EVENT_3EDH STREX_FAIL_SPEC PC_WRITE_SPEC dn_rxreq_snp_stalled hnf_snp_sent_untrk sbsx_wr_req_trkr_occ_cnt_ovfl sbsx_txrsp_stall rnd_rdb_hybrid cxha_rdbbyp_occ cxla_tx_cxs_link_credit_backpressure clkdiv2_lrank_turnaround_activate MFSPR_INSTR_COMPLETED IU1_INSTR_COMPLETED L3_CACHE_MISSES L1_EXTERNAL_INTERVENTIONS PREFETCH_ENGINE_COLLISION_VS_LOAD BR_MARKED_INSTR_FINISH BRANCH_MISPRED SYSCALL_TRAP_INTR L2_LINEFILL_BUFFER CASTOUTS_RELEASED DVT1_DETECTED mmx-3dnow x87-reclass-microfaults dram-controller-queue-bypass probe-hit-dirty-with-memory-cancel ic-misses TSC ARMV7_CORTEX_A5 ARMV7_CORTEX_A8 BRANCH-MISSES-RETIRED offcore_rsp cmask %s, "pmcid": "0x%08x", "pid": "%d" "tid": "%d", "value": "0x%016jx"}
%s, "userdata": "0x%08x"}
v17 GenuineIntel-6-A[56] ( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD) Instructions Per Cycle (per Logical Processor) FP_Arith_Utilization Cor;Flops;HPC UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC) Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting Average per-core data fill bandwidth to the L3 cache [GB / sec] Giga Floating Point Operations Per Second C6_Pkg_Residency L2 cache lines in E state filling L2 Demand Data Read requests L2 fill requests that access L2 cache event=0xd2,period=20011,umask=0x4 mem_load_uops_l3_miss_retired.remote_hitm Offcore requests buffer cannot take more entries for this thread core This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation) Spec update: BDM76 Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Spec update: BDM76 event=0xc7,period=2000006,umask=0x15 fp_assist.simd_output Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details) event=0xc8,period=2000003,umask=0x40 event=0xcd,period=100007,umask=0x1,ldlat=0x20 Number of times a disallowed operation caused an RTM abort Number of times we entered an RTM region; does not count nested transactions cpl_cycles.ring0 event=0x88,period=200003,umask=0xff br_inst_exec.all_conditional This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches event=0x88,period=200003,umask=0x81 This event counts all (macro) branch instructions retired br_inst_retired.far_branch event=0xc4,period=100007,umask=0x40 br_misp_exec.nontaken_conditional Total execution stalls resource_stalls.any Cycles stalled due to no eligible RS entry available uops_dispatched_port.port_2 Cycles per thread when uops are executed in port 5 event=0xb1,cmask=3,period=2000003,umask=0x1 uops_executed_port.port_7_core Number of flags-merge uops being allocated. Such uops considered perf sensitive
added by GSR u-arch event=0x35,umask=0x1,filter_opc=0x19e llc_references.pcie_write This is an occupancy event that tracks the number of cores that are in C3. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu Load misses that miss the DTLB and hit the STLB (2M) dtlb_load_misses.walk_completed_4k dtlb_load_misses.walk_duration This event counts the number of DTLB flush attempts of the thread-specific entries offcore_response.all_pf_code_rd.supplier_none.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020004 offcore_response.demand_rfo.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000018000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C8000 offcore_response.pf_l2_code_rd.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020020 Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000090 offcore_response.all_pf_rfo.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000040 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000200 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000100 This event counts mispredicted return instructions retired (Precise event) This event counts the number of retirement slots used (Precise event) event=0x34,umask=0x11 L3 Lookup read request that access cache and found line in M-state. Unit: uncore_cbox event=0x34,umask=0x2f offcore_response.all_reads.llc_hit.hit_other_core_no_fwd offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00200 8Bytes event=0x22,period=200000,umask=0x40 event=0x2d,period=200000,umask=0x42 l2_reject_busq.self.any.s_state mem_load_retired.l2_hit simd_comp_inst_retired.packed_single event=0xb3,period=2000000,umask=0x20 simd_uop_type_exec.logical.ar SIMD packed shift micro-ops retired event=0x10,period=2000000,umask=0x1 event=0x87,period=2000000,umask=0x1 ld-op-st splits event=0x5,period=200000,umask=0xf event=0x5,period=200000,umask=0x92 event=0x7b,period=200000,umask=0x20 event=0x65,period=200000,umask=0xe0 Burst read bus transactions bus_trans_def.all_agents bus_trans_inval.all_agents event=0xc4,period=2000000,umask=0x0 br_inst_retired.pred_taken br_inst_type_retired.cond_taken div.s data_tlb_misses.dtlb_miss event=0x31,period=200003 Memory uop retired where cross core or cross module HITM occurred (Precise event capable) Supports address when precise (Must be precise) Load uops retired that missed L1 data cache (Precise event capable) Supports address when precise (Must be precise) offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_needed Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_needed event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000008 Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwd Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xc3,period=200003,umask=0x4 BACLEARs asserted for return branch Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.
This event counts differently than Intel processors based on Silvermont microarchitecture Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken (Must be precise) Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter cycles_div_busy.all machine_clears.disambiguation event=0xc3,period=200003,umask=0x8 Duration of D-side page-walks in cycles Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress Counts data reads generated by L1 or L2 prefetchers hit the L2 cache Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000800 event=0x8,period=200003,umask=0x8 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault event=0x8,period=200003,umask=0x4 Page walk completed due to an instruction fetch in a 1GB page tlb_flushes.stlb_any This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 offcore_response.all_rfo.l3_hit.hitm_other_core event=0xc6,period=2000003,umask=0x7 offcore_response.all_requests.l3_miss.any_response offcore_response.pf_l3_rfo.l3_miss.any_response Number of times an RTM execution started Counts the number of not taken branch instructions retired event=0x87,period=2000003,umask=0x4 Cycles at least 3 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads Number of DTLB page walker loads that hit in the L2 event=0xf2,period=100003,umask=0x4 l2_store_lock_rqsts.hit_m Retired load uops which data sources were HitM responses from shared LLC (Precise event) Retired load uops that miss the STLB. (Precise Event) Counts all demand & prefetch data reads that hit in the LLC offcore_response.demand_code_rd.llc_hit.any_response offcore_response.demand_data_rd.llc_hit.any_response Counts all demand data writes (RFOs) that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x18000 fp_comp_ops_exe.x87 Cycles DSB to MITE switches caused delay Counts cycles the IDQ is empty Counts demand code reads that miss the LLC and the data returned from dram Cycles weighted by number of requests pending in Coherency Tracker Number of requests allocated in Coherency Tracker. Unit: uncore_arb Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC. Unit: uncore_arb Counts the number of LLC evictions allocated A snoop misses in some processor core event=0x34,umask=0x20 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0090 Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response offcore_response.all_reads.llc_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0001 Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches Counts demand data reads that miss the LLC and the data returned from local dram offcore_response.pf_l2_data_rd.llc_miss.remote_dram Occupancy for all LLC misses that are addressed to remote memory. Unit: uncore_cbox freq_band1_cycles % unc_p_freq_ge_4000mhz_transitions Allocated L1D data cache lines in M state l2_l1d_wb_rqsts.hit_s This event counts retired load uops that hit in the last-level (L3) cache without snoops required br_misp_retired.near_call This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type event=0xa2,period=2000003,umask=0xe Counts the number of load micro-ops retired that hit in the L2 Supports address when precise (Precise event) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800403091 offcore_response.any_pf_l2.l2_hit_this_tile_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000070 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00040032f7 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00100032f7 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000088000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000022 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400004 offcore_response.demand_code_rd.l2_hit_near_tile event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000004 Counts demand cacheable data and L1 prefetch data reads that accounts for any response offcore_response.partial_reads.l2_hit_far_tile_e_f Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400040 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000040 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000081000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100403091 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000070 Counts any Read request that accounts for responses from MCDRAM (local and far) offcore_response.demand_data_rd.mcdram_far Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local Counts L2 code HW prefetches that accounts for data responses from DRAM Far Counts the number of branch instructions retired (Precise event) event=0x3,period=200003,umask=0x20 l1d.m_snoop_evict event=0x43,period=2000000,umask=0x1 l2_data_rqsts.demand.m_state l2_data_rqsts.demand.s_state event=0x24,period=200000,umask=0x2 l2_transactions.l1d_wb event=0x27,period=100000,umask=0x20 mem_inst_retired.latency_above_threshold_2048 event=0xcb,period=2000000,umask=0x1 Load instructions retired IO (Precise Event) Offcore data reads satisfied by a remote cache or remote DRAM Offcore requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x477 offcore_response.demand_data.any_cache_dram offcore_response.demand_data.remote_cache_hitm All offcore demand data reads Offcore demand code reads satisfied by the LLC and HIT in a sibling core offcore_response.demand_ifetch.llc_hit_other_core_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1804 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F02 Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core Offcore prefetch data requests satisfied by any cache or DRAM Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x730 Offcore prefetch data requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1830 Offcore prefetch data reads satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3810 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x840 Offcore prefetch RFO requests satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x170 offcore_response.prefetch.remote_cache fp_comp_ops_exe.mmx fp_comp_ops_exe.sse2_integer SIMD integer 64 bit packed multiply operations Offcore demand data requests satisfied by any DRAM offcore_response.demand_ifetch.remote_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2002 offcore_response.pf_rfo.any_llc_miss event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF820 Loads dispatched from the MOB False dependencies due to partial address aliasing Segment rename stall cycles event=0xc4,period=200000,umask=0x4 resource_stalls.rob_full event=0xb1,any=1,period=2000000,umask=0x8 uops_issued.fused Retired load instructions which data sources were HitM responses from shared L3 Supports address when precise (Precise event) Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0080001 offcore_response.demand_data_rd.l3_hit_s.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0080002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0088000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400048000 offcore_response.other.supplier_none.spl_hit event=0x32,period=2000003,umask=0x8 event=0xc6,period=100007,umask=0x1,frontend=0x1 cycle_activity.cycles_l3_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000040004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000002 All (macro) branch instructions retired Spec update: SKL091 Number of instructions retired. General Counter - architectural event Spec update: SKL091, SKL044 int_misc.clear_resteer_cycles event=0xc1,period=100003,umask=0x3f Bad;Branches;CodeGen;PGO Page walk completed due to a demand data load to a 2M/4M page Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts code reads generated by L2 prefetchers that miss L2 offcore_response.all_pf_rfo.llc_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0122 offcore_response.pf_l2_code_rd.llc_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400004 Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram offcore_requests.demand.read_data event=0xb0,period=100000,umask=0x4 event=0x60,period=2000000,umask=0x8 REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8ff offcore_response.any_rfo.all_local_dram_and_remote_cache_hit REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff80 REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT offcore_response.pf_ifetch.all_local_dram_and_remote_cache_hit REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM offcore_response.any_data.other_local_dram REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS offcore_response.demand_rfo.any_dram_and_remote_fwd event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf880 REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf870 Retired load instructions which data sources missed L3 but serviced from remote dram Supports address when precise (Precise event) offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd offcore_response.pf_l1d_and_sw.l3_hit.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_l3_rfo.l3_hit.hitm_other_core Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache offcore_response.all_rfo.l3_miss.remote_hit_forward offcore_response.demand_code_rd.l3_miss.remote_hit_forward offcore_response.demand_data_rd.l3_miss.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00002 offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss_or_no_fwd Power_License1_Utilization Write Pending Queue Occupancy. Unit: uncore_imc event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x01 unc_cha_core_snp.evict_gtone Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI unc_iio_comp_buf_inserts.cmpd.all_parts event=0xc2,ch_mask=0x0f,fc_mask=0x4,umask=0x03 PCIe Completion Buffer Inserts of completions with data: Part 0. Unit: uncore_iio Read request for 4 bytes made by the CPU to IIO Part1. Unit: uncore_iio event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x08 Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_read.part1 Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1. Unit: uncore_iio event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x08 unc_iio_txn_req_by_cpu.peer_write.part2 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus event=0xf,umask=0x4 uncore_m2m Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) event=0x2d,umask=0x1 Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and event=0x2 Valid data FLITs received from any slot. Unit: uncore_upi unc_upi_txl_bypassed OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD ocr.all_pf_data_rd.l3_hit_m.snoop_none ocr.all_pf_rfo.l3_hit.any_snoop OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0004 Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP ocr.demand_data_rd.l3_hit_m.snoop_miss Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_hit_f.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C8000 ocr.other.l3_hit_f.any_snoop ocr.other.l3_hit_f.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200400 ocr.pf_l1d_and_sw.l3_hit_f.hitm_other_core Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE ocr.pf_l2_data_rd.l3_hit_s.any_snoop Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_e.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080020 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040080 ocr.pf_l3_data_rd.l3_hit_s.snoop_miss Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE ocr.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_m.hit_other_core_fwd offcore_response.all_data_rd.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.all_pf_rfo.supplier_none.no_snoop_needed offcore_response.all_reads.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000207F7 offcore_response.all_reads.supplier_none.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.demand_code_rd.l3_hit_f.hit_other_core_fwd offcore_response.demand_code_rd.l3_hit_f.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE offcore_response.demand_code_rd.l3_hit_s.hit_other_core_no_fwd offcore_response.demand_code_rd.supplier_none.no_snoop_needed offcore_response.demand_data_rd.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS offcore_response.demand_data_rd.l3_hit_f.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_hit_f.hitm_other_core offcore_response.other.l3_hit_s.hitm_other_core offcore_response.other.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED offcore_response.pf_l2_data_rd.l3_hit_f.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400010 This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.pf_l2_rfo.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwd offcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_none offcore_response.pf_l3_rfo.supplier_none.no_snoop_needed ocr.all_data_rd.l3_miss.hit_other_core_no_fwd ocr.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000490 OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000120 OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD ocr.all_pf_rfo.l3_miss_local_dram.hitm_other_core ocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd ocr.all_reads.l3_miss.any_snoop OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS ocr.demand_code_rd.l3_miss_local_dram.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000001 ocr.demand_data_rd.l3_miss_remote_hop1_dram.any_snoop Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop ocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000020 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE ocr.pf_l3_data_rd.l3_miss_local_dram.no_snoop_needed ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_core Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.all_pf_data_rd.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP offcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.pf_l2_data_rd.l3_miss_local_dram.hitm_other_core offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.pf_l3_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed ocr.all_data_rd.supplier_none.hit_other_core_no_fwd OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_not_needed ocr.all_rfo.supplier_none.any_snoop ocr.demand_data_rd.any_response UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS Underfill read commands for Intel Optane DC persistent memory. Unit: uncore_imc Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory Tag Hit; Underfill Rd Hit from NearMem, Dirty Line event=0x51,period=100003,umask=0x1 Counts demand requests to L2 cache Counts retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event) Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events event=0x9c,period=1000003,umask=0x1 Counts the number of times HLE abort was triggered Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache event=0x54,period=100003,umask=0x40 ocr.demand_code_rd.dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000010 Counts taken conditional mispredicted branch instructions retired (Precise event) Core cycles the allocator was stalled due to recovery from earlier clear event for this thread event=0xcc,period=100003,umask=0x20 event=0xcc,period=100003,umask=0x40 Number of uops decoded out of instructions exclusively fetched by decoder 0 Demand Data Read transactions pending for off-core. Highly correlated Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle DSB;FetchBW Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode ocr.reads_to_core.l3_hit ocr.reads_to_core.snc_cache.hit_with_fwd Counts both cacheable and non-cacheable code reads to the core (cstate_core@c1\-residency@ / msr@tsc@) * 100 Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x700800002 Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM event=0x45,umask=0x04 unc_m_wpq_inserts.pch0 unc_m_act_count.all event=0x2,umask=0x1C event=0x35,umask=0xC001FF01 unc_cha_tor_inserts.ia_hit_drd TOR Inserts : RFOs issued by iA Cores that Hit the LLC. Unit: uncore_cha TOR Occupancy : All requests from iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss unc_cha_tor_inserts.ia_hit_crd_pref unc_cha_tor_inserts.ia_llcprefrfo event=0x35,umask=0xCD43FF04 unc_cha_tor_inserts.io_miss_itomcachenear unc_cha_tor_inserts.ia_miss_llcprefdata event=0x35,umask=0xCCD7FE01 unc_cha_tor_occupancy.io_miss_pcirdcur unc_iio_txn_req_of_cpu.cmpd.part0 event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x01 event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x04 event=0xd5,fc_mask=0x04,umask=0xff event=0x8,period=100003,umask=0x8 Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis Counts the number of store uops retired Supports address when precise (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0044 This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0040 Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache ocr.uc_rd.l3_hit.snoop_not_needed Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request ocr.hwpf_l2_data_rd.l3_miss_local Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000001 Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100000010000 topdown_bad_speculation.all topdown_bad_speculation.machine_clears topdown_be_bound.mem_scheduler event=0x74,period=1000003,umask=0x2 Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows (Precise event) uops_retired.x87 Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests unc_cha_tor_inserts.ia_drd_opt_pref TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts unc_cha_tor_occupancy.ia_miss_drd_opt Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP Clockticks of the power control unit (PCU) itlb_misses.pde_cache_miss Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page Counts the number of load ops retired that miss in the second Level TLB Supports address when precise (Precise event) Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST. Unit: cpu_core L2 cache hits per kilo instruction for all request types (including speculative). Unit: cpu_core Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses. Unit: cpu_core Average number of parallel requests to external memory. Accounts for all requests. Unit: cpu_core CPU_CLK_UNHALTED.CORE_P INST_RETIRED.ANY / BR_INST_RETIRED.CALL Instructions per Load. Unit: cpu_atom Instructions per Store. Unit: cpu_atom Cycle cost per LLC hit. Unit: cpu_atom MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM). Unit: cpu_atom Counts the number of store uops retired Supports address when precise (Precise event). Unit: cpu_atom event=0xd0,period=1000003,umask=0x5,ldlat=0x80 mem_uops_retired.load_latency_gt_16 Retired load instructions that split across a cacheline boundary Supports address when precise (Precise event). Unit: cpu_core Retired load instructions with L1 cache hits as data sources Supports address when precise (Precise event). Unit: cpu_core Counts the number of floating point operations retired that required microcode assist. Unit: cpu_atom Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt) (Precise event). Unit: cpu_atom event=0xb0,cmask=1,period=1000003,umask=0x1 Uops delivered to IDQ while MS is busy. Unit: cpu_core Mispredicted conditional branch instructions retired (Precise event). Unit: cpu_core Cycles total of 4 uops are executed on all ports and Reservation Station was not empty. Unit: cpu_core misc2_retired.lfence Increments whenever there is an update to the LBR array. Unit: cpu_core unc_m_cas_count_wr Store misses in all TLB levels causes a page walk that completes. (All page sizes). Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C000001 arith.idiv_active event=0x5,umask=0x00000000ff Write request of 4 bytes made by IIO Part0 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000002 Data requested of the CPU : Card writing to another Card (same or different stack). Unit: uncore_iio Read requests from a unit on this socket. Unit: uncore_cha event=0x36,umask=0x00c816fe01 event=0x35,umask=0x00c8178a01 unc_upi_rxl_flits.prothdr event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000001 event=0xc0,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000001 event=0xc0,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000001 event=0xc1,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000001 event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000080 event=0x54,umask=0x0000000002 event=0x35,umask=0x00C001FFff event=0x35,umask=0x00c001fe01 TOR Inserts; Misses from local IO. Unit: uncore_cha TOR Inserts; DRd Opt hits from local IA. Unit: uncore_cha event=0x36,umask=0x00c001ff08 event=0x36,umask=0x00C001FFff unc_cha_tor_occupancy.ipq unc_cha_tor_occupancy.ia_miss_rfo_pref unc_cha_tor_occupancy.ia_crd_pref TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC. Unit: uncore_cha event=0x36,umask=0x00c8f3ff04 unc_cha_tor_inserts.ia_hit_llcprefdata event=0x36,umask=0x00ccd7fd01 TOR Occupancy; LLCPrefCode misses from local IA. Unit: uncore_cha event=0x35,umask=0x00C8978A01 unc_cha_tor_inserts.ia_miss_crd_pref_remote unc_cha_tor_inserts.ia_wbmtoi event=0x35,umask=0x00CC23FF04 TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0x00c86f0601 TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC. Unit: uncore_cha TOR Occupancy : PMM Access. Unit: uncore_cha The number of instruction fetches that miss in both the L1 and L2 TLBs l2_request_g1.cacheable_ic_read event=0x64,umask=0x10 All L3 Request Types. Unit: amd_l3 The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts ex_div_count fp_ret_sse_avx_ops.dp_mult_add_flops event=0x4,umask=0x08 ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss event=0x46,umask=0x02 event=0xaf,umask=0x02 l1_dtlb_misses 3e-5MiB event=0x94,umask=0x04 The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB page event=0x43,umask=0x08 ls_sw_pf_dc_fill.ls_mabresp_lcl_cache ls_sw_pf_dc_fill.ls_mabresp_lcl_l2 Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote) ls_hw_pf_dc_fill.ls_mabresp_lcl_l2 Instruction Cache Refills from L2. The number of 64 byte instruction cache line was fulfilled from the L2 cache xi_ccx_sdp_req1 Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entry ls_dmnd_fills_from_sys.lcl_l2 Software Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination register event=0x64,umask=0xf0 d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses) event=0x1c9 Demand data cache fills from either DRAM or MMIO in the same NUMA node Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node ls_sw_pf_dc_fills.far_cache Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2 Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines into L2 cache when each access is at a constant distance from the previous) event=0xad,umask=0x01 l3_xi_sampled_latency_requests.dram_far event=0xad,umask=0x08 local_processor_read_data_beats_cs4 local_processor_read_data_beats_cs6 Read data beats (64 bytes) for local processor at Coherent Station (CS) 11 event=0x9f,umask=0xbfe Read data beats (64 bytes) for remote processor at Coherent Station (CS) 5 event=0x1f,umask=0xbff Write data beats (64 bytes) for remote processor at Coherent Station (CS) 5 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 10 event=0x8df,umask=0xbfe Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 4 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 3 event=0x4df,umask=0xbff fp_ret_x87_fp_ops.add_sub_ops Retired x87 floating-point divide and square root ops sse_avx_ops_retired.mmx_mul event=0xb,umask=0x09 Retired MMX integer shift ops Retired MMX integer logical ops event=0xc,umask=0x01 fp_pack_ops_retired.fp128_all packed_int_op_type.int128_sha Retired 128-bit packed integer compare ops event=0xd,umask=0x0e uncore_umcpmc Number of ACTIVATE commands sent for writes umc_data_slot_clks.all L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes Instruction fetches that hit in the L1 ITLB for 2M pages de_dis_ops_from_decoder.any_fp_dispatch Number of cycles dispatch is stalled for integer physical register file tokens Number of cycles dispatch is stalled for taken branch buffer tokens Number of cycles dispatch is stalled for floating-point scheduler tokens Number of cycles dispatch is stalled for integer scheduler queue 3 tokens All L1 data cache fills umc_mem_write_bandwidth umc_mem_bandwidth uncore_hisi_ddrc.flux_wcmd INSTR_RETIRED_ANY LS_RETIRED_CPUID_INSTRUCTIONS IC_RETURN_STACK_HIT FR_RETIRED_FPU_INSTRUCTIONS FR_NUMBER_OF_BREAKPOINTS_FOR_DR0 NB_MEMORY_CONTROLLER_BYPASS_SATURATION CID_WRITE CLOCK_CYCLES L2_STORE_MERGED MEM_REPLAY_EVT EVENT_00H EVENT_09H EVENT_31H EVENT_7CH EVENT_95H EVENT_AAH EVENT_B2H EVENT_B4H EVENT_FCH DATA_ENGINE_CLOCK_ENABLED EVENT_11EH EVENT_128H EVENT_14BH EVENT_15EH EVENT_180H EVENT_194H EVENT_1A3H EVENT_1A6H EVENT_1B0H EVENT_1CEH EVENT_1ECH EVENT_1F2H EVENT_213H EVENT_21FH EVENT_221H EVENT_247H EVENT_276H EVENT_287H EVENT_29EH EVENT_2A0H EVENT_2B8H EVENT_2CCH EVENT_2D1H EVENT_2DFH EVENT_2F1H EVENT_30FH EVENT_381H EVENT_396H EVENT_39BH EVENT_3A8H EVENT_3D3H EVENT_3EEH EVENT_3EFH L1D_TLB_REFILL_LD UNALIGNED_LD_SPEC BUS_ACCESS_NOT_SHARED hni_rdt_rd_alloc sbsx_txdat_flitv cxha_chirsp_up_stall L1_DATA_SNOOP_HIT_CASTOUT_QUEUE TAKEN_BRANCHES_PROCESSED SS_SM_INSTR_PIECES SNOOP_MODIFIED BUS_TAS_FOR_READS ADDRESS_COLLISION EXT_INPUT_INTR_TAKEN LV2_VS L2_CACHE_DATA_ALLOCATIONS FPU_RESULT_STALL_CYCLES usr rdszbyte interrupts INTEL_ATOM ARMV7_CORTEX_A9 THREAD ps->ps_state != PL_STATE_ERROR br_misp_retired.all_branches v10 GenuineIntel-6-35 GenuineIntel-6-1F GenuineIntel-6-96 Branches;Fed;FetchBW IpCall BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN IpArith Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate) Flops;FpScalar;InsType IpArith_AVX256 Mem;MemoryBound;MemoryBW L2HPKI_Load Fraction of cycles spent in the Operating System (OS) Kernel mode MEM_Parallel_Reads Socket_CLKS l1d.replacement event=0x27,period=200003,umask=0x50 L2 cache lines in I state filling L2 event=0x24,period=200003,umask=0x24 Core-originated cacheable demand requests that refer to L3 This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event Supports address when precise. Spec update: BDE70, BDM100 event=0xd3,period=100007,umask=0x4 Retired load uops that miss the STLB. (Precise Event - PEBS) Supports address when precise (Precise event) fp_arith_inst_retired.128b_packed_single event=0xc7,period=2000003,umask=0x1 fp_assist.simd_input event=0x79,cmask=1,period=2000003,umask=0x4 event=0x9c,cmask=2,period=2000003,umask=0x1 Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xc8,period=2000003,umask=0x20 event=0xcd,period=503,umask=0x1,ldlat=0x100 Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts) Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded This event counts not taken branch instructions retired event=0x3c,period=2000003 Execution stalls while L1 cache miss demand load is outstanding inst_retired.x87 event=0xc3,period=2000003,umask=0x1 Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes Number of integer Move Elimination candidate uops that were not eliminated event=0x5e,cmask=1,edge=1,inv=1,period=200003,umask=0x1 event=0xb1,cmask=2,period=2000003,umask=0x2 event=0xa1,any=1,period=2000003,umask=0x10 Cycles per core when uops are exectuted in port 6 uops_issued.flags_merge event=0xe,period=2000003,umask=0x20 event=0x35,umask=0x1,filter_opc=0x180,filter_tid=0x3e unc_c_tor_occupancy.llc_data_read unc_h_requests.writes_local write requests to remote home agent. Unit: uncore_ha read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc event=0x2,umask=0x8 This is an occupancy event that tracks the number of cores that are in C6. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events . Unit: uncore_pcu itlb_misses.walk_completed_4k Retired load uops misses in L1 cache as data sources Supports address when precise (Precise event) This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) offcore_response.all_pf_code_rd.supplier_none.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0090 offcore_response.all_rfo.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0008 offcore_response.demand_code_rd.l3_hit.snoop_not_needed offcore_response.other.l3_hit.snoop_not_needed offcore_response.pf_l2_data_rd.supplier_none.snoop_not_needed offcore_response.pf_l2_rfo.l3_hit.snoop_hitm offcore_response.pf_l2_rfo.supplier_none.snoop_hitm offcore_response.pf_l2_rfo.supplier_none.snoop_miss Counts prefetch (that bring data to LLC only) code reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0080 offcore_response.pf_l3_data_rd.supplier_none.snoop_hitm offcore_response.pf_l3_rfo.l3_hit.snoop_none Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000240 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000001 offcore_response.other.l3_miss_local_dram.snoop_none offcore_response.other.l3_miss_local_dram.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020040 offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hitm Actually retired uops (Precise event) event=0x80,umask=0x01 Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case offcore_response.all_reads.llc_miss.remote_dram Modified cache lines evicted from the L1 data cache Modified cache lines allocated in the L1 data cache event=0x23,period=200000,umask=0x40 event=0x29,period=200000,umask=0x4f l2_m_lines_out.self.any Rejected L2 cache requests event=0x30,period=200000,umask=0x71 l2_rqsts.self.any.m_state l2_rqsts.self.demand.m_state mem_load_retired.l2_miss event=0xcd,period=100000,umask=0x0 simd_inst_retired.scalar_single SIMD saturated arithmetic micro-ops retired simd_uops_exec.ar SIMD packed multiply micro-ops executed event=0x87,period=2000000,umask=0x2 event=0x5,period=200000,umask=0x8c prefetch.hw_prefetch L1 hardware prefetch request event=0x62,period=200000,umask=0x20 bus_request_outstanding.self event=0x70,period=200000,umask=0xe0 bus_trans_brd.all_agents bus_trans_burst.self bus_trans_io.self Partial write bus transaction bus_trans_rfo.all_agents eist_trans segment_reg_loads.any br_inst_retired.mispred_not_taken All indirect branches that are not calls event=0x89,period=200000,umask=0x11 Mispredicted ind branches that are not calls event=0x3,period=200000,umask=0xff reissue.overlap_store event=0x2,period=200000,umask=0x83 Cycles no micro-ops retired data_tlb_misses.dtlb_miss_ld Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy Counts memory requests originating from the core that miss in the L2 cache Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400003010 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000048000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000004 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400004000 offcore_response.pf_l1_data_rd.l2_hit Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0x80,period=200003,umask=0x1 event=0xc4,period=200003,umask=0xf9 Retired conditional branch instructions that were taken (Precise event capable) (Must be precise) event=0xc5,period=200003 event=0xca,period=200003,umask=0x2 Unfilled issue slots per cycle because of a full resource in the backend event=0x3,period=200003,umask=0x4 Loads blocked due to store forward restriction (Precise event capable) (Must be precise) ld_blocks.utlb_miss Loads blocked because address in not in the UTLB (Precise event capable) (Must be precise) Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000011000 event=0x49,period=200003,umask=0x10 Page walks outstanding due to walking the EPT every cycle Counts all L2 HW prefetcher requests that missed L2 offcore_response.all_data_rd.l3_hit.hitm_other_core Number of instructions retired. General Counter - architectural event Spec update: HSD11, HSD140 L3 Lookup write request that access cache and found line in I-state Completed page walks in any TLB of any page size due to demand load misses Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) Completed page walks due to misses in ITLB 4K page entries Number of DTLB page walker hits in the L2 Number of DTLB page walker loads that hit in the L3 Spec update: HSD25 Counts the number of Extended Page Table walks from the DTLB that hit in memory Counts the number of Extended Page Table walks from the ITLB that hit in the L2 Counts all demand & prefetch code reads that hit in the LLC offcore_response.all_data_rd.llc_hit.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0001 fp_comp_ops_exe.sse_scalar_double Number of transitions from SSE to AVX-256 when penalty applicable Cycles Allocation is stalled due to Resource Related reason Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC A snoop invalidates a modified line in some processor core. Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to LLC eviction LLC lookup request that access cache and found line in E-state event=0x34,umask=0x04 unc_cbo_cache_lookup.es Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size Counts all prefetch data reads that hit the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc003f7 Counts all demand code reads that miss the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67fc00010 LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode.code. Unit: uncore_cbox event=0x35,umask=0x3,filter_opc=0x19c event=0x35,umask=0x1,filter_opc=0x1c8 Counts the number of cycles that the uncore was running at a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu event=0xc,filter_band1=20 unc_p_freq_ge_4000mhz_cycles event=0x27,period=200003,umask=0x4 All retired load uops (Precise event) event=0x14,cmask=1,edge=1,period=100003,umask=0x1 cycle_activity.cycles_no_dispatch Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400044 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000403091 Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080070 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x10004032f7 offcore_response.any_read.l2_hit_this_tile_e Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000004 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080100 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000100 Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state offcore_response.uc_code_reads.l2_hit_far_tile_e_f Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800001 Counts Demand cacheable data writes that accounts for data responses from DRAM Far Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far offcore_response.partial_reads.mcdram offcore_response.partial_reads.mcdram_far Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800020 Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts Software Prefetches that accounts for data responses from MCDRAM Local offcore_response.uc_code_reads.ddr_near event=0xcd,period=2000003,umask=0x1 Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page Counts the total number of core cycles when no micro-ops are allocated for any reason mcdram bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk event=0x2,umask=0x01 L1D cache lines replaced in M state event=0x40,period=2000000,umask=0x2 l2_data_rqsts.prefetch.mesi l2_rqsts.prefetches L2 RFO requests event=0xf0,period=200000,umask=0x20 event=0x27,period=100000,umask=0x80 L2 demand lock RFOs in M state l2_write.rfo.mesi event=0xb,period=200,umask=0x10,ldlat=0x200 Offcore data reads satisfied by any cache or DRAM offcore_response.any_data.local_cache Offcore data reads that HITM in a remote cache Offcore RFO requests satisfied by the LLC Offcore RFO requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F08 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1077 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x733 offcore_response.data_in.remote_cache_hitm Offcore demand data reads satisfied by the LLC or local DRAM offcore_response.demand_ifetch.remote_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x402 offcore_response.demand_rfo.remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1080 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF30 Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit Offcore prefetch data reads that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1840 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3840 offcore_response.pf_rfo.any_location offcore_response.pf_rfo.llc_hit_other_core_hitm X87 Floating point assists (Precise Event) event=0xf7,period=20000,umask=0x4 X87 Floating poiint assists for invalid input value (Precise Event) SSE and SSE2 FP Uops event=0x10,period=2000000,umask=0x20 simd_int_128.packed_shift simd_int_64.packed_mpy Offcore data reads satisfied by the local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF844 Offcore RFO requests that missed the LLC offcore_response.pf_data_rd.any_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF840 Offcore prefetch RFO requests that missed the LLC Offcore prefetch requests satisfied by a remote DRAM load_dispatch.rs_delayed sb_drain.any Conditional branch instructions executed event=0x18,period=2000000,umask=0x1 event=0x4c,period=200000,umask=0x1 event=0xa8,cmask=1,period=2000000,umask=0x1 rat_stalls.flags event=0xd2,period=2000000,umask=0x4 Stack pointer instructions decoded Uops decoded by Microcode Sequencer event=0xb1,any=1,cmask=1,period=2000000,umask=0x3f Uops executed on port 0 Uops executed on port 1 DTLB first level misses but second level hit event=0x49,period=200000,umask=0x2 Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type Counts the number of L2 cache lines filling the L2. Counting does not cover rejects mem_inst_retired.stlb_miss_loads Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C0004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C0004 offcore_response.demand_code_rd.l3_hit_m.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400004 offcore_response.demand_data_rd.l3_hit_e.snoop_hit_no_fwd offcore_response.demand_data_rd.l3_hit_s.snoop_hitm offcore_response.demand_rfo.l3_hit_m.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200408000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40028000 Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired event=0xc6,period=100007,umask=0x1,frontend=0x11 Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event) Execution stalls while L3 cache miss demand load is outstanding event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020002 rtm_retired.aborted_timer Number of times we entered an RTM region. Does not count nested transactions This event counts far branch instructions retired Spec update: SKL091 (Precise event) event=0x3c,period=25003,umask=0x2 Core crystal clock cycles when this thread is unhalted and the other thread is halted Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load This event counts cycles during which the microcode scoreboard stalls happen Number of macro-fused uops retired. (non precise) event=0x49,cmask=1,period=100003,umask=0x10 Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake This event counts the number of load ops retired that got data from the other core or from the other module (Precise event) Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response Countsof demand RFO requests to write to partial cache lines that miss L2 Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) JCC counts the number of mispredicted conditional branches (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event) Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) (Precise event) This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event) Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.pf_llc_rfo.llc_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400090 REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM event=0x60,cmask=1,period=2000000,umask=0x8 REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT offcore_response.data_ifetch.all_local_dram_and_remote_cache_hit REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM offcore_response.demand_rfo.other_local_dram REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD offcore_response.prefetch.any_dram_and_remote_fwd event=0x4f,period=2000000,umask=0x10 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2777 offcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwd offcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwd OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 offcore_response.all_data_rd.l3_miss.any_snoop offcore_response.all_data_rd.l3_miss.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00491 offcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000080 Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache event=0x28,period=200003,umask=0x18 1000000000 * ( cha@event\=0x36\,umask\=0x21\,config\=0x40433@ / cha@event\=0x35\,umask\=0x21\,config\=0x40433@ ) / ( cha_0@event\=0x0@ / duration_time ) Read Pending Queue Allocations. Unit: uncore_imc event=0x50,umask=0x04 unc_upi_txl_flits.all_data unc_iio_data_req_of_cpu.mem_read.part0 PCI Express bandwidth writing at IIO, part 2. Unit: uncore_iio Core Cross Snoops Issued; Multiple Core Requests. Unit: uncore_cha unc_cha_dir_update.ha unc_cha_fast_asserted.horz Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data) RspSFwd Snoop Responses Received. Unit: uncore_cha Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x08 Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x02 Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x08 event=0x22,umask=0x2 unc_m2m_direct2upi_not_taken_dirstate unc_m2m_directory_lookup.state_i event=0x2e,umask=0x20 unc_m2m_directory_update.any unc_m2m_prefcam_demand_promotions Prefecth requests that got turn into a demand request. Unit: uncore_m2m event=0x9 unc_upi_rxl_flits.all_null mem_load_retired.local_pmm ocr.all_data_rd.l3_hit_f.no_snoop_needed ocr.all_data_rd.l3_hit_f.snoop_miss OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100491 OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0490 OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040120 ocr.all_reads.l3_hit.hit_other_core_no_fwd ocr.all_reads.l3_hit_m.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100122 ocr.demand_code_rd.l3_hit_s.no_snoop_needed ocr.demand_data_rd.l3_hit_m.any_snoop ocr.demand_rfo.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100002 ocr.pf_l1d_and_sw.l3_hit.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100400 ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwd Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP ocr.pf_l2_data_rd.l3_hit_e.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040010 ocr.pf_l2_data_rd.l3_hit_m.snoop_none Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP ocr.pf_l2_rfo.l3_hit_s.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100020 ocr.pf_l2_rfo.l3_hit_s.snoop_none ocr.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP ocr.pf_l3_data_rd.l3_hit_m.snoop_miss ocr.pf_l3_rfo.l3_hit.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080100 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP offcore_response.all_data_rd.l3_hit_s.snoop_miss This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS offcore_response.all_pf_rfo.pmm_hit_local_pmm.any_snoop This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE offcore_response.all_reads.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804007F7 offcore_response.all_rfo.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.demand_code_rd.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD offcore_response.other.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.pf_l2_data_rd.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020010 offcore_response.pf_l2_rfo.l3_hit_e.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_hit_e.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020100 ocr.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd ocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000490 ocr.all_pf_rfo.l3_miss.snoop_miss OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000120 ocr.all_pf_rfo.l3_miss_local_dram.snoop_miss OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B8007F7 OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000122 Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000001 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM ocr.pf_l1d_and_sw.l3_miss_local_dram.any_snoop Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000400 ocr.pf_l2_rfo.l3_miss.snoop_miss ocr.pf_l2_rfo.l3_miss.snoop_none ocr.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd offcore_response.all_reads.l3_miss.remote_hit_forward This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_none offcore_response.other.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.pf_l1d_and_sw.l3_miss.snoop_miss This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.pf_l2_rfo.l3_miss.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwd ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_none ocr.all_rfo.supplier_none.no_snoop_needed ocr.pf_l2_data_rd.supplier_none.snoop_none ocr.pf_l2_rfo.supplier_none.no_snoop_needed ocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_needed ocr.pf_l3_rfo.supplier_none.hit_other_core_fwd Tag Check; Clean Counts all retired load instructions. This event accounts for SW prefetch instructions for loads Supports address when precise (Precise event) ocr.demand_data_rd.l3_hit.snoop_hit_no_fwd Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified Cycles where at least 1 outstanding data read request is pending event=0xc7,period=100003,umask=0x8 event=0x80,period=500009,umask=0x4 C10_Pkg_Residency Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request event=0xc4,period=400009,umask=0x11 event=0xa3,cmask=1,period=1000003,umask=0x1 TMA slots where no uops were being issued due to lack of back-end resources Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request mem_load_l3_hit_retired.xsnp_no_fwd Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event) Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data ocr.demand_rfo.l3_hit ocr.streaming_wr.l3_miss_local Line not found snoop reply HitM snoop reply with data, line kept in Shared state core_snoop_response.s_hit_fse ocr.demand_data_rd.snc_pmm Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000477 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x730000477 PMM Commands : Writes. Unit: uncore_imc event=0x35,umask=0xC817FE01 TOR Inserts; DRd Pref misses from local IA. Unit: uncore_cha TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_ddr event=0x35,umask=0xC8170601 Data requested by the CPU : Core reporting completion of Card read from Core DRAM. Unit: uncore_iio event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x04 unc_iio_txn_req_of_cpu.mem_write.part7 event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x04 event=0xc2,ch_mask=0x04,fc_mask=0x04,umask=0x03 event=0xc2,ch_mask=0x08,fc_mask=0x04,umask=0x03 unc_iio_comp_buf_inserts.cmpd.part6 PCIe Completion Buffer Occupancy of completions with data : Part 0. Unit: uncore_iio : All Inserts Inbound (p2p + faf + cset). Unit: uncore_irp Multi-socket cacheline Directory Lookups : Found in I state. Unit: uncore_m2m M2M Reads Issued to iMC : PMM - All Channels. Unit: uncore_m2m Valid Flits Received : All Non Data. Unit: uncore_upi Valid Flits Sent : All Non Data. Unit: uncore_upi Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims) event=0x34,period=200003,umask=0x8 ocr.all_code_rd.l3_hit.snoop_hit_no_fwd ocr.all_code_rd.l3_hit.snoop_hit_with_fwd Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002003C0000 ocr.all_code_rd.l3_miss ocr.demand_data_and_l1pf_rd.l3_miss Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) Counts the total number of BTCLEARS Counts the number of unhalted reference clock cycles at TSC frequency This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls) TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 event=0x49,period=200003,umask=0x8 Counts the number of page walks completed due to instruction fetch misses to any page size ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED ) Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Unit: cpu_atom Instructions Per Cycle. Unit: cpu_atom CPU_CLK_UNHALTED.CORE:k / CPU_CLK_UNHALTED.CORE Average CPU Utilization. Unit: cpu_atom mem_uops_retired.load_latency_gt_128 event=0xd0,period=1000003,umask=0x5,ldlat=0x40 Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Unit: cpu_core Number of PREFETCHT1 or PREFETCHT2 instructions executed. Unit: cpu_core Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core event=0x79,cmask=1,period=2000003,umask=0x20 event=0x47,cmask=2,period=1000003,umask=0x2 event=0xcd,period=1000003,umask=0x2 Counts demand data reads that have any type of response. Unit: cpu_atom Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU. Unit: cpu_atom event=0xc3,period=1000003,umask=0x80 Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls. Unit: cpu_atom event=0x1c Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM. Unit: uncore_imc Cycles when at least one PMH is busy with a page walk for a store. Unit: cpu_core Number of page walks outstanding for an outstanding code request in the PMH each cycle. Unit: cpu_core L2_LINES_OUT.NON_SILENT Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss) FP_ARITH_DISPATCHED.PORT_5 fp_arith_inst_retired2.512b_packed_half Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708000002 ARITH.IDIV_ACTIVE Cycles with retired uop(s) UOPS_RETIRED.MS event=0x5,umask=0x00000000D0 Data requested of the CPU : Card writing to DRAM. Unit: uncore_iio event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000002 event=0x35,umask=0x00c8178601 TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha event=0x2,umask=0x0000000002 event=0x4,umask=0x000000000f event=0x5,umask=0x000000000f RxQ Flit Buffer Allocations : Slot 2. Unit: uncore_upi Tx Flit Buffer Bypassed. Unit: uncore_upi event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000080 event=0x58,umask=0x0000000002 event=0x58,umask=0x0000000008 event=0x55,umask=0x0000000002 unc_cha_tor_inserts.mmcfg TOR Inserts : Just Local Targets. Unit: uncore_cha event=0x35,umask=0x00c887fd01 TOR Inserts; RFO pref from local IA. Unit: uncore_cha TOR Inserts; DRd Pref from local IA. Unit: uncore_cha event=0x36,umask=0x0000000020 unc_cha_tor_occupancy.ia_hit_crd_pref event=0x36,umask=0x00c807ff01 TOR Occupancy; LLCPrefRFO from local IA. Unit: uncore_cha TOR Occupancy; RdCur and FsRdCur hits from local IO. Unit: uncore_cha TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely. Unit: uncore_cha TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha event=0x36,umask=0x00c8978a01 TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha TOR Occupancy : CLFlushes issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_wcil unc_cha_tor_occupancy.ia_miss_local_wcil_pmm event=0x36,umask=0x00c86f0a01 TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC. Unit: uncore_cha event=0x60,umask=0x10 All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable l2_wcb_req.cl_zero event=0xc1 Retired Near Returns The number of near return instructions (RET or RET Iw) retired remote_outbound_data_controller_0 event=0x807,umask=0x02 dram_channel_data_controller_0 event=0x41,umask=0x08 LS MAB allocates by type - loads event=0x45,umask=0x20 ic_oc_mode_switch.ic_oc_mode_switch all_l2_cache_hits L3 Misses (includes Chg2X). Unit: amd_l3 d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss) bp_l1_tlb_fetch_hit.if2m event=0x94,umask=0x01 Total number uOps assigned to pipe 1 fp_disp_faults.x87_fill_fault Number of interrupts taken Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit Count of dispatched Ops from OpCache The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk to 4K page Instruction Cache Miss. Counts various IC tag related hit and miss events event=0x18e,umask=0x07 Op Cache Hit. Counts Op Cache micro-tag hit/miss events Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB event=0x47,umask=0x01 Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 3 available de_dis_dispatch_token_stalls2.int_sch1_token_stall event=0x44,umask=0x14 Demand data cache fills from all types of data sources Any data cache fills from all types of data sources L2 cache requests: prefetch directly into L2 event=0x70,umask=0x10 l2_pf_miss_l2_hit_l3.l2_burst L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous) L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of all types l3_xi_sampled_latency_requests.ext_far Retired CLFLUSH instructions Cycles with no retire because thread arbitration did not select the thread Read data beats (64 bytes) for local processor at Coherent Station (CS) 2 Read data beats (64 bytes) for local processor at Coherent Station (CS) 8 local_processor_write_data_beats_cs1 event=0x5f,umask=0x7ff remote_processor_read_data_beats_cs5 event=0x8df,umask=0xbff local_socket_inf0_inbound_data_beats_ccm3 event=0x59e,umask=0x7fe Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 3 local_socket_inf1_inbound_data_beats_ccm4 event=0x51e,umask=0x7ff Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 0 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 0 event=0x49e,umask=0xbff remote_socket_inf0_outbound_data_beats_ccm3 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 2 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 5 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 7 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 1 event=0xc1f,umask=0xf3e Retired x87 floating-point multiply ops Retired SSE and AVX floating-point multiply-accumulate ops (each operation is counted as 2 ops) Retired floating-point ops of all widths fp_ops_retired_by_type.scalar_sqrt Retired vector floating-point divide ops event=0xa,umask=0xd0 event=0xa,umask=0xff Retired MMX integer compare ops Retired SSE and AVX integer ops of other types fp_pack_ops_retired.fp128_add event=0xc,umask=0x03 fp_pack_ops_retired.fp256_all event=0xd,umask=0x08 event=0xd,umask=0x20 Retired 256-bit packed integer multiply ops Number of ACTIVATE commands sent umc_pchg_cmd.rd Number of clocks used by the data bus Cycles when the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough Ops fetched from op cache and dispatched Ops dispatched from any source Total dispatch slots (upto 6 instructions can be dispatched in each cycle) l2_cache_misses_from_l1_ic_miss (umc_cas_cmd.wr * 64) / 1e6 / duration_time umc_precharge_cmd_rate DC_MISALIGNED_DATA_REFERENCE DC_MICROARCHITECTURAL_LATE_CANCEL BU_FILL_INTO_L2 NB_HT_BUS1_BANDWIDTH L2_ACCESS PRED_BRANCH_EXEC_TAKEN EVENT_0AH EVENT_18H EVENT_59H EVENT_87H EVENT_A4H EVENT_C6H PREDICTABLE_FUNCTION_RETURN LOAD_STORE_PIPE DMB_STALL EVENT_118H EVENT_132H EVENT_13CH EVENT_13DH EVENT_157H EVENT_158H EVENT_16AH EVENT_17DH EVENT_18BH EVENT_18CH EVENT_190H EVENT_197H EVENT_19DH EVENT_1A5H EVENT_1A7H EVENT_1BBH EVENT_1CFH EVENT_1F0H EVENT_226H EVENT_242H EVENT_249H EVENT_2DBH EVENT_2E3H EVENT_2F7H EVENT_303H EVENT_336H EVENT_33EH EVENT_388H EVENT_393H EVENT_3A2H EVENT_3BCH EVENT_3E1H EVENT_3E6H L1D_CACHE_WB_VICTIM DSB_SPEC RC_LD_SPEC L2D_TLB dn_rxreq_pici_dvmop hni_arvalid_no_arready sbsx_wvalid_no_wready rnd_rrt_occ_ovfl rni_s0_rdata_beats cxla_tx_cxs_link1 THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES L1_DATA_STORE_MISS L1_DATA_CACHE_OP_HIT CYCLES_NO_INSTR_DISPATCHED TOTAL_TRANSLATED DATA_MMU_MISS STASH_HITS STASH_REQUESTS_L1 SNOOP_THROTTLING_TURNED_ON CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL dirty-l2-victim low-op-pos-2 postwrszdword rdmodwr branch-mispredicts USER INTEL_SANDYBRIDGE INTEL_HASWELL_XEON UNKNOWN DISABLED ALLOCATED /usr/src/lib/libpmc/pmclog.c UNHALTED-CORE-CYCLES l3_request_g1.caching_l3_cache_accesses RESOURCE_STALLS_ANY inst_retired.any event {"type": "pmcattach" %s, "pmcid": "0x%08x", "event": "0x%08x", "flags": "0x%08x", "rate": "%jd"}
GenuineIntel-6-25 4 * CPU_CLK_UNHALTED.THREAD FLOPc Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles) Mem;MemoryBW Average Frequency Utilization relative nominal frequency This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects l2_lines_in.i event=0x24,period=200003,umask=0xf8 RFO requests to L2 cache event=0x24,period=200003,umask=0x44 L2 or L3 HW prefetches that access L2 cache l2_trans.code_rd RFO requests that access L2 cache event=0xd1,period=100007,umask=0x20 offcore_requests_outstanding.cycles_with_data_rd event=0x60,cmask=1,period=2000003,umask=0x1 Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element fp_arith_inst_retired.single idq.ms_cycles This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3 event=0x54,period=2000003,umask=0x1 Number of times a TSX Abort was triggered due to release/commit but data and address mismatch Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer Cycles when L1 and L2 are locked due to UC or split lock Speculative and retired indirect branches excluding calls and returns Taken speculative and retired macro-conditional branches Return instructions retired. (Precise Event - PEBS) (Precise event) Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise) This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.
Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case cycle_activity.cycles_l1d_miss Execution stalls while L2 cache miss demand load is outstanding Instructions retired from execution Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault event=0xcc,period=2000003,umask=0x20 Cycles per thread when uops are executed in port 0 event=0xa1,period=2000003,umask=0x8 uops_dispatched_port.port_5 event=0xb1,cmask=1,inv=1,period=2000003,umask=0x1 uops_retired.all event=0x37,umask=0x1 M line evictions from LLC (writebacks to memory). Unit: uncore_cbox event=0x35,umask=0x3,filter_opc=0x187 event=0x35,umask=0x1,filter_opc=0x1c8,filter_tid=0x3e unc_h_snoop_resp.rspcnflct (UNC_M_POWER_CHANNEL_PPD / UNC_M_DCLOCKTICKS) * 100. event=0x5 dtlb_load_misses.stlb_hit dtlb_load_misses.stlb_hit_4k event=0x8,period=2000003,umask=0x4 Store operations that miss the first TLB level but hit the second and do not cause page walks itlb_misses.walk_completed Code miss in all TLB levels causes a page walk that completes. (4K) Spec update: BDM69 Mem;SoC Average number of parallel requests to external memory. Accounts for all requests Retired load uops with L1 cache hits as data sources Supports address when precise (Precise event) Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: BDM100 (Precise event) offcore_response.all_data_rd.l3_hit.snoop_hitm offcore_response.all_pf_rfo.l3_hit.snoop_miss offcore_response.all_pf_rfo.supplier_none.snoop_not_needed Counts all demand & prefetch RFOs have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020008 offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020004 offcore_response.demand_data_rd.supplier_none.snoop_miss offcore_response.pf_l2_code_rd.l3_hit.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0040 offcore_response.pf_l2_code_rd.supplier_none.any_snoop offcore_response.pf_l2_code_rd.supplier_none.snoop_none offcore_response.pf_l2_data_rd.supplier_none.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020100 Randomly selected loads with latency value being above 64 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000122 offcore_response.corewb.l3_miss.snoop_none offcore_response.demand_data_rd.l3_miss.snoop_none offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020100 event=0x34,umask=0x26 offcore_response.demand_rfo.llc_hit.any_response Counts all demand & prefetch code reads miss in the L3 offcore_response.all_data_rd.llc_miss.remote_hit_forward event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC007F7 Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache l1d_cache.all_ref l1d_cache.evict event=0x2c,period=200000,umask=0x48 L2 cacheable instruction fetch requests l2_ld.self.any.i_state l2_ld.self.any.mesi l2_ld.self.prefetch.i_state event=0x2d,period=200000,umask=0x48 l2_reject_busq.self.demand.i_state event=0x2e,period=200000,umask=0x7f l2_rqsts.self.prefetch.mesi event=0x2a,period=200000,umask=0x41 Floating point assists for retired operations event=0xaa,period=2000000,umask=0x2 event=0xaa,period=2000000,umask=0x1 event=0x7d,period=200000,umask=0x40 bus_drdy_clocks.all_agents bus_trans_mem.all_agents Partial bus transactions event=0x66,period=200000,umask=0xe0 event=0x88,period=2000000,umask=0x20 Instructions retired (precise event) (Must be precise) mul.s Micro-op reissues on a store-load collision uops_retired.any itlb.flush mem_load_retired.dtlb_miss page_walks.i_side_walks l2_reject_xq.all event=0xd0,period=200003,umask=0x21 Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem offcore_response.corewb.l2_miss.hitm_other_core offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_needed decode_restriction.predecode_wrong hw_interrupts.masked br_inst_retired.rel_call Retired mispredicted near indirect call instructions (Precise event capable) (Must be precise) event=0xc5,period=200003,umask=0x7e Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event event=0xca,period=200003 Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200004800 Page walk completed due to a demand load to a 4K page Retired load uops misses in L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM offcore_response.pf_l2_data_rd.l3_hit.any_response Randomly selected loads with latency value being above 128 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00040 Counts prefetch (that bring data to L2) data reads miss in the L3 Number of near branch instructions retired that were taken but mispredicted (Precise event) ild_stall.iq_full Number of instructions at retirement Spec update: HSD11, HSD140 Number of integer move elimination candidate uops that were eliminated Number of microcode assists invoked by HW upon uop writeback L3 Lookup external snoop request that access cache and found line in MESI-state event=0x22,umask=0x88 event=0x22,umask=0x28 Number of cache load STLB hits. No page walk Store misses in all DTLB levels that cause completed page walks Store misses in all DTLB levels that cause completed page walks (2M/4M) Store miss in all TLB levels causes a page walk that completes. (4K) page_walker_loads.ept_dtlb_l1 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400001 l2_l1d_wb_rqsts.hit_e Retired load uops with locked access. (Precise Event) Cases when offcore requests buffer cannot take more entries for core Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores arith.fpu_div Cycles per core when uops are dispatched to port 0 This 48-bit fixed counter counts the UCLK cycles. Unit: uncore_arb A snoop invalidates a non-modified line in some processor core. Unit: uncore_cbox A snoop hits a non-modified line in some processor core. Unit: uncore_cbox event=0x22,umask=0x20 Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.all_reads.llc_hit.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c03f7 offcore_response.pf_l2_data_rd.llc_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800244 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f8203f7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800004 Counts demand data reads that miss the LLC and the data returned from remote & local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20001 Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram event=0x35,umask=0x1,filter_opc=0x1e4 unc_c_tor_occupancy.miss_remote (UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100. unc_p_freq_band3_transitions Cycles when 1 or more uops were delivered to the by the front end event=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400077 event=0x89,period=200003,umask=0xd0 Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 event=0x3,period=100003,umask=0x10 Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles Counts all the load micro-ops retired event=0x4,period=200003,umask=0x20 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400044 offcore_response.any_code_rd.l2_hit_near_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000044 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000044 offcore_response.any_data_rd.l2_hit_far_tile_e_f Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080070 Counts any Read request that accounts for any response offcore_response.any_request.l2_hit_far_tile_e_f Counts any request that accounts for responses which hit its own tile's L2 with data in S state offcore_response.any_rfo.l2_hit_near_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080001 offcore_response.demand_rfo.l2_hit_far_tile_e_f offcore_response.partial_reads.l2_hit_this_tile_m offcore_response.partial_writes.l2_hit_far_tile_e_f Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state offcore_response.pf_software.l2_hit_near_tile Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400200 Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding offcore_response.any_code_rd.mcdram Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local offcore_response.any_data_rd.mcdram_near event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101008000 offcore_response.demand_code_rd.ddr_far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400080 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400100 offcore_response.pf_l2_code_rd.mcdram_far Counts Software Prefetches that accounts for responses from DDR (local and far) unc_m_cas_count.rd L1D cache lines allocated in the M state L1D load lock accepted in fill buffer L1 writebacks to L2 in M state l2_write.lock.i_state event=0x27,period=100000,umask=0x10 L2 demand lock RFOs in I state (misses) Offcore data reads satisfied by the IO, CSR, MMIO unit offcore_response.any_data.remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x744 Offcore code reads that HIT in a remote cache offcore_response.any_ifetch.remote_cache_hitm Offcore code or data read requests satisfied by a remote cache or remote DRAM offcore_response.data_in.llc_hit_other_core_hit Offcore demand data requests that HIT in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x803 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x401 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x104 offcore_response.demand_ifetch.remote_cache Offcore prefetch data requests that HIT in a remote cache All offcore prefetch data reads offcore_response.pf_data_rd.llc_hit_other_core_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4710 Offcore prefetch RFO requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x720 offcore_response.pf_rfo.remote_cache Offcore prefetch requests satisfied by the LLC store_blocks.l1d_block fp_assist.output fp_comp_ops_exe.sse_fp fp_comp_ops_exe.sse_fp_scalar event=0x19,period=2000000,umask=0x1 Offcore RFO requests satisfied by any DRAM offcore_response.demand_data_rd.any_llc_miss event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF801 offcore_response.demand_rfo.remote_dram l1i.reads event=0x7,period=200000,umask=0x1 snoop_response.hit Instruction queue forced BACLEAR br_inst_exec.near_calls event=0x88,period=20000,umask=0x30 Retired branch instructions (Precise Event) Cycles when thread is not halted (programmable counter) event=0xc3,period=20000,umask=0x4 rat_stalls.scoreboard uops_decoded.esp_sync uops_executed.core_stall_count Uops executed on any port (core count) Cycles no Uops were issued on any thread event=0xc2,cmask=1,period=2000000,umask=0x1 event=0xf2,period=200003,umask=0x1 Retired load instructions with locked access Supports address when precise (Precise event) Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point offcore_response.demand_data_rd.l3_hit_m.spl_hit offcore_response.demand_data_rd.l3_hit_s.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000400002 offcore_response.demand_rfo.supplier_none.any_snoop offcore_response.other.l3_hit_e.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80088000 offcore_response.other.l3_hit_e.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0048000 event=0xc6,period=100007,umask=0x1,frontend=0x400406 frontend_retired.stlb_miss Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC400001 offcore_response.other.l3_hit_m.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC408000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC408000 offcore_response.other.l3_miss.spl_hit event=0x3c,period=25003,umask=0x1 Number of cycles using always true condition applied to PEBS instructions retired event Spec update: SKL091, SKL044 (Must be precise) Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5 uops_issued.vector_width_mismatch 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) Total penalty related to DSB (uop cache) misses - subset/see of/the Instruction_Fetch_BW Bottleneck All Stores event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000018008 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400008008 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000040 The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch Counts all machine clears This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS) (Precise event) Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all prefetch code reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0120 offcore_response.pf_llc_rfo.llc_hit.snoop_miss Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response offcore_response.all_pf_data_rd.llc_miss.dram offcore_response.pf_l_ifetch.llc_miss_local.dram Offcore demand code read requests event=0x60,cmask=1,period=2000000,umask=0x2 offcore_response.any_rfo.local_dram_and_remote_cache_hit REQUEST = OTHER and RESPONSE = LOCAL_CACHE REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE offcore_response.any_request.other_local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3050 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf840 REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS snoopq_requests_outstanding.data Cycles snoop invalidate requests queued dtlb_misses.walk_cycles event=0xb7,period=100000,umask=0x1,offcore_rsp=0x58FF event=0xf,period=40000,umask=0x4 Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.demand_code_rd.l3_hit.no_snoop_needed offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00001 Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache offcore_response.pf_l1d_and_sw.l3_miss.remote_hitm Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 core_power.lvl1_turbo_license LLC misses - Uncacheable reads (from cpu) . Unit: uncore_cha unc_cha_requests.writes_local unc_iio_data_req_of_cpu.mem_read.part2 event=0x37,umask=0x01 Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state unc_cha_requests.invitoe_remote Ingress (from CMS) Occupancy; IRQ. Unit: uncore_cha Counts number of entries in the specified Ingress queue in each cycle Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline event=0xc2,ch_mask=0x01,fc_mask=0x4,umask=0x03 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Read request for up to a 64 byte transaction is made by the CPU to IIO Part1. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Read request for up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x01 Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus unc_m2m_direct2core_not_taken_dirstate unc_m2m_directory_update.a2i event=0x2e,umask=0x40 event=0x38,umask=0x2 event=0x57 Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller) uncore_m3upi event=0x21 unc_upi_rxl0p_power_cycles ocr.all_data_rd.l3_hit.hitm_other_core ocr.all_data_rd.l3_hit.snoop_miss OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080490 OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100490 ocr.all_pf_rfo.l3_hit_f.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100120 OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000807F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800407F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0122 OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP ocr.all_rfo.l3_hit_m.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100122 ocr.demand_code_rd.l3_hit.hit_other_core_fwd Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD ocr.demand_data_rd.l3_hit.hitm_other_core ocr.demand_data_rd.l3_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0001 ocr.demand_data_rd.l3_hit_e.hitm_other_core Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80088000 Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080400 Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE ocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100080 ocr.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200100 ocr.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd ocr.pf_l3_rfo.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_data_rd.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE offcore_response.all_pf_rfo.l3_hit_s.snoop_miss offcore_response.all_reads.l3_hit_e.hit_other_core_no_fwd offcore_response.all_reads.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.demand_code_rd.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE offcore_response.demand_rfo.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.demand_rfo.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD offcore_response.other.supplier_none.hit_other_core_no_fwd offcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE offcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwd offcore_response.pf_l2_data_rd.l3_hit_m.snoop_miss offcore_response.pf_l2_data_rd.l3_hit_s.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l2_rfo.l3_hit_e.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_s.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400020 offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020020 This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.pf_l3_data_rd.l3_hit_e.hitm_other_core offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_fwd offcore_response.pf_l3_data_rd.l3_hit_f.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020080 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000490 OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_miss.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC0007F7 ocr.all_reads.l3_miss_local_dram.any_snoop ocr.all_reads.l3_miss_local_dram.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10040007F7 OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.demand_data_rd.l3_miss.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000001 ocr.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000010 ocr.pf_l2_data_rd.l3_miss.remote_hit_forward event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000020 ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_none ocr.pf_l3_rfo.l3_miss.snoop_miss This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_rfo.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.all_pf_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP offcore_response.all_reads.l3_miss_local_dram.hit_other_core_fwd offcore_response.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_none This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD offcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.other.l3_miss_remote_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP ocr.all_rfo.supplier_none.snoop_none OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache ocr.demand_code_rd.l3_hit.snoop_hitm ocr.demand_code_rd.l3_hit.snoop_sent ocr.other.l3_hit.snoop_not_needed For every cycle, increments by the number of outstanding data read requests pending Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event) Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event) Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event) Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) ocr.demand_data_rd.l3_miss ocr.demand_rfo.l3_miss Counts the number of times we could not allocate Lock Buffer event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000001 ocr.hwpf_l1d_and_swpf.local_dram ocr.hwpf_l2_rfo.dram Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request Not taken branch instructions retired (Precise event) br_inst_retired.indirect event=0xc4,period=100003,umask=0x80 uops_decoded.dec0 uops_executed.cycles_ge_4 Instructions Per Cycle (per physical core) ocr.demand_data_rd.remote_cache.snoop_hitm Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified) ocr.demand_rfo.l3_miss_local Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches core_snoop_response.i_fwd_m HitM snoop reply with data, line invalidated event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FFC0002 ocr.itom.remote ocr.reads_to_core.remote unc_m_rpq_occupancy_pch0 TOR Inserts : CRds issued by iA Cores that Hit the LLC. Unit: uncore_cha event=0x36,umask=0xC807FF01 TOR Occupancy : DRds issued by iA Cores. Unit: uncore_cha TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.io_pcirdcur unc_iio_data_req_by_cpu.mem_read.part5 event=0xc2,ch_mask=0x80,fc_mask=0x04,umask=0x03 PCIe Completion Buffer Inserts of completions with data: Part 7. Unit: uncore_iio event=0xd5,fc_mask=0x04,umask=0x10 unc_i_misc1.lost_fwd Multi-socket cacheline Directory Lookups : Found in A state. Unit: uncore_m2m event=0x2e,umask=0x01 Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis mem_bound_stalls.ifetch_dram_hit mem_bound_stalls.load_dram_hit Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0477 Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches (Precise event) This event is deprecated event=0x71,period=1000003,umask=0x1 Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC unc_cha_tor_inserts.ia_drd_opt TOR Inserts; Data read from local IA that misses in the snoop filter TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0x36,umask=0xC8A7FF01 TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC. Unit: uncore_cha PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 event=0x85,period=2000003,umask=0x80 Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache). Unit: cpu_core Fraction of branches of other types (not individually covered by other metrics in Info.Branches group). Unit: cpu_core L1 cache true misses per kilo instruction for all demand loads (including speculative). Unit: cpu_core Average CPU Utilization. Unit: cpu_core TOPDOWN_FE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE) Cycles_per_Demand_Load_L2_Hit Cycles_per_Demand_Load_L3_Hit offcore_requests_outstanding.data_rd event=0x5,period=1000003,umask=0xff Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page. Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts. Unit: cpu_atom event=0xe7,period=1000003,umask=0x3 The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. Unit: cpu_core Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch. Unit: cpu_core Cycles where at least 3 uops were executed per-thread. Unit: cpu_core Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss when load subsequently retires. Unit: cpu_atom event=0x13,period=100003,umask=0x20 event=0x13,period=100003,umask=0x2 Retired load instructions which data sources missed L3 but serviced from local dram Supports address when precise event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808000001 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708004477 Uops executed on ports 7 and 8 event=0x3,umask=0x0000000080 event=0x3,umask=0x0000000044 event=0x50,umask=0x0000000030 event=0x35,umask=0x00C8977E01 Valid Flits Received : Slot 0. Unit: uncore_upi Tx Flit Buffer Occupancy. Unit: uncore_upi event=0x11,umask=0x0000000008 event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000004 event=0xc2,ch_mask=0x20,fc_mask=0x07,umask=0x0000000004 event=0xc2,ch_mask=0x80,fc_mask=0x07,umask=0x0000000004 event=0x21,umask=0x0301 TOR Inserts; CRd hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c88ffd01 event=0x35,umask=0x00c827fd01 TOR Inserts; RFO pref misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c803ff04 unc_cha_tor_inserts.ia_drd event=0x36,umask=0x00C001FF08 event=0x36,umask=0x00c887fd01 All LLC lines in S state that are victimized on a fill. Unit: uncore_cha event=0x35,umask=0x00cd43fe04 event=0x35,umask=0x00c837fe01 unc_cha_tor_inserts.ia_drdpte TOR Occupancy; LLCPrefData hits from local IA. Unit: uncore_cha TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_crd_remote event=0x35,umask=0x00C88F7E01 TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha event=0x35,umask=0x00C86F8A01 TOR Inserts : CLFlushes issued by IO Devices. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_crd_pref_local unc_cha_tor_occupancy.ia_wbmtoi event=0x87,umask=0x02 All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event l2_latency.l2_cycles_waiting_on_fills event=0x63,umask=0x20 l2_cache_req_stat.ic_dc_miss_in_l2 event=0,umask=0x40 fpu_pipe_assignment.total1 This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops ls_dispatch.store_dispatch ls_tablewalker.dc_type1 L2 DTLB Misses & Data page walks 6.1e-5MiB Total number of fp uOps ls_hw_pf_dc_fill.ls_mabresp_lcl_cache Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semantics Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types). Use l2_cache_misses_from_dc_misses instead L1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB ls_mab_alloc.load_store_allocations event=0x44,umask=0x40 ls_any_fills_from_sys.ext_cache_local All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead ls_sw_pf_dc_fills.mem_io_local event=0x5a,umask=0x04 de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch de_dis_dispatch_token_stalls1.fp_flush_recovery_stall L2 Cache Misses from L2 Cache HWPF Retired branch instructions mispredicted due to direction mismatch ls_dmnd_fills_from_sys.local_l2 Demand data cache fills from cache of another CCX when the address was in the same NUMA node ls_any_fills_from_sys.dram_io_near Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket) Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access) ls_hw_pf_dc_fills.local_ccx l2_pf_hit_l2.all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region) L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stream (fetch additional sequential lines into L2 cache) event=0x72,umask=0x02 Instruction cache lines (64 bytes) fulfilled from the L2 cache l3_xi_sampled_latency.dram_near event=0xac,umask=0x20 local_processor_read_data_beats_cs0 Read data beats (64 bytes) for local processor at Coherent Station (CS) 0 event=0x5f,umask=0x7fe event=0x11f,umask=0x7fe event=0x21f,umask=0x7fe Read data beats (64 bytes) for local processor at Coherent Station (CS) 10 Write data beats (64 bytes) for local processor at Coherent Station (CS) 7 local_processor_write_data_beats_cs9 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 4 remote_socket_upstream_write_beats_iom1 event=0x49e,umask=0x7fe event=0x49f,umask=0x7ff event=0x51f,umask=0xbfe Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 5 Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 0 local_socket_outbound_data_beats_link1 fp_ret_x87_fp_ops.div_sqrt_ops Retired packed 256-bit floating-point ops fp_ops_retired_by_type.scalar_blend event=0xa,umask=0x30 Retired vector floating-point ops of other types Retired MMX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) sse_avx_ops_retired.sse_avx_mul event=0xb,umask=0x70 fp_pack_ops_retired.fp128_other Retired 256-bit packed floating-point multiply ops event=0xd,umask=0xd0 L1 DTLB misses for all page sizes Number of cycles dispatch is stalled for integer scheduler queue 0 tokens Fraction of dispatch slots that remained unused because the frontend did not supply enough instructions/ops l1_data_cache_fills_from_same_ccx local_socket_upstream_read_beats_iom0 + local_socket_upstream_read_beats_iom1 + local_socket_upstream_read_beats_iom2 + local_socket_upstream_read_beats_iom3 local_socket_upstream_dma_read_data umc_mem_read_bandwidth event-hyphen UNC_CBO_TWO_HYPH. Unit: uncore_cbox BU_CPU_CLK_UNHALTED EXC_TAKEN L1_DCACHE_WB L1_DCACHE_NEON_ACCESS L2_CACHE_NEON_HIT PMUEXTIN1_EVT EVENT_4FH EVENT_5CH EVENT_83H EVENT_BEH EVENT_E7H EVENT_10DH EVENT_113H EVENT_152H EVENT_188H EVENT_195H EVENT_1C2H EVENT_1D3H EVENT_20AH EVENT_21BH EVENT_24AH EVENT_254H EVENT_25CH EVENT_260H EVENT_262H EVENT_28BH EVENT_29FH EVENT_2A8H EVENT_2AEH EVENT_2B5H EVENT_308H EVENT_339H EVENT_347H EVENT_370H EVENT_3A1H EVENT_3CBH EVENT_3D8H EVENT_3E0H EXC_TRAP_PABORT dn_rxreq_snp_sent hnf_slc_sf_cache_access hni_rdt_wr_alloc sbsx_txrsp_flitv rnd_wrt_occ_ovfl cxha_sdb_occ cxra_wr_dat_buf_occ L3_EXTERNAL_INTERVENTIONS CACHEOPS_TRANSLATED WRITE_THROUGH_STORES_TRANSLATED STORES_COMPLETED_ALLOCATED_TO_DLFB INSTR_L1_CACHE_LOCKS DLFB_RETRIES_TO_MBAR L2_CACHE_INSTR_HITS DVT5_DETECTED DVT6_DETECTED DECORATED_LOADS owner page-hit nonpostwrszdword E500 FREE metric_expr: %s
config1 basic_string %s, "pmcid": "0x%08x", "pid": "%d", "pathname": "%s"}
"0x%016jx"]}
GenuineIntel-6-5C Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate) 1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY Summary;Power ( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time Kernel_Utilization Average external Memory Bandwidth Use for reads and writes [GB / sec] ( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time 1000000000 * ( cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x35\,umask\=0x3\,filter_opc\=0x182@ ) / ( cbox_0@event\=0x0@ / duration_time ) (cstate_core@c3\-residency@ / msr@tsc@) * 100 event=0x24,period=200003,umask=0xe7 Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) Supports address when precise. Spec update: BDM100 (Precise event) mem_load_uops_retired.hit_lfb mem_load_uops_retired.l2_miss mem_uops_retired.split_loads offcore_response This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE event=0xc8,period=2000003,umask=0x2 Number of times we entered an HLE region; does not count nested transactions mem_trans_retired.load_latency_gt_64 This event counts speculative cache-line split load uops dispatched to the L1 cache Speculative cache line split STA uops dispatched to L1 cache rtm_retired.start pipeline This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed br_inst_exec.taken_direct_near_call br_misp_exec.taken_indirect_jump_non_call_ret event=0x89,period=200003,umask=0x84 Taken speculative and retired mispredicted indirect calls Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event) event=0,period=2000003,umask=0x2 cycle_activity.cycles_ldm_pending event=0xd,cmask=1,period=2000003,umask=0x3 This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0 resource_stalls.rs event=0xa2,period=2000003,umask=0x4 event=0xb1,cmask=3,period=2000003,umask=0x2 Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch Uncore cache clock ticks. Unit: uncore_cbox event=0x34,umask=0x11,filter_state=0x1 64Bytes unc_c_llc_victims.m_state LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.rfo_llc_prefetch event=0x35,umask=0x3,filter_opc=0x192 read requests to remote home agent. Unit: uncore_ha event=0x1,umask=0x4 unc_m_power_self_refresh unc_p_power_state_occupancy.cores_c0 unc_p_freq_max_power_cycles dtlb_load_misses.miss_causes_a_walk This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific) event=0x85,period=100003,umask=0x40 itlb_misses.stlb_hit_4k tlb_flush.dtlb_thread event=0xbd,period=100007,umask=0x1 Retired store uops that miss the STLB Supports address when precise (Precise event) Counts all demand & prefetch data reads Counts all prefetch code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0090 offcore_response.all_pf_rfo.supplier_none.snoop_hitm Counts all demand & prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0122 offcore_response.all_rfo.supplier_none.any_snoop offcore_response.all_rfo.supplier_none.snoop_miss Counts writebacks (modified to exclusive) Counts all demand code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020004 offcore_response.demand_data_rd.supplier_none.snoop_none offcore_response.demand_data_rd.supplier_none.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0002 Counts any other requests event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0040 offcore_response.pf_l2_code_rd.supplier_none.snoop_not_needed offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_no_fwd offcore_response.pf_l2_rfo.supplier_none.snoop_hit_no_fwd offcore_response.pf_l3_code_rd.l3_hit.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020100 Randomly selected loads with latency value being above 128 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000091 offcore_response.all_pf_code_rd.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000240 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020010 offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000200 offcore_response.pf_l3_rfo.l3_hit.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000100 Number of times RTM abort was triggered (Precise event) This event counts conditional branch instructions retired (Precise event) This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event) This event counts resource-related stall cycles A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core. Unit: uncore_cbox event=0x22,umask=0x48 L3 Lookup any request that access cache and found line in I-state. Unit: uncore_cbox This 48-bit fixed counter counts the UCLK cycles event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C8FFF Counts all demand & prefetch RFOs miss in the L3 Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data. Unit: uncore_qpi event=0x40,period=200000,umask=0x8 event=0x27,period=200000,umask=0x70 event=0x30,period=200000,umask=0x41 l2_reject_busq.self.demand.mesi event=0x2e,period=200000,umask=0x71 event=0x2e,period=200000,umask=0x52 SIMD Instructions retired SIMD packed logical micro-ops retired x87_comp_ops_exe.fxch.ar event=0x7,period=200000,umask=0x8f L0 DTLB misses due to load operations page_walks.walks Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.any_request.l2_miss.hitm_other_core offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_needed Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000080 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000010 Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache offcore_response.pf_l2_data_rd.l2_miss.hitm_other_core event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000020 cycles_div_busy.fpdiv Counts core cycles the floating point divide unit is busy Machine clears due to FP assists References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture Counts branch instructions retired for all branch types. This is an architectural performance event (Must be precise) Counts near relative CALL branch instructions retired (Must be precise) Retired mispredicted near return instructions (Precise event capable) (Must be precise) Retired mispredicted conditional branch instructions that were taken (Precise event capable) (Must be precise) ld_blocks.data_unknown Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB) (Must be precise) Counts machine clears for any reason event=0x9c,period=200003 Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010010 offcore_response.pf_l2_rfo.outstanding event=0xc3,period=20003,umask=0x4 Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault event=0x85,period=200003,umask=0x10 Demand Data Read miss L2, no rejects Spec update: HSD78, HSM80 All requests to L2 cache Spec update: HSD78, HSM80 This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event) Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded offcore_response.pf_l2_rfo.l3_hit.any_response This event counts Instruction Cache (ICACHE) misses Number of times an HLE execution started event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC08FFF Counts all prefetch (that bring data to LLC only) code reads miss in the L3 Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops event=0x34,umask=0x46 This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks event=0xd3,period=100003,umask=0x10 Dirty L2 cache lines filling the L2 event=0x24,period=200003,umask=0xc event=0x24,period=200003,umask=0x80 event=0x24,period=200003,umask=0x4 Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores event=0xb7,period=100003,umask=0x1,offcore_rsp=0x000105B3 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010122 Counts all writebacks from the core to the LLC Counts all demand code reads that hit in the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0001 Counts all demand rfo's Counts number of SSE* or AVX-128 double precision FP scalar uops executed 1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY Loads with latency value being above 512 (Must be precise) Speculative cache-line split Store-address uops dispatched to L1D Counts all demand & prefetch code reads that miss the LLC and the data returned from dram offcore_response.all_reads.llc_miss.dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3004003f7 Cycles which a Uop is dispatched on port 0 Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core unc_cbo_xsnp_response.inval_m A snoop invalidates a modified line in some processor core offcore_response.all_reads.llc_hit.snoop_miss Counts all data/code/rfo reads (demand & prefetch) that hit the LLC Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there PCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_inserts.miss_opcode.ddio_miss. Unit: uncore_cbox LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox event=0x35,umask=0x1,filter_opc=0x1e6 Write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu freq_band2_cycles % unc_p_freq_ge_3000mhz_cycles event=0x51,period=2000003,umask=0x4 Retired load uops which data sources were HitM responses from shared LLC This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2 UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY UOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.CORE\,cmask\=1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\,cmask\=1@) Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded QPI clock ticks. Used to get percentages of QPI cycles events. Unit: uncore_qpi Counts the number of times that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu offcore_response.any_data_rd.l2_hit_near_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010003091 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000070 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004008000 offcore_response.any_request.l2_hit_this_tile_f offcore_response.any_rfo.l2_hit_far_tile event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080022 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080022 Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010002000 offcore_response.pf_l2_code_rd.l2_hit_near_tile event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000040 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800401000 offcore_response.uc_code_reads.any_response offcore_response.uc_code_reads.l2_hit_near_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000044 Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.any_read.ddr_far Counts any Read request that accounts for data responses from DRAM Far offcore_response.demand_data_rd.ddr_near event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200001 offcore_response.demand_rfo.mcdram_far offcore_response.partial_reads.ddr_far offcore_response.partial_writes.mcdram_far Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080802000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x2000020020 Counts Software Prefetches that accounts for data responses from DRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400200 no_alloc_cycles.not_delivered Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included event=0x40,period=2000000,umask=0x8 l1d_wb_l2.s_state l2_data_rqsts.prefetch.s_state l2_rqsts.ifetch_hit event=0x24,period=200000,umask=0x1 Memory instructions retired above 32 clocks (Precise Event) mem_uncore_retired.other_core_l2_hitm offcore_response.any_data.any_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4744 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1822 offcore_response.data_in.llc_hit_no_other_core Offcore request = all data, response = local cache Offcore request = all data, response = local cache or dram offcore_response.demand_data.llc_hit_no_other_core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x201 Offcore demand data reads satisfied by the LLC Offcore demand data reads satisfied by a remote cache or remote DRAM Offcore demand code reads satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4702 Offcore demand RFO requests that HITM in a remote cache Offcore other requests satisfied by the LLC and HITM in a sibling core offcore_response.other.remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x830 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F10 Offcore prefetch code reads satisfied by any cache or DRAM offcore_response.pf_ifetch.remote_cache_hit event=0xfd,period=200000,umask=0x20 event=0xfd,period=200000,umask=0x2 offcore_response.any_data.remote_dram offcore_response.any_ifetch.remote_dram Offcore requests that missed the LLC offcore_response.any_rfo.any_dram Offcore code or data read requests that missed the LLC Offcore request = all data, response = any DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2001 offcore_response.other.any_llc_miss event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF830 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF870 event=0xd5,period=2000000,umask=0x1 l1i.cycles_stalled event=0xb8,period=100000,umask=0x1 snoop_response.hite bpu_missed_call_ret Taken branches executed event=0x87,period=2000000,umask=0xf ssex_uops_retired.scalar_double Stack pointer sync operations event=0xd1,cmask=1,period=2000000,umask=0x2 uops_executed.port4_core DTLB load miss caused by low part of address event=0x8,period=2000000,umask=0x10 DTLB miss page walks l2_lines_out.non_silent offcore_response.demand_code_rd.l3_hit_e.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40400004 offcore_response.demand_data_rd.l3_hit_m.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020001 offcore_response.demand_rfo.l3_hit.spl_hit offcore_response.demand_rfo.l3_hit_e.snoop_hit_no_fwd offcore_response.demand_rfo.l3_hit_s.snoop_none offcore_response.demand_rfo.l3_hit_s.spl_hit offcore_response.other.l3_hit_e.snoop_hitm offcore_response.other.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80028000 event=0x32,period=2000003,umask=0x4 Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore frontend_retired.l2_miss frontend_retired.latency_ge_1 event=0xc6,period=100007,umask=0x1,frontend=0x400206 event=0xc6,period=100007,umask=0x1,frontend=0x100206 event=0xc6,period=100007,umask=0x1,frontend=0x300206 Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ offcore_response.demand_data_rd.l3_hit_m.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4008000 rtm_retired.aborted_events br_inst_retired.cond_ntaken event=0x55,period=2000003,umask=0x1 event=0xb1,cmask=1,inv=1,period=2000003,umask=0x2 Counts the retirement slots used Mispredictions_SMT Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches) 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (10 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) ) ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\,cmask\=1@ BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES offcore_response.demand_data_rd.l2_miss.snoop_miss offcore_response.demand_rfo.l2_miss.snoop_miss Counts the number of JCC baclears Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks Counts all data/code/rfo references (demand & prefetch) COREWB & ANY_RESPONSE offcore_requests_outstanding.any.read offcore_requests_outstanding.demand.read_data_not_empty REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE REQUEST = ANY RFO and RESPONSE = ANY_LOCATION REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE offcore_response.demand_ifetch.all_local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5004 REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3011 REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3044 offcore_response.other.any_dram_and_remote_fwd event=0xc5,period=20000,umask=0x4 DTLB misses casued by low part of address event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F50 DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts demand data reads that hit in the L3 Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00122 Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00004 Counts demand data reads that miss the L3 and the modified data is transferred from remote cache offcore_response.pf_l2_rfo.l3_miss.snoop_miss_or_no_fwd offcore_response.pf_l3_data_rd.l3_miss.remote_hitm Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache CORE_POWER.LVL1_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not uncore_upi event=0x33,umask=0x42 Counts number of allocations per cycle into the specified Ingress queue event=0x5c,umask=0x20 event=0x5c,umask=0x10 unc_iio_comp_buf_occupancy.cmpd.all_parts event=0xd5,fc_mask=0x04,umask=0x04 unc_iio_data_req_by_cpu.mem_write.part1 unc_iio_txn_req_by_cpu.peer_read.part3 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x01 Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus unc_m2m_bypass_m2m_egress.not_taken event=0x29 Inserts into the Memory Controller Prefetch Queue. Unit: uncore_m2m unc_m2m_rxc_ad_inserts event=0x12,umask=0x1 ocr.all_data_rd.l3_hit_m.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040491 ocr.all_data_rd.l3_hit_s.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040490 OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200120 ocr.all_pf_rfo.l3_hit_f.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C07F7 ocr.all_reads.l3_hit.snoop_none ocr.all_reads.l3_hit_e.any_snoop ocr.all_reads.l3_hit_s.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080122 OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040122 OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP ocr.demand_code_rd.l3_hit_m.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040004 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD ocr.demand_rfo.l3_hit_s.snoop_none ocr.other.l3_hit.hitm_other_core ocr.other.l3_hit.snoop_miss ocr.other.l3_hit_m.snoop_none Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD ocr.pf_l1d_and_sw.l3_hit_e.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080010 ocr.pf_l2_data_rd.l3_hit_e.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200080 ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_fwd ocr.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100080 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP ocr.pf_l3_rfo.l3_hit_f.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_hit_m.snoop_miss offcore_response.all_data_rd.l3_hit_s.hit_other_core_fwd offcore_response.all_data_rd.l3_hit_s.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020491 This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS offcore_response.all_pf_rfo.l3_hit_f.hit_other_core_fwd offcore_response.all_pf_rfo.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000207F7 This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE offcore_response.all_rfo.l3_hit_m.hit_other_core_no_fwd offcore_response.demand_code_rd.l3_hit_e.no_snoop_needed offcore_response.demand_code_rd.l3_hit_m.no_snoop_needed offcore_response.demand_data_rd.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_hit_s.no_snoop_needed offcore_response.demand_data_rd.pmm_hit_local_pmm.any_snoop offcore_response.demand_rfo.l3_hit_m.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400002 offcore_response.demand_rfo.pmm_hit_local_pmm.snoop_not_needed offcore_response.demand_rfo.supplier_none.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_data_rd.l3_hit_e.snoop_miss offcore_response.pf_l3_data_rd.l3_hit_f.snoop_none offcore_response.pf_l3_data_rd.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD ocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_none ocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwd ocr.all_pf_rfo.l3_miss.any_snoop ocr.all_pf_rfo.l3_miss.no_snoop_needed ocr.all_pf_rfo.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C0007F7 OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_miss.no_snoop_needed ocr.demand_data_rd.l3_miss_local_dram.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000002 ocr.demand_rfo.l3_miss_local_dram.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C008000 ocr.other.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC08000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000010 Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000080 Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.pf_l2_rfo.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD offcore_response.pf_l2_rfo.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED ocr.all_pf_rfo.pmm_hit_local_pmm.any_snoop OCR.ALL_RFO.ANY_RESPONSE have any response type OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.all_rfo.supplier_none.hitm_other_core Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.demand_data_rd.supplier_none.any_snoop Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED ocr.demand_rfo.supplier_none.no_snoop_needed ocr.pf_l2_data_rd.pmm_hit_local_pmm.any_snoop ocr.pf_l2_data_rd.supplier_none.snoop_miss Write commands for Intel Optane DC persistent memory. Unit: uncore_imc Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory event=0x48,period=1000003,umask=0x4 Number of L1D misses that are outstanding Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0001 Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data ocr.hwpf_l2_rfo.l3_hit.snoop_hitm Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events event=0x79,cmask=5,period=2000003,umask=0x4 Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB) ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED (cstate_pkg@c10\-residency@ / msr@tsc@) * 100 Counts demand data reads that was not supplied by the L3 cache Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache event=0xc5,period=50021,umask=0x10 Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken (Precise event) Counts cycles where the Store Buffer was full and no loads caused an execution stall Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses) Uops exclusively fetched by decoder 0 event=0xc2,cmask=1,inv=1,period=1000003,umask=0x2 Number of page walks outstanding for a store in the PMH each cycle Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode) Supports address when precise (Precise event) Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket event=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000002 For every cycle, increments by the number of outstanding code read requests pending UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@event\=0x36\,umask\=0xC817FE01\,thresh\=1@ Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode event=0xb7,period=100003,umask=0x1,offcore_rsp=0x703C00002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000477 Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket Number of DRAM Refreshes Issued. Unit: uncore_imc Local read requests that miss the SF/LLC and are sent to the CHA's home agent. Unit: uncore_cha unc_cha_tor_occupancy.ia event=0x36,umask=0xC807FE01 unc_cha_tor_occupancy.io_miss event=0x35,umask=0xC8178601 Cache and Snoop Filter Lookups; Data Read Request. Unit: uncore_cha Data requested of the CPU : CmpD - device sending completion to CPU request. Unit: uncore_iio Number Transactions requested by the CPU : Core writing to Card's MMIO space. Unit: uncore_iio event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x01 unc_iio_data_req_of_cpu.mem_read.part6 Multi-socket cacheline Directory Lookups : Found in S state. Unit: uncore_m2m event=0x2c,umask=0x01 unc_cha_tor_inserts.io_itomcachenear_local Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode. Unit: uncore_m2m Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode Page walks completed due to a demand data load to a 1G page l2_reject_xq.any Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0044 Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded ocr.hwpf_l2_rfo.l3_hit.snoop_hit_with_fwd Counts the number of instruction cache hits ocr.corewb_m.l3_miss_local ocr.demand_data_and_l1pf_rd.l3_miss_local Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache event=0x3,period=1000003,umask=0x1 topdown_fe_bound.other DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page ept.epdpe_miss event=0x85,period=2000003,umask=0x20 Instruction per taken branch. Unit: cpu_core TOPDOWN_RETIRING.ALL / (5 * CPU_CLK_UNHALTED.CORE) Percentage of total non-speculative loads that are splits. Unit: cpu_atom Number of Instructions per non-speculative Branch Misprediction. Unit: cpu_atom X87_Uop_Ratio Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled Supports address when precise (Must be precise). Unit: cpu_atom All L2 requests.[This event is alias to L2_RQSTS.REFERENCES]. Unit: cpu_core Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event). Unit: cpu_core Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event). Unit: cpu_core event=0x20,cmask=1,period=1000003,umask=0x4 Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core frontend_retired.unknown_branch Cycles where a code fetch is stalled due to L1 instruction cache tag miss. Unit: cpu_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400002 event=0x47,cmask=3,period=1000003,umask=0x3 memory_activity.stalls_l2_miss Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Unit: cpu_core Counts the number of unhalted core clock cycles. (Fixed event). Unit: cpu_atom Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation. Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls). Unit: cpu_atom Counts the number of integer divide uops retired (Precise event). Unit: cpu_atom Counts the number of x87 uops retired, includes those in MS flows (Precise event). Unit: cpu_atom Thread cycles when thread is not in halt state. Unit: cpu_core event=0xe7,period=1000003,umask=0x40 Cycles at least 2 micro-op is executed from any thread on physical core. Unit: cpu_core This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS. Unit: cpu_core Incoming VC0 write request. Unit: uncore_imc unc_m_cas_count_rd event=0x2a,period=100003,umask=0x1,offcore_rsp=0x730004477 event=0xc5,period=100003,umask=0x80 Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction event=0x20,umask=0x0000000001 event=0x2,umask=0x000000000f event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000001 TOR Inserts for DRd Pref misses from local IA. Unit: uncore_cha event=0x4,umask=0x000000010e event=0x5,umask=0x000000010e event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000004 event=0xc1,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000001 event=0x17,umask=0x07 event=0x2b unc_cha_llc_lookup.data_rd unc_cha_tor_inserts.all TOR Inserts; RFO hits from local IA. Unit: uncore_cha unc_cha_tor_inserts.ipq event=0x35,umask=0x0000000010 event=0x35,umask=0x00c8a7fd01 event=0x35,umask=0x00c803fd04 event=0x35,umask=0x00ccc7ff01 TOR Inserts; DRd Opt Pref from local IA. Unit: uncore_cha event=0x35,umask=0x00c80fff01 event=0x36,umask=0x00ccc7fe01 TOR Occupancy; RFO misses from local IA. Unit: uncore_cha event=0x36,umask=0x00c001fd04 event=0x36,umask=0x00c8a7fe01 unc_cha_tor_occupancy.io_itom TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally. Unit: uncore_cha TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0x00c88f7e01 event=0x36,umask=0x00c867fe01 unc_cha_tor_occupancy.ia_miss_wcil_pmm TOR Occupancy : WbMtoIs issued by IO Devices. Unit: uncore_cha event=0x8e ic_cache_fill_l2 Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1) event=0x8c,umask=0x01 event=0x99 All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized Retired Branch Instructions x87 instructions event=0xd4 ex_tagged_ibs_ops.ibs_count_rollover Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3 dram_channel_data_controller_5 Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS Number of SSE Move Ops event=0xaf,umask=0x40 l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3 l2_cache_accesses_from_dc_misses L2 Cache Accesses from L1 Data Cache Misses (including prefetch) All L2 Cache Hits event=0x45,umask=0xf0 Micro-ops Dispatched The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB page Floating Point Dispatch Faults. XMM fill fault de_dis_uops_from_decoder.decoder_dispatched bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 1G page event=0x28f,umask=0x04 ex_ret_ops Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Node Demand Data Cache Fills by Data Source. From Local L2 to the core de_dis_dispatch_token_stalls2.int_sch2_token_stall Dynamic indirect predictions (branch used the indirect predictor to make a prediction) Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit Hardware prefetch data cache fills from local L2 cache L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fetch additional sequential lines into L1 cache) l2_pf_miss_l2_hit_l3.all l2_pf_miss_l2_l3.l1_stream event=0x72,umask=0x80 Op cache misses Op cache accesses of all types Retired macro-ops Read data beats (64 bytes) for local processor at Coherent Station (CS) 1 Read data beats (64 bytes) for local processor at Coherent Station (CS) 6 event=0x1f,umask=0x7ff local_processor_write_data_beats_cs6 local_processor_write_data_beats_cs10 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 6 remote_processor_write_data_beats_cs9 local_socket_inf0_inbound_data_beats_ccm5 Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 5 local_socket_inf1_inbound_data_beats_ccm0 local_socket_inf1_inbound_data_beats_ccm5 local_socket_inf0_outbound_data_beats_ccm6 Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 2 remote_socket_inf1_inbound_data_beats_ccm5 event=0x41e,umask=0xbff Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 5 Retired x87 floating-point ops of all types Retired packed 512-bit floating-point ops fp_ops_retired_by_type.vector_add Retired vector floating-point add ops Retired SSE and AVX integer logical ops event=0xc,umask=0x05 Retired 128-bit packed floating-point convert ops fp_pack_ops_retired.fp128_shuffle fp_pack_ops_retired.fp256_cmp Retired 128-bit packed integer logical ops event=0xd,umask=0x70 Number of PRECHARGE commands sent l1_demand_data_cache_fills_from_near_cache DRAM write data for remote processor local_socket_upstream_dma_write_data Local socket outbound data from the CPU (e.g. write data) Total cache hits FR_DISPATCH_STALL_FOR_SEGMENT_LOAD MEM_WRITE EVENT_03H EVENT_19H EVENT_84H EVENT_96H EVENT_CBH EVENT_F0H EVENT_F6H EVENT_FFH MAIN_TLB_MISS_STALL DATA_EVICTION L2D_CACHE_REFILL EVENT_119H EVENT_12AH EVENT_140H EVENT_168H EVENT_1ABH EVENT_1B3H EVENT_1B7H EVENT_1C4H EVENT_1F8H EVENT_22BH EVENT_239H EVENT_23CH EVENT_243H EVENT_280H EVENT_28EH EVENT_29BH EVENT_2BFH EVENT_2C7H EVENT_319H EVENT_357H EVENT_36FH EVENT_395H EVENT_3CDH EVENT_3FDH LDREX_SPEC ASE_SPEC LL_CACHE_RD hni_wdb_occ_cnt_ovfl sbsx_rd_req rnd_s0_rdata_beats cxha_wdb_occ clkdiv2_high_qos_depth COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD L2_INSTR_CACHE_MISSES BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT LSU_EMPTY CYCLES_IN_SUPER DCACHE_MISS_COMPLETION_STALL FXU_LONG_INSTR_COMPLETION_STALL FINISHED_UNCOND_BRANCHES_MISS_BTB CYCLES_SU1_SCHED_STALLED LOADS_TRANSLATED STORES_TRANSLATED DATA_L1_CACHE_LOCKS STORE_TRANSLATE_WHEN_QUEUE_FULL LOAD_MISS_DLFB_FULL_CYCLES LOAD_MISS_LDQ_FULL_CYCLES x87 probe-hit data ARMV8 pmclog_read pme->table[idx].name %s
ldlat %s, "pmcid": "0x%08x", "pid": "%d", "base": "0x%016jx", "dyn": "0x%016jx", "pathname": "%s"}
Per-Logical Processor actual clocks when the Logical Processor is active ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) Number of Instructions per non-speculative Branch Misprediction (JEClear) InsType IpStore Measured Average Frequency for unhalted processors [GHz] l2_rqsts.demand_data_rd_hit This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted l2_trans.l2_fill mem_load_uops_retired.l1_miss This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source Supports address when precise (Precise event) Retired load uops that split across a cacheline boundary.(Precise Event - PEBS) Supports address when precise (Precise event) Uops delivered to Instruction Decode Queue (IDQ) from MITE path Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy hle_retired.aborted tx_exec.misc4 tx_mem.abort_hle_elision_buffer_mismatch Speculative and retired direct near calls br_inst_exec.all_indirect_jump_non_call_ret br_inst_exec.all_indirect_near_return Taken speculative and retired indirect branches with return mnemonic All (macro) branch instructions retired Conditional branch instructions retired. (Precise Event - PEBS) (Precise event) event=0x89,period=200003,umask=0x41 This event counts not taken speculative and retired mispredicted macro conditional branch instructions event=0x89,period=200003,umask=0x88 br_misp_retired.all_branches_pebs This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise) cpu_clk_unhalted.thread_p_any This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use Number of machine clears (nukes) of any type uops_executed.core_cycles_ge_1 event=0xa1,any=1,period=2000003,umask=0x2 event=0xe,period=2000003,umask=0x10 llc_misses.code_llc_prefetch event=0x21,umask=0x4 Shared line response from remote cache. Unit: uncore_ha write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc (UNC_M_POWER_SELF_REFRESH / UNC_M_DCLOCKTICKS) * 100. Pre-charge for writes. Unit: uncore_imc event=0x80,occ_sel=1 Counts the number of cycles when current is the upper limit on frequency. Unit: uncore_pcu Load miss in all TLB levels causes a page walk that completes. (1G) Spec update: BDM69 This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault Spec update: BDM69 dtlb_store_misses.walk_completed_2m_4m Cycle count for an Extended Page table walk event=0xbc,period=2000003,umask=0x14 page_walker_loads.itlb_l3 IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) ) MEM_Request_Latency offcore_response.all_data_rd.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0240 offcore_response.all_pf_code_rd.l3_hit.snoop_not_needed offcore_response.all_rfo.any_response offcore_response.all_rfo.l3_hit.snoop_hit_no_fwd offcore_response.all_rfo.supplier_none.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020008 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020001 offcore_response.other.any_response offcore_response.other.l3_hit.any_snoop offcore_response.other.supplier_none.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0020 offcore_response.pf_l3_code_rd.l3_hit.snoop_not_needed offcore_response.pf_l3_code_rd.supplier_none.snoop_miss offcore_response.pf_l3_rfo.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0100 offcore_response.pf_l3_rfo.supplier_none.snoop_hitm offcore_response.pf_l3_rfo.supplier_none.snoop_miss Randomly selected loads with latency value being above 16 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 4 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) Randomly selected loads with latency value being above 512 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000091 offcore_response.all_pf_code_rd.l3_miss.snoop_none offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hitm offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000090 offcore_response.all_pf_data_rd.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000122 offcore_response.all_rfo.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000008 offcore_response.demand_data_rd.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204008000 offcore_response.pf_l2_code_rd.l3_miss.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000040 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000040 offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hitm unc_cbo_cache_lookup.write_mesi unc_arb_trk_requests.all Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC007F7 offcore_response.pf_llc_rfo.llc_miss.any_response event=0x28,period=200000,umask=0x41 l2_ld.self.any.m_state event=0x2b,period=200000,umask=0x42 l2_rqsts.self.prefetch.m_state l2_st.self.s_state Retired loads that hit the L2 cache (precise event) Retired loads that miss the L2 cache fp_assist.s simd_assist event=0xb3,period=2000000,umask=0x2 Store splits event=0x61,period=200000,umask=0x20 event=0x6f,period=200000,umask=0xe0 event=0x6b,period=200000,umask=0xe0 Explicit writeback bus transactions ext_snoop.all_agents.hit ext_snoop.this_agent.hitm Retired branch instructions that were predicted taken Mispredicted and taken cond branch instructions retired event=0x8,period=200000,umask=0x6 event=0x82,period=200000,umask=0x1 Number of I-Side page walks L1 Cache evictions for dirty data Load uops retired that hit L2 (Precise event capable) Supports address when precise (Must be precise) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400008000 offcore_response.corewb.l2_hit Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000008 offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwd event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000001 Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required offcore_response.partial_streaming_stores.l2_hit event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000044000 offcore_response.pf_l2_data_rd.l2_hit offcore_response.streaming_stores.l2_miss.any Counts the number of floating point divide uops retired (Must be precise) BACLEARs asserted for any branch type event=0x13,period=200003,umask=0x4 Cycles code-fetch stalled due to any reason br_inst_retired.call Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition) (Must be precise) Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist (Must be precise) ITLB misses Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.corewb.outstanding Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000020 Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received event=0x85,period=2000003,umask=0x2 Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3 Retired load uops missed L1 cache as data sources Supports address when precise. Spec update: HSM30 (Precise event) Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61, HSM63 This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis Spec update: HSD135 Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled Spec update: HSD135 Cycles with less than 2 uops delivered by the front end Spec update: HSD135 Randomly selected loads with latency value being above 16 Supports address when precise. Spec update: HSD76, HSD25, HSM26 (Must be precise) offcore_response.demand_data_rd.l3_miss.any_response Number of ITLB page walker hits in the L3 + XSNP Spec update: HSD25 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400091 l2_lines_out.dirty_all Core-originated cacheable demand requests that refer to LLC Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400244 Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) event=0x34,umask=0x06 mem_load_uops_llc_miss_retired.remote_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0010 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc00004 LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox Counts the number of times that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu Cycles spent changing Frequency. Unit: uncore_pcu freq_ge_2000mhz_cycles % Counts the number of times that the uncore transitioned to a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu event=0xd,edge=1,filter_band2=30 Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu jkt metrics event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC20077 offcore_response.all_demand_mlc_pref_reads.llc_miss.remote_hitm_hit_forward Resource stalls out of order resources full This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses l2_requests_reject.all offcore_response.any_code_rd.any_response offcore_response.any_code_rd.l2_hit_this_tile_s offcore_response.any_data_rd.l2_hit_near_tile Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x18001832f7 Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state offcore_response.any_request.l2_hit_near_tile_m Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.any_rfo.l2_hit_this_tile_e Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000080 offcore_response.pf_l1_data_rd.l2_hit_far_tile_m Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800081000 Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008001000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000200 Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600044 offcore_response.any_request.mcdram_far Counts any request that accounts for data responses from MCDRAM Local event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800004 Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.pf_l1_data_rd.mcdram_near offcore_response.pf_l2_code_rd.ddr_far Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local Counts the number of mispredicted near RET branch instructions retired (Precise event) Counts the number of unhalted core clock cycles Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted Cycles L1D locked L2 data demand loads in M state All L2 data prefetches event=0x26,period=200000,umask=0x20 event=0xf2,period=100000,umask=0x1 l2_rqsts.ifetches event=0x24,period=200000,umask=0x20 event=0x24,period=200000,umask=0xc event=0x27,period=100000,umask=0xf0 Memory instructions retired above 256 clocks (Precise Event) event=0xb7,period=100000,umask=0x1,offcore_rsp=0x844 All offcore requests event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4722 offcore_response.any_rfo.remote_cache_dram Offcore RFO requests satisfied by a remote cache or remote DRAM Offcore writebacks to the LLC or local DRAM Offcore code or data read requests satisfied by the LLC and HIT in a sibling core offcore_response.data_ifetch.llc_hit_other_core_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8033 Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x703 Offcore demand data reads satisfied by any cache or DRAM Offcore demand data reads satisfied by the LLC and not found in a sibling core Offcore demand data reads satisfied by the LLC and HIT in a sibling core offcore_response.demand_data_rd.remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x102 Offcore other requests satisfied by the LLC and not found in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x480 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4780 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F30 Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core Offcore prefetch data requests satisfied by a remote cache offcore_response.pf_data_rd.local_cache Offcore prefetch data reads satisfied by the LLC Offcore prefetch code reads satisfied by the LLC or local DRAM offcore_response.pf_ifetch.remote_cache_hitm offcore_response.pf_rfo.any_cache_dram offcore_response.pf_rfo.io_csr_mmio offcore_response.prefetch.local_cache event=0x10,period=2000000,umask=0x8 SSE* FP double precision Uops SSE FP scalar Uops Offcore writebacks that missed the LLC offcore_response.data_ifetch.local_dram offcore_response.demand_data.local_dram Offcore other requests that missed the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4010 es_reg_renames event=0x88,period=20000,umask=0x8 Mispredicted call branches executed event=0xd2,period=2000000,umask=0x8 ssex_uops_retired.packed_double SIMD Scalar-Single Uops retired (Precise Event) event=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3f uops_executed.core_stall_cycles_no_port5 Uops executed on port 4 (core count) event=0xc2,period=2000000,umask=0x2 Total cycles using precise uop retired event (Precise Event) dtlb_load_misses.pde_miss event=0x49,period=200000,umask=0x10 Counts L2 cache hits when fetching instructions, code reads Core-originated cacheable demand requests missed L3 Spec update: SKL057 Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS offcore_response.demand_code_rd.l3_hit_e.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040004 offcore_response.demand_data_rd.l3_hit.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080001 offcore_response.demand_data_rd.l3_hit_e.spl_hit offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C8000 offcore_response.other.l3_hit_m.snoop_hit_no_fwd offcore_response.other.l3_hit_s.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80108000 frontend_retired.any_dsb_miss Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C400001 offcore_response.demand_rfo.l3_hit_e.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104008000 rob_misc_events.pause_inst event=0xc2,cmask=16,inv=1,period=2000003,umask=0x2 Mem;MemoryBW;Offcore_SMT L1MPKI_Load Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB) Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault mem_uops_retired.utlb_miss offcore_response.any_code_rd.l2_miss.hit_other_core_no_fwd Counts any data read (demand & prefetch) that have any response type event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200008008 Counts writeback (modified to exclusive) that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080000008 Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise event) Counts the number of taken JCC branch instructions retired (Precise event) Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted Duration of I-side page-walks in core cycles This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0120 Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all demand & prefetch prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0020 REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400010 offcore_requests_outstanding.demand.rfo REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f44 offcore_response.data_ifetch.local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f03 offcore_response.demand_data_rd.local_dram_and_remote_cache_hit REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff50 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff40 offcore_response.any_ifetch.other_local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf8ff event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3022 offcore_response.data_in.other_local_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3003 REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM offcore_response.pf_rfo.other_local_dram DTLB miss page walk cycles event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2710 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5810 mem_uncore_retired.local_dram_and_remote_cache_hit offcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwd OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element offcore_response.all_data_rd.l3_miss.remote_hitm offcore_response.all_pf_data_rd.l3_miss.any_snoop offcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800002 Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly Fraction of Core cycles where the core was running with power-delivery for license level 1. SMT version; use when SMT is enabled and measuring per logical CPU CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.THREAD Write Pending Queue Allocations. Unit: uncore_imc unc_cha_core_snp.core_gtone event=0x33,umask=0x82 Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed unc_cha_snoop_resp.rspifwd event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x04 Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Read request for up to a 64 byte transaction is made by the CPU to IIO Part0. Unit: uncore_iio Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2. Unit: uncore_iio event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x04 Read request for up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Write request of up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio uncore_irp unc_m2m_direct2upi_not_taken_credits event=0x2e,umask=0x2 event=0x2e,umask=0x10 Reads to iMC issued at Normal Priority (Non-Isochronous). Unit: uncore_m2m unc_m2m_imc_writes.all Writes to iMC issued. Unit: uncore_m2m M2M Writes Issued to iMC; All, regardless of priority Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory Prefetches generated by the flow control queue of the M3UPI unit. Unit: uncore_m3upi Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA unc_upi_txl0p_power_cycles Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080491 OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080491 OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP ocr.all_data_rd.l3_hit_s.snoop_miss OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100490 OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002007F7 ocr.all_rfo.l3_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200122 ocr.demand_code_rd.l3_hit_f.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200004 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD ocr.demand_code_rd.l3_hit_s.hitm_other_core ocr.demand_data_rd.l3_hit.any_snoop Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD ocr.demand_data_rd.l3_hit_s.hit_other_core_no_fwd ocr.demand_rfo.l3_hit_e.hit_other_core_no_fwd ocr.demand_rfo.l3_hit_e.no_snoop_needed ocr.demand_rfo.l3_hit_s.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800108000 ocr.pf_l1d_and_sw.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080400 ocr.pf_l1d_and_sw.l3_hit_e.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080020 ocr.pf_l2_rfo.l3_hit_f.hitm_other_core Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040020 ocr.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_hit_s.any_snoop ocr.pf_l3_rfo.l3_hit.hit_other_core_no_fwd ocr.pf_l3_rfo.l3_hit_e.snoop_none Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.l3_hit_s.any_snoop offcore_response.all_data_rd.l3_hit_f.snoop_none This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_f.snoop_miss offcore_response.all_pf_data_rd.l3_hit_m.snoop_miss This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.all_pf_rfo.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020120 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS offcore_response.all_reads.l3_hit_e.hitm_other_core offcore_response.all_reads.l3_hit_m.hit_other_core_no_fwd offcore_response.all_reads.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP offcore_response.demand_code_rd.l3_hit.hit_other_core_fwd offcore_response.demand_code_rd.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED offcore_response.demand_code_rd.pmm_hit_local_pmm.any_snoop offcore_response.demand_data_rd.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD offcore_response.other.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020010 offcore_response.pf_l2_rfo.l3_hit_f.snoop_none offcore_response.pf_l2_rfo.l3_hit_m.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.l3_hit_s.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP offcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l3_rfo.supplier_none.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020100 Intel AVX-512 computational 128-bit packed BFloat16 instructions retired Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction. Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000490 OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000120 ocr.all_reads.l3_miss.hit_other_core_no_fwd OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.all_reads.l3_miss_remote_hop1_dram.any_snoop ocr.all_reads.l3_miss_remote_hop1_dram.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000004 ocr.demand_data_rd.l3_miss_local_dram.snoop_miss ocr.demand_rfo.l3_miss.remote_hitm ocr.other.l3_miss.snoop_miss ocr.other.l3_miss_local_dram.snoop_none Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x110008000 ocr.pf_l2_data_rd.l3_miss.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000100 offcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP offcore_response.demand_code_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.l3_miss.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.pf_l2_rfo.l3_miss.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.all_data_rd.supplier_none.no_snoop_needed ocr.all_pf_data_rd.supplier_none.hit_other_core_fwd OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD ocr.all_pf_data_rd.supplier_none.snoop_miss ocr.all_pf_rfo.pmm_hit_local_pmm.snoop_none OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS ocr.all_reads.supplier_none.hit_other_core_fwd ocr.all_rfo.supplier_none.hit_other_core_no_fwd ocr.demand_code_rd.supplier_none.no_snoop_needed Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE ocr.other.supplier_none.hit_other_core_fwd Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED ocr.pf_l1d_and_sw.supplier_none.no_snoop_needed ocr.pf_l2_data_rd.supplier_none.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED ocr.pf_l3_data_rd.supplier_none.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD Intel Optane DC persistent memory read latency (ns). Unit: uncore_imc All hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc unc_cha_tor_occupancy.ia_miss_drd event=0x38,umask=0x20 Write requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data ocr.hwpf_l2_data_rd.l3_hit.any event=0x32,period=100003,umask=0x4 Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events event=0xc6,period=100007,umask=0x1,frontend=0x502006 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event) Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt) event=0x5d,period=100003,umask=0x2 tx_mem.abort_capacity_read Counts the number of times a TSX line had a cache conflict Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch ocr.demand_code_rd.local_dram ocr.demand_rfo.local_dram ocr.streaming_wr.any_response ocr.streaming_wr.local_dram Number of instructions retired. General Counter - architectural event (Precise event) Number of uops executed on port 1 Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) Cycles when at least one PMH is busy with a page walk for a store tgl metrics Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core ocr.demand_data_rd.pmm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x700800001 ocr.reads_to_core.local_pmm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000477 event=0x82 PMM Commands : Underfill reads. Unit: uncore_imc event=0x37,umask=0x0F event=0x35,umask=0xC807FD01 TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_hit TOR Inserts : ItoMs issued by IO Devices that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_rfo_pref_remote event=0x36,umask=0xC8178A01 unc_iio_data_req_of_cpu.mem_write.part7 unc_iio_data_req_of_cpu.cmpd.part6 unc_iio_txn_req_by_cpu.mem_write.part6 unc_iio_txn_req_of_cpu.cmpd.part4 PCIe Completion Buffer Occupancy of completions with data : Part 6. Unit: uncore_iio event=0x10,umask=0x40 Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache Counts the number of load uops retired that hit in the L1 data cache Supports address when precise (Precise event) ocr.demand_data_and_l1pf_rd.l3_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004003C0000 event=0x71,period=1000003,umask=0x20 Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3002184000000 ocr.l1wb_m.l3_miss This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) ocr.uc_rd.any_response Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired (Precise event) Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready (Precise event) topdown_bad_speculation.monuke topdown_be_bound.alloc_restrictions event=0x71,period=1000003,umask=0x40 Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts TOR Inserts : All requests from iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Inserts : DRd_Opts issued by iA Cores. Unit: uncore_cha TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC. Unit: uncore_cha event=0x36,umask=0xC8A7FD01 Clockticks of the integrated IO (IIO) traffic controller PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault ept.epde_hit 64 * LONGEST_LAT_CACHE.MISS / 1000000000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2104000002 Average external Memory Bandwidth Use for reads and writes [GB / sec]. Unit: cpu_core Uops Per Instruction. Unit: cpu_atom 100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL Percentage of all uops which are FPDiv uops. Unit: cpu_atom Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2 cache. Unit: cpu_atom Counts the number of load ops retired that hit in DRAM Supports address when precise (Precise event). Unit: cpu_atom Counts the number of load uops retired Supports address when precise (Precise event). Unit: cpu_atom event=0x43,period=1000003,umask=0xfd Completed demand load uops that miss the L1 d-cache. Unit: cpu_core decode.lcp event=0x79,cmask=6,period=2000003,umask=0x8 Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Unit: cpu_core event=0x73,period=1000003 This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE. Unit: cpu_core event=0xec,cmask=1,edge=1,period=2000003,umask=0x40 Number of all retired NOP instructions. Unit: cpu_core int_misc.unknown_branch_cycles int_vec_retired.256bit Counts cycles where the pipeline is stalled due to serializing operations. Unit: cpu_core event=0xc2,cmask=1,period=1000003,umask=0x2 unc_m_vc0_requests_rd event=0x12,period=100003,umask=0x8 Counts hardware prefetches (which bring data to L2) that have any type of response amx_ops_retired.int8 INST_RETIRED.MACRO_FUSED Precise instruction retired with PEBS precise-distribution (Precise event) TOPDOWN.MEMORY_BOUND_SLOTS Number of uops dispatch to execution port 6 IMC Clockticks at DCLK frequency. Unit: uncore_imc PMM Read Pending Queue occupancy. Unit: uncore_imc event=0x3,umask=0x0000000020 event=0xe0,umask=0x0000000010 event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000002 TOR Occupancy for DRd misses from local IA targeting local memory. Unit: uncore_cha Valid Flits Sent : Data. Unit: uncore_upi Valid Flits Received : Slot 1. Unit: uncore_upi event=0x4,umask=0x000000010f unc_upi_txl_inserts event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000004 event=0xc0,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000001 event=0x1c,umask=0x03 unc_m2m_tracker_inserts.ch0 unc_m3upi_cms_clockticks TOR Inserts; Hits from Local IA. Unit: uncore_cha event=0x35,umask=0x00ccc7fe01 event=0x35,umask=0x00c001fd04 TOR Inserts : IRQ - iA. Unit: uncore_cha unc_cha_tor_inserts.remote_tgt unc_cha_tor_inserts.isoc event=0x35,umask=0x00c897fd01 event=0x36,umask=0x00C000FF04 event=0x36,umask=0x00c803ff04 event=0x35,umask=0x00c837ff01 event=0x35,umask=0x00C86F0A01 unc_cha_tor_inserts.ia_miss_wcil_ddr unc_cha_tor_occupancy.ia_miss_wil unc_cha_tor_occupancy.ia_miss_remote_wcilf_ddr event=0x36,umask=0x00cd43fd04 ic_cache_fill_sys bp_l1_tlb_miss_l2_hit bp_tlb_rel All L2 Cache Requests (Breakdown 1 - Common). Data cache stores event=0x60,umask=0x20 l2_request_g1.l2_hw_pf All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized event=0x61,umask=0x08 l2_cache_req_stat.ic_access_in_l2 l2_fill_pending.l2_fill_busy ex_ret_mmx_fp_instr.x87_instr ex_ret_fus_brnch_inst dram_channel_data_controller_2 event=0,umask=0xf0 The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Ops fp_ret_sse_avx_ops.dp_add_sub_flops x87 bottom-executing uOps retired event=0x29,umask=0x01 ls_mab_alloc.stores L1 DTLB Reload of a page of 1G size ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable d_ratio(ex_ret_brn_misp, ex_ret_brn) event=0x60,umask=0xc8 L2 Cache Misses from L1 Instruction Cache Misses event=0xe,umask=0x0e Add/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 ls_pref_instr_disp.prefetch_w Ops dispatched from either the decoders, OpCache or both Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP ops The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (2M page size) Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2. Modifiable L2 prefetcher misses in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches ex_ret_fused_instr Demand Data Cache Fills by Data Source. From DRAM or IO connected in same node ls_any_fills_from_sys.ext_cache_remote ls_misal_loads.ma64 Core to L2 cache requests (not including L2 prefetch) for instruction cache access l2_pf_miss_l2_l3.l1_region Instruction cache hits l3_xi_sampled_latency_requests.all Interrupts taken Write data beats (64 bytes) for local processor at Coherent Station (CS) 0 event=0x8df,umask=0x7ff local_socket_inf0_inbound_data_beats_ccm1 Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 0 Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 1 local_socket_inf0_outbound_data_beats_ccm7 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 0 event=0x49f,umask=0xbfe event=0x55f,umask=0xbfe remote_socket_inf0_outbound_data_beats_ccm6 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 1 Retired SSE and AVX floating-point multiply ops fp_retired_ser_ops.all Retired scalar floating-point ops event=0xa,umask=0x01 event=0xa,umask=0x60 fp_ops_retired_by_type.vector_all Retired MMX integer multiply ops of other types Retired SSE and AVX integer compare ops sse_avx_ops_retired.sse_avx_other sse_avx_ops_retired.all Retired 128-bit packed floating-point square root ops event=0xd,umask=0x03 Number of clocks used by the data bus for writes L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages smt_contention d_ratio(ex_ret_ops, total_dispatch_slots) retiring Fraction of dispatch slots that remained unused because of stalls not related to the memory subsystem retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops)) L2 cache misses from L1 data cache misses L1 data cache fills from another CCX cache in any NUMA node 1MB/s Memory controller ACTIVATE command rate BUS_ACCESS INSTRUCTIONS_ISSUED_CYCLE CYCLES_STALLED_NEON_FULLQ EVENT_02H EVENT_13H EVENT_2BH EVENT_4AH EVENT_D6H EVENT_F7H DATA_MICRO_TLB_MISS_STALL EVENT_11BH EVENT_11CH EVENT_126H EVENT_150H EVENT_15FH EVENT_16CH EVENT_181H EVENT_183H EVENT_1A2H EVENT_1BAH EVENT_205H EVENT_223H EVENT_248H EVENT_26CH EVENT_282H EVENT_285H EVENT_29DH EVENT_2E1H EVENT_30BH EVENT_317H EVENT_35BH EVENT_35DH EVENT_38DH EVENT_3ACH EVENT_3BDH EVENT_3BFH EVENT_3C9H EVENT_3D2H EVENT_3FEH ISB_SPEC dn_rxreq_vivi_dvmop hnf_snp_sent rnd_s2_rdata_beats clkdiv2_waiting_for_wr_data LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0 LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL REFETCH_SERIALIZATION SECOND_SPECULATION_BUFFER_ACTIVE SUCCESSFUL_STWCX L2_CACHE_MISSES MARKED_STORE_SENT_TO_STS LSU_MARKED_INSTR_FINISH LOADS_TRANSLATED_ALLOCATED_TO_DLFB DATA_MMU_MISS_CYCLES INSTR_MMU_TLB4K_RELOADS EXT_INPUT_INTR_PENDING_LATENCY_CYCLES PMC0_OVERFLOW INTV_ALLOCATIONS L2_CACHE_DIRTY_REDUNDANT_UPDATES L2_INCOHERENT_LINE_INVALIDATIONS IAC2S_DETECTED DAC1S_DTECTED count= add-pipe-excluding-junk-ops locked-instructions PRECISE UCF INTEL_ATOM_GOLDMONT_P SS topic: %s
{"type": "pmcallocatedyn" {"type": "thr_exit" v19 GenuineIntel-6-[4589]E GenuineIntel-6-37 AuthenticAMD-23-[012][0-9A-F] AuthenticAMD-25-[[:xdigit:]]+ This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU CLKS Ret;SMT;TmaL1 Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting Bad;BrMispredicts Instructions per Load (lower number means higher occurrence rate) Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate) l2_rqsts.all_pf l2_rqsts.l2_pf_miss mem_load_uops_retired.l3_hit This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path Supports address when precise. Spec update: BDM35 (Precise event) event=0xca,period=100003,umask=0x10 Number of SIMD Move Elimination candidate uops that were eliminated Number of transitions from SSE to AVX-256 when penalty applicable Spec update: BDM30 event=0x80,period=2000003,umask=0x4 event=0x79,period=2000003,umask=0x8 event=0x79,period=2000003,umask=0x2 event=0x9c,cmask=1,inv=1,period=2000003,umask=0x1 This is a precise version (that is, uses PEBS) of the event that counts return instructions retired (Precise event) event=0x89,period=200003,umask=0xc4 Not taken speculative and retired mispredicted macro conditional branches This event counts all mispredicted macro branch instructions retired Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache Cycles 4 Uops delivered by the LSD, but didn't come from the decoder Resource-related stall cycles event=0xb1,period=2000003,umask=0x1 uops_executed_port.port_4 Cycles without actually retired uops All LLC Misses (code+ data rd + data wr - including demand and prefetch). Unit: uncore_cbox ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox write requests to local home agent. Unit: uncore_ha (UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * 100. This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G) Spec update: BDM69 event=0x8,period=2000003,umask=0x2 ept.walk_cycles itlb.itlb_flush offcore_response.all_data_rd.supplier_none.snoop_hitm offcore_response.all_pf_rfo.supplier_none.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0122 offcore_response.corewb.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C8000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020040 offcore_response.pf_l2_data_rd.l3_hit.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010020 offcore_response.pf_l3_code_rd.supplier_none.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020080 offcore_response.pf_l3_data_rd.supplier_none.snoop_hit_no_fwd Counts randomly selected loads with latency value being above 256 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) offcore_response.all_data_rd.l3_miss.snoop_none offcore_response.all_data_rd.l3_miss_local_dram.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000090 offcore_response.all_rfo.l3_miss_local_dram.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000008 offcore_response.corewb.l3_miss_local_dram.snoop_not_needed offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000020 offcore_response.pf_l3_code_rd.l3_miss.snoop_miss offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_miss offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_none offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000100 A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core event=0x34,umask=0x81 L3 Lookup any request that access cache and found line in E or S-state offcore_response.pf_llc_code_rd.llc_miss.any_response l2_ifetch.self.e_state l2_ld.self.any.s_state l2_ld.self.prefetch.mesi l2_reject_busq.self.prefetch.m_state l2_rqsts.self.any.s_state event=0x2e,period=200000,umask=0x48 l2_rqsts.self.prefetch.e_state event=0x77,period=200000,umask=0x2 event=0xe4,period=2000000,umask=0x1 Bogus branches br_missp_type_retired.return event=0x14,period=2000000,umask=0x1 event=0x13,period=2000000,umask=0x81 event=0x8,period=200000,umask=0xa ITLB hits page_walks.d_side_walks Number of D-side only page walks core_reject_l2q.all mem_load_uops_retired.dram_hit Counts the number of load uops retired Supports address when precise (Must be precise) Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks Supports address when precise (Must be precise) offcore_response.any_pf_data_rd.l2_miss.hit_other_core_no_fwd Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010400 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000001 offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_needed Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600001000 Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Instructions retired (Precise event capable) (Must be precise) Unfilled issue slots per cycle Counts anytime a load that retires is blocked for any reason (Must be precise) Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress Counts data reads (demand & prefetch) hit the L2 cache event=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000003091 Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010008 Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault event=0x49,period=2000003,umask=0x4 Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks offcore_response.pf_l3_code_rd.l3_hit.any_response Counts cycles DSB is delivered at least one uops. Set Cmask = 1 Speculative cache-line split store-address uops dispatched to L1D event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400244 offcore_response.all_rfo.l3_miss.local_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00004 offcore_response.demand_rfo.l3_miss.any_response This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end Cycles which a uop is dispatched on port 0 in this thread event=0x34,umask=0x4f An external snoop hits a modified line in some processor core An external snoop misses in some processor core Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G) Number of ITLB page walker hits in the L2 event=0xbc,period=2000003,umask=0x28 offcore_response.pf_l2_rfo.llc_miss.any_response l2_l1d_wb_rqsts.hit_m event=0x27,period=200003,umask=0x1 mem_load_uops_llc_miss_retired.local_dram Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall Count XClk pulses when this thread is unhalted and the other is halted Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) event=0x22,umask=0x02 Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests event=0x8,period=2000003,umask=0x84 Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc20002 llc_references.pcie_ns_write QPI clock ticks. Use to get percentages for QPI cycles events. Unit: uncore_qpi event=0xb,edge=1,filter_band0=12 l1d.all_m_replacement Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement Mispredicted taken branch instructions retired (Precise event) partial_rat_stalls.flags_merge_uop partial_rat_stalls.mul_single_uop Uops dispatched from any thread This event counts the number of micro-ops retired (Precise event) unc_m_act_count event=0x4,umask=0xc Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses l2_requests.miss event=0x4,period=200003,umask=0x80 mem_uops_retired.hitm event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400044 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080044 offcore_response.any_data_rd.l2_hit_this_tile_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00020032f7 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800408000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800188000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008008000 Counts Demand cacheable data write requests that accounts for any response offcore_response.any_rfo.l2_hit_this_tile_s Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000002 offcore_response.pf_l1_data_rd.l2_hit_far_tile offcore_response.pf_l2_code_rd.l2_hit_near_tile_e_f Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.pf_l2_rfo.l2_hit_far_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080020 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state offcore_response.pf_l2_rfo.l2_hit_this_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002001000 Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end offcore_response.any_code_rd.mcdram_near event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400070 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x01818032f7 Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800002 Counts the number of far branch instructions retired (Precise event) Counts the number of mispredicted far branch instructions retired (Precise event) Counts the number of mispredicted near relative CALL branch instructions retired (Precise event) This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider event=0xca,period=200003,umask=0x20 recycleq.ld_block_st_forward recycleq.ld_splits event=0xcb,period=200003,umask=0x1f 6.4e-05MiB event=0x43,period=2000000,umask=0x2 L1 data cache read in I state (misses) L1 data cache load locks in S state L1 data cache stores in E state event=0x26,period=200000,umask=0x8 l2_lines_out.any l2_rqsts.ld_miss l2_rqsts.prefetch_hit L2 fill transactions event=0xf0,period=200000,umask=0x40 event=0x27,period=100000,umask=0x8 L2 demand store RFOs in M state mem_inst_retired.latency_above_threshold_1024 event=0xb,period=3,umask=0x10,ldlat=0x8000 Offcore data reads satisfied by the LLC event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1011 Offcore code reads satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8044 offcore_response.any_rfo.local_cache_dram offcore_response.any_rfo.remote_cache_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x108 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x808 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x177 offcore_response.demand_data.remote_cache Offcore demand code reads satisfied by any cache or DRAM offcore_response.demand_ifetch.io_csr_mmio Offcore other requests satisfied by any cache or DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x210 Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x740 Offcore prefetch code reads satisfied by a remote cache Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM offcore_response.prefetch.llc_hit_no_other_core simd_int_64.shuffle_move offcore_response.any_data.any_dram Offcore code reads satisfied by any DRAM Offcore code or data read requests satisfied by a remote DRAM Offcore demand code reads that missed the LLC Offcore demand code reads satisfied by a remote DRAM Offcore prefetch requests satisfied by the local DRAM L1I instruction fetch misses event=0xf6,period=2000000,umask=0x1 Late Branch Prediction Unit clears event=0x88,period=20000,umask=0x10 event=0x89,period=20000,umask=0x7 event=0x89,period=2000,umask=0x8 Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) resource_stalls.other event=0xc7,period=200000,umask=0x4 event=0xc7,period=200000,umask=0x10 event=0xb1,any=1,cmask=1,period=2000000,umask=0x1f Cycles no Uops issued on ports 0, 1 or 5 Uops issued on ports 2, 3 or 4 event=0xe,period=2000000,umask=0x2 dtlb_misses.stlb_hit BACLEAR asserted, regardless of cause Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch Retired load instructions with L1 cache hits as data sources Supports address when precise (Precise event) offcore_response.demand_code_rd.supplier_none.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080001 offcore_response.demand_data_rd.l3_hit_e.snoop_not_needed offcore_response.demand_rfo.l3_hit_e.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40080002 offcore_response.demand_rfo.l3_hit_m.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200088000 offcore_response.other.l3_hit_s.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200028000 frontend_retired.latency_ge_128 Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops Cycles with less than 3 uops delivered by the front-end offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd offcore_response.demand_code_rd.l3_miss.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4000004 offcore_response.demand_data_rd.l3_hit_s.snoop_non_dram offcore_response.demand_rfo.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204008000 event=0x14,cmask=1,period=2000003,umask=0x1 Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16) Spec update: SKL091, SKL044 (Must be precise) Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS Counts any data read (demand & prefetch) that miss L2 offcore_response.any_data_rd.l2_miss.snoop_miss Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received Instruction fetches from Icache NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event) Counts all prefetch RFOs that hit in the LLC Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400080 Mispredicted not taken branch instructions retired.(Precise Event - PEBS) (Precise event) REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4ff REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf877 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2050 REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM offcore_response.pf_ifetch.other_local_dram Snoop code requests Cycles snoop code requests queued dtlb_misses.pde_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0001 OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd Counts all prefetch (that bring data to L2) RFOs that hit in the L3 offcore_response.all_pf_data_rd.l3_miss.snoop_miss_or_no_fwd Counts all demand & prefetch RFOs that miss in the L3 Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00004 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwd offcore_response.demand_data_rd.l3_miss.remote_hit_forward offcore_response.demand_rfo.l3_miss.remote_hitm Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00020 core_power.lvl0_turbo_license ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD ) Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX) Power_License2_Utilization Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command event=0x35,umask=0x21,config1=0x41a33 event=0x2,umask=0xf unc_iio_data_req_of_cpu.mem_read.part3 Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels Rsp*WB Snoop Responses Received. Unit: uncore_cha event=0xd5,fc_mask=0x04,umask=0x0f PCIe Completion Buffer occupancy of completions with data: Part 1 PCIe Completion Buffer occupancy of completions with data: Part 2. Unit: uncore_iio Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_write.part0 Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Write request of up to a 64 byte transaction is made by IIO Part1 to Memory. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state event=0x3,umask=0x27 Idle FLITs transmitted. Unit: uncore_upi event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040491 ocr.all_pf_data_rd.l3_hit.hitm_other_core OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED ocr.all_pf_rfo.l3_hit_e.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080120 OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS ocr.all_pf_rfo.l3_hit_s.no_snoop_needed OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000807F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800807F7 ocr.all_reads.l3_hit_f.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4002007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000407F7 OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801007F7 ocr.all_rfo.l3_hit.snoop_miss ocr.demand_code_rd.l3_hit_f.snoop_none Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040001 ocr.demand_rfo.l3_hit.hit_other_core_no_fwd ocr.demand_rfo.l3_hit.snoop_miss ocr.demand_rfo.l3_hit_e.snoop_miss Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE ocr.other.l3_hit_e.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100400 Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200010 ocr.pf_l2_data_rd.l3_hit_f.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200010 ocr.pf_l2_data_rd.l3_hit_m.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040010 ocr.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD ocr.pf_l2_rfo.l3_hit_m.snoop_miss Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd offcore_response.all_data_rd.l3_hit_e.snoop_miss This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED offcore_response.all_reads.l3_hit_f.snoop_none This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP offcore_response.all_rfo.l3_hit_m.any_snoop This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_hit.no_snoop_needed This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED offcore_response.pf_l1d_and_sw.l3_hit_m.snoop_none offcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_fwd offcore_response.pf_l2_data_rd.l3_hit_s.snoop_none offcore_response.pf_l2_rfo.l3_hit_e.hitm_other_core offcore_response.pf_l2_rfo.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020080 This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS event=0xcf,period=2000003,umask=0x80 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000490 OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD ocr.all_pf_data_rd.l3_miss_local_dram.snoop_none ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_needed OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_miss OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISS ocr.all_reads.l3_miss.snoop_none ocr.all_reads.l3_miss_local_dram.snoop_miss OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1100007F7 OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000001 Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000002 Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000100 offcore_response.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.all_pf_rfo.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD offcore_response.all_reads.l3_miss_remote_hop1_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.all_rfo.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE offcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS offcore_response.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS offcore_response.other.l3_miss_local_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_miss offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_core offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_fwd offcore_response.pf_l3_data_rd.l3_miss.hit_other_core_no_fwd offcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.all_pf_data_rd.supplier_none.snoop_none OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED ocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_none ocr.pf_l3_data_rd.supplier_none.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD event=0xe4,umask=0x1 Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified Counts all microcode Floating Point assists Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle Fraction of Physical Core issue-slots utilized by this Logical Processor Fraction of branches of other types (not individually covered by other metrics in Info.Branches group) Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache ocr.streaming_wr.l3_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00800 Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes Counts mispredicted conditional branch instructions retired (Precise event) event=0xa8,cmask=5,period=2000003,umask=0x1 Counts the number of machine clears (nukes) of any type uops_dispatched.port_1 Counts cycles when at least 1 micro-op is executed from any thread on physical core Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80082380 ocr.reads_to_core.l3_miss_local_socket Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache event=0xef,period=1000003,umask=0x4 Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x730000001 Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket unc_m_tagchk.nm_rd_hit event=0xd3,umask=0x08 event=0x2,umask=0x08 PMM Write Queue Inserts. Unit: uncore_imc TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC. Unit: uncore_cha TOR Inserts : ItoMs issued by IO Devices. Unit: uncore_cha TOR Occupancy : RFOs issued by iA Cores. Unit: uncore_cha event=0x35,umask=0xCD43FD04 unc_cha_tor_inserts.ia_miss_drd_pmm unc_iio_data_req_of_cpu.mem_read.part5 unc_iio_data_req_of_cpu.mem_read.part7 event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x04 unc_iio_txn_req_by_cpu.mem_read.part7 unc_iio_txn_req_of_cpu.mem_read.part4 unc_iio_txn_req_of_cpu.cmpd.part5 event=0xc2,ch_mask=0xff,fc_mask=0x04,umask=0x03 Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) Counts the total number of store uops retired Supports address when precise (Precise event) Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_with_fwd This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache ocr.hwpf_l2_code_rd.l3_hit.snoop_hitm Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000044 Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache ocr.hwpf_l2_code_rd.l3_miss_local event=0xb7,period=100003,umask=0x1,offcore_rsp=0x402184000000 Counts uncached memory writes that were not supplied by the L3 cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING Counts uncached memory reads that were supplied by DRAM Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1 Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear event=0x73,period=1000003,umask=0x2 Counts the total number of DRAM CAS commands issued on this channel PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault Total pipeline cost of branch related instructions (used for program control-flow including function calls). Unit: cpu_core Cycles Per Instruction (per Logical Processor). Unit: cpu_core Instructions Per Cycle across hyper-threads (per physical core). Unit: cpu_core Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor). Unit: cpu_core L2 cache misses per kilo instruction for all demand loads (including speculative). Unit: cpu_core Cycles Per Instruction for the Operating System (OS) Kernel mode. Unit: cpu_core Percent of instruction miss cost that hit in the L3. Unit: cpu_atom load ops retired per 1000 instruction. Unit: cpu_atom All retired load instructions Supports address when precise (Precise event). Unit: cpu_core Cycles MITE is delivering any Uop. Unit: cpu_core Execution stalls while L3 cache miss demand load is outstanding. Unit: cpu_core Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Unit: cpu_atom This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL (Precise event). Unit: cpu_atom Counts the number of issue slots not consumed due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing uops from the UROM until a specified older uop retires. Unit: cpu_atom arith.fp_divider_active event=0xe7,period=1000003,umask=0xac int_vec_retired.add_256 event=0x3,period=100003,umask=0x82 event=0xb2,period=2000003,umask=0x80 Any Rank at Hot state. Unit: uncore_imc uncore_clock event=0x11,period=100003,umask=0x4 OFFCORE_REQUESTS_OUTSTANDING.DATA_RD frontend_retired.ms_flows Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10070 XQ.FULL_CYCLES Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch (Precise event) MISC2_RETIRED.LFENCE This event is deprecated. Refer to new event UOPS_RETIRED.STALLS Precharge due to read on page miss. Unit: uncore_imc event=0x35,umask=0x00c8f3ff04 Valid Flits Received : Idle. Unit: uncore_upi unc_upi_rxl_inserts.slot0 RxQ Flit Buffer Bypassed : Slot 0. Unit: uncore_upi event=0x31,umask=0x0000000004 event=0x40 event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000004 event=0xc1,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000001 event=0x16,umask=0x07 Tracker Inserts : Channel 0. Unit: uncore_m2m TOR Inserts; Hits from local IO. Unit: uncore_cha unc_cha_tor_inserts.match_opc TOR Inserts : Just ISOC. Unit: uncore_cha TOR Inserts; DRd Opt misses from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_crd_pref unc_cha_tor_inserts.ia_itom unc_cha_tor_occupancy.ia_hit_rfo event=0x36,umask=0x00c001fe04 TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_crd_pref unc_cha_tor_inserts.ia_miss_drdpte event=0x35,umask=0x00ccd7fd01 TOR Inserts; LLCPrefData from local IA. Unit: uncore_cha TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely. Unit: uncore_cha TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0x00c8170601 unc_cha_tor_occupancy.ia_miss_remote_wcilf_pmm unc_cha_tor_occupancy.ia_miss_wcilf_ddr event=0x36,umask=0x00c8670601 unc_cha_tor_occupancy.ia_miss_local_wcil_ddr bp_l1_tlb_fetch_hit event=0x60,umask=0x01 LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests event=0x64,umask=0x07 Caching: L3 cache accesses. Unit: amd_l3 event=0xd1 The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0 fp_retx87_fp_ops.add_sub_ops fp_num_mov_elim_scal_op.opt_potential fp_retired_ser_ops.x87_bot_ret Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type ls_dispatch.ld_st_dispatch L1 DTLB Miss of a page of 1G size event=0x45,umask=0x40 event=0x45,umask=0x10 event=0x28a,umask=0x01 de_dis_dispatch_token_stalls0.alsq3_0_token_stall l2_cache_accesses_from_l2_hwpf l2_cache_misses_from_ic_miss l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2 event=0x25,umask=0x08 event=0x25,umask=0x02 Software Prefetch Data Cache Fills by Data Source. From another cache (home node local) Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination register The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit (4K or 16K page size) op_cache_hit_miss.op_cache_miss All L3 Request Types. All L3 cache Requests. Unit: amd_l3 L3 Misses by Request Type. Ignores SliceID, EnAllSlices, CoreID, EnAllCores and ThreadMask. Requires unit mask 0xFF to engage event for counting. Unit: amd_l3 Counts the number of SMIs received Any Data Cache Fills by Data Source. From DRAM or IO connected in different Node l3_cache_accesses bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX ls_hw_pf_dc_fills.far_cache L2 cache requests: data cache reads including hardware and software prefetch l2_pf_hit_l2.l1_stream event=0x1f,umask=0x7fe local_processor_read_data_beats_cs5 local_processor_read_data_beats_cs9 local_processor_write_data_beats_cs2 Write data beats (64 bytes) for local processor at Coherent Station (CS) 4 event=0x15f,umask=0x7ff local_processor_write_data_beats_cs11 Read data beats (64 bytes) for remote processor at Coherent Station (CS) 0 event=0xdf,umask=0xbfe event=0x25f,umask=0xbfe remote_processor_write_data_beats_cs10 Read data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2 remote_socket_upstream_read_beats_iom1 event=0x59f,umask=0x7fe event=0x5df,umask=0x7fe Data beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 0 event=0x49e,umask=0x7ff Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 1 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 6 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 5 event=0x5de,umask=0xbff event=0x59f,umask=0xbff event=0xd1f,umask=0xf3e fp_ops_retired_by_width.pack_256_uops_retired Retired vector floating-point compare ops event=0xa,umask=0x80 fp_ops_retired_by_type.vector_shuffle event=0xb,umask=0x60 fp_pack_ops_retired.fp128_sqrt Retired 128-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) Retired 128-bit packed integer CLM ops packed_int_op_type.int128_all Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages Instruction fetches that hit in the L1 ITLB for 1G pages Pipeline restarts not caused by branch mispredicts Number of cycles dispatch is stalled for floating-point flush recovery Fraction of dispatch slots that remained unused because the other thread was selected L2 cache misses from L1 instruction cache misses Macro-ops retired DRAM read data for local processor remote_processor_write_data_beats_cs0 + remote_processor_write_data_beats_cs1 + remote_processor_write_data_beats_cs2 + remote_processor_write_data_beats_cs3 + remote_processor_write_data_beats_cs4 + remote_processor_write_data_beats_cs5 + remote_processor_write_data_beats_cs6 + remote_processor_write_data_beats_cs7 + remote_processor_write_data_beats_cs8 + remote_processor_write_data_beats_cs9 + remote_processor_write_data_beats_cs10 + remote_processor_write_data_beats_cs11 remote_socket_upstream_dma_read_data local_socket_outbound_data_from_cpu hisi_sccl,l3c DC_MISS IC_FETCH INSTR_EXECUTED CYCLES_NO_INSTRUCTION EVENT_04H EVENT_22H EVENT_27H EVENT_3FH EVENT_CAH EVENT_D2H EVENT_E0H INSTR_RENAMED BUS_ACCESS_ST EXC_FIQ EVENT_137H EVENT_14FH EVENT_159H EVENT_17EH EVENT_18EH EVENT_1B5H EVENT_1CAH EVENT_1D9H EVENT_1DAH EVENT_1E9H EVENT_1EEH EVENT_206H EVENT_225H EVENT_24DH EVENT_261H EVENT_26BH EVENT_27AH EVENT_34DH EVENT_34FH EVENT_379H EVENT_37DH EVENT_38FH EVENT_399H EVENT_3ABH EVENT_3CFH LL_CACHE_MISS_RD dn_rxreq_dvmsync rnd_txreq_flits_total rni_s0_wdata_beats rni_wrt_alloc cxha_reqtrk_occ cxla_avg_rx_tlp_sz_dws clkdiv2_read_backlog MFVSCR_SYNC_CYCLES CYCLES_NO_COMPLETED_INSTRS L1_DATA_CYCLES_USED BPU_STALL_ON_LR_DEPENDENCY FPU_INSTR_COMPLETED CYCLES_THREE_INSTR_COMPLETED SNOOP_RETRIES SRQ_EMPTY FXU_COMPLETION_STALL BIU_MASTER_REQUESTS BIU_MASTER_RETRIES L2_HIT_CACHE_ACCESSES L2_CACHE_INSTR_ACCESSES inv scrubber read-to-write-turnaround k8-bu-cpu-clk-unhalted DMC620_PMU_CD2 INTEL_HASWELL ARMV8_CORTEX_A57 LONGEST_LAT_CACHE.MISS %s, "pmcid": "0x%08x", "pid": "%d", "value": "0x%016jx"}
%s, "pid": "%d", "flags": "0x%08x", "pcomm": "%s"}
GenuineIntel-6-26 GenuineIntel-6-3E AuthenticAMD-25-[0245][[:xdigit:]] Pipeline Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) Mem;MemoryBW;SoC cbox_0@event\=0x0@ C3 residency percent per core event=0x48,cmask=1,period=2000003,umask=0x1 event=0x48,any=1,cmask=1,period=2000003,umask=0x1 Requests from L2 hardware prefetchers l2_rqsts.miss L2 writebacks that access L2 cache This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source Supports address when precise (Precise event) event=0xd1,period=100003,umask=0x8 mem_uops_retired.all_stores Retired load uops with locked access. (Precise Event - PEBS) Supports address when precise. Spec update: BDM35 (Precise event) offcore_requests_outstanding.all_data_rd event=0xb7,period=100003,umask=0x1 Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end event=0x79,cmask=1,period=2000003,umask=0x30 Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ rtm_retired.aborted This event counts both taken and not taken speculative and retired direct near calls event=0x88,period=200003,umask=0xc4 Taken speculative and retired indirect calls br_inst_retired.near_taken br_misp_exec.all_conditional Reference cycles when the core is not in halt state event=0,any=1,period=2000003,umask=0x2 Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache event=0xd,period=2000003,umask=0x8 event=0xa1,period=2000003,umask=0x1 event=0xa1,period=2000003,umask=0x4 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7 Counts the number of uops to be executed per-thread each cycle Cycles per core when uops are dispatched to port 7 uops_retired.retire_slots PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox unc_h_requests.reads_remote unc_m_pre_count.wr Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size Spec update: BDM69 This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault Spec update: BDM69 This event counts the number of cycles while PMH is busy with the page walk Spec update: BDM69 dtlb_store_misses.stlb_hit_4k Number of ITLB page walker hits in the L3 + XSNP Spec update: BDM69, BDM98 Retired load uops with L2 cache hits as data sources Supports address when precise. Spec update: BDM35 (Precise event) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020240 offcore_response.all_pf_rfo.supplier_none.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020122 offcore_response.corewb.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0040 Counts prefetch (that bring data to LLC only) code reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000008 offcore_response.demand_code_rd.l3_hit.snoop_non_dram offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hitm offcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss offcore_response.demand_rfo.l3_hit.snoop_non_dram offcore_response.demand_rfo.l3_miss.snoop_none offcore_response.other.l3_miss_local_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000040 offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoop offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000100 This event counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) L3 Lookup read request that access cache and found line in E or S-state. Unit: uncore_cbox Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic Number of Core coherent Data Read entries allocated in DirectData mode. Unit: uncore_arb Retired load uop whose Data Source was: Remote cache HITM Supports address when precise. Spec update: BDE70 (Precise event) event=0x40,period=2000000,umask=0x83 l1d_cache.replm L1 Cacheable Data Writes l2_ld.self.demand.e_state l2_ld_ifetch.self.i_state l2_lines_out.self.any event=0x26,period=200000,umask=0x50 L2 locked accesses event=0x2b,period=200000,umask=0x4f event=0x30,period=200000,umask=0x7f event=0x30,period=200000,umask=0x51 l2_rqsts.self.any.e_state event=0xce,period=2000000,umask=0x0 Retired Streaming SIMD Extensions 2 (SSE2) vector instructions misalign_mem_ref.ld_bubble event=0x7,period=200000,umask=0x81 bus_io_wait.self bus_lock_clocks.all_agents event=0xc8,period=200000,umask=0x0 Branch instructions decoded Retired branch instructions that were mispredicted not-taken br_missp_type_retired.cond br_missp_type_retired.ind event=0xc0,period=2000000,umask=0x0 data_tlb_misses.l0_dtlb_miss_st event=0xd0,period=200003,umask=0x41 offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwd offcore_response.any_read.l2_miss.hit_other_core_no_fwd Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000002 offcore_response.full_streaming_stores.l2_miss.any event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000800 Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation Retired instructions of near indirect Jmp or call (Precise event capable) (Must be precise) br_inst_retired.return event=0xcd,period=200003,umask=0x1 issue_slots_not_consumed.recovery issue_slots_not_consumed.resource_full Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available (Must be precise) Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010002 Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Page walks outstanding due to a demand data store every cycle event=0x85,period=2000003,umask=0x8 Retired load uops which data sources were hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles Spec update: HSD62, HSD61, HSM63 Counts all prefetch (that bring data to L2) RFOs hit in the L3 Number of times an HLE execution successfully committed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00001 Counts demand data reads miss the L3 and the data is returned from local dram offcore_response.pf_l3_code_rd.l3_miss.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00200 This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling loads blocked by overlapping with store buffer that cannot be forwarded False dependencies in MOB due to partial compare on address unc_cbo_cache_lookup.write_i DTLB demand load misses with low part of linear-to-physical address translation missed This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks DTLB store misses with low part of linear-to-physical address translation missed Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00040 Demand data read requests sent to uncore Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles offcore_response.all_rfo.llc_hit.any_response Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts non-temporal stores offcore_response.demand_data_rd.llc_miss.dram LLC lookup request that access cache and found line in E-state or S-state Misses in all TLB levels that cause a page walk of any page size from demand loads Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded) offcore_response.all_pf_data_rd.llc_hit.hitm_other_core Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23ffc08000 Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all demand code reads that miss the LLC and the data returned from local dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800001 Counts demand data reads that miss the LLC and the data returned from remote dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20200 txl0p_power_cycles % unc_q_txl_flits_g0.non_data freq_band3_cycles % event=0x60 (UNC_P_FREQ_GE_4000MHZ_CYCLES / UNC_P_CLOCKTICKS) * 100. Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu This event counts the number of store uops retired (Precise event) event=0xac,period=2000003,umask=0x2 event=0x59,cmask=1,period=2000003,umask=0x20 Cycles per core when load or STA uops are dispatched to port 2 Counts the number of L2 cache misses Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x18004032f7 Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state Counts any request that accounts for responses which hit its own tile's L2 with data in F state Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.demand_data_rd.l2_hit_near_tile_m offcore_response.demand_rfo.l2_hit_far_tile Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400080 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800082000 offcore_response.pf_l1_data_rd.l2_hit_this_tile_e offcore_response.pf_l2_code_rd.l2_hit_far_tile_e_f offcore_response.pf_l2_rfo.supplier_none Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode offcore_response.uc_code_reads.l2_hit_near_tile offcore_response.uc_code_reads.l2_hit_this_tile_s uops_retired.packed_simd offcore_response.any_code_rd.ddr Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far) offcore_response.any_rfo.ddr Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200022 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800400 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800400 offcore_response.demand_rfo.ddr offcore_response.partial_writes.ddr_far Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken (Precise event) Fixed Counter: Counts the number of unhalted reference clock cycles event=0xca,period=200003,umask=0x4 Counts any retired store that was pushed into the recycle queue for any reason Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once Supports address when precise (Precise event) ddr bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_imc Counts the number of load micro-ops retired that cause a DTLB miss Supports address when precise (Precise event) l1d.m_evict event=0x53,period=2000000,umask=0x1 L1D hardware prefetch requests triggered event=0xf1,period=100000,umask=0x2 All L2 prefetches L1D writeback to L2 transactions Longest latency cache miss mem_inst_retired.latency_above_threshold_128 event=0xb,period=20000,umask=0x10,ldlat=0x8 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8011 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF22 offcore_response.corewb.llc_hit_no_other_core offcore_response.corewb.local_cache Offcore code or data read requests satisfied by the LLC Offcore code or data read requests satisfied by the LLC or local DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1033 Offcore demand data reads satisfied by the IO, CSR, MMIO unit Offcore demand data reads satisfied by a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F04 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4704 offcore_response.demand_ifetch.remote_cache_hit offcore_response.other.any_location offcore_response.other.local_cache Offcore other requests satisfied by a remote cache or remote DRAM offcore_response.pf_ifetch.remote_cache Offcore prefetch code reads satisfied by a remote cache or remote DRAM Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core Offcore prefetch requests satisfied by a remote cache event=0xcc,period=2000000,umask=0x1 Transitions from MMX to Floating Point instructions event=0x12,period=200000,umask=0x10 SIMD integer 64 bit unpack operations Two Uop instructions decoded offcore_response.any_ifetch.any_llc_miss offcore_response.any_request.any_llc_miss Offcore code or data read requests satisfied by any DRAM Offcore demand data reads satisfied by the local DRAM offcore_response.demand_data_rd.remote_dram Offcore demand RFO requests satisfied by the local DRAM offcore_response.pf_ifetch.any_llc_miss event=0x80,period=2000000,umask=0x4 event=0x13,period=2000000,umask=0x7 BACLEAR asserted, regardless of cause event=0xc3,period=20000,umask=0x2 event=0xa2,period=2000000,umask=0x8 ssex_uops_retired.packed_single Uops executed on ports 0-4 (core count) uops_executed.core_stall_cycles event=0xdb,period=2000000,umask=0x1 event=0x85,period=200000,umask=0x2 Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc. event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C0004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40080004 offcore_response.demand_code_rd.l3_hit_s.snoop_not_needed offcore_response.demand_code_rd.l4_hit_local_l4.snoop_miss offcore_response.demand_code_rd.l4_hit_local_l4.spl_hit offcore_response.demand_data_rd.l3_hit_s.spl_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0400001 offcore_response.demand_data_rd.l4_hit_local_l4.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40020001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x40400002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020002 offcore_response.other.l3_hit.spl_hit Retired Instructions who experienced a critical DSB miss (Precise event) Retired Instructions who experienced Instruction L1 Cache true miss (Precise event) event=0xc6,period=100007,umask=0x1,frontend=0x400106 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event) Number of times an HLE execution aborted due to unfriendly events (such as interrupts) Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles Supports address when precise (Must be precise) offcore_response.demand_code_rd.l4_hit_local_l4.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC400001 offcore_response.demand_rfo.l3_miss.snoop_non_dram offcore_response.demand_rfo.l3_miss.spl_hit offcore_response.demand_rfo.l3_miss_local_dram.snoop_not_needed offcore_response.other.l3_miss.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C408000 arith.divider_active This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired Spec update: SKL091 (Must be precise) event=0x3c,any=1,period=25003,umask=0x1 event=0xa3,cmask=20,period=2000003,umask=0x14 Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two) Spec update: SKL091, SKL044 Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS) Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread Fraction of branches that are non-taken conditionals (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT ) Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB) Instruction fetch requests that miss the ITLB and hit the STLB This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims) L2 cache requests from this core This event counts the number of store ops retired offcore_response.pf_l2_code_rd.l2_miss.snoop_miss The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle Total cycles for all the page walks. (I-side and D-side) This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS) (Precise event) offcore_response.all_code_rd.llc_hit.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0244 Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0200 offcore_response.any_ifetch.all_local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f22 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff08 offcore_response.pf_data.all_local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff10 REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS offcore_response.any_rfo.any_dram_and_remote_fwd REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2722 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5877 offcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwd Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0400 Counts all prefetch (that bring data to LLC only) data reads that have any response type offcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwd OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD Counts all demand code reads that miss the L3 and the data is returned from remote dram Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800080 Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule idi_misc.wb_downgrade ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). SMT version; use when SMT is enabled and measuring per logical CPU LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha upi_data_bandwidth_tx unc_cha_hitme_hit.ex_rds unc_cha_llc_victims.total_m event=0x3d,umask=0x01 unc_iio_data_req_of_cpu.peer_read.part2 event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x08 unc_iio_data_req_of_cpu.peer_write.part2 unc_iio_txn_req_by_cpu.peer_read.part2 event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x08 unc_iio_txn_req_by_cpu.peer_write.part3 unc_iio_txn_req_of_cpu.peer_write.part2 Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy unc_m2m_directory_update.a2s unc_m2m_directory_update.i2s unc_m2m_imc_reads.all unc_upi_clockticks Protocol header and credit FLITs received from any slot. Unit: uncore_upi Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode. Unit: uncore_upi OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200491 OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080490 ocr.all_pf_rfo.l3_hit.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100120 OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE ocr.all_reads.l3_hit_f.hitm_other_core OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE ocr.all_reads.l3_hit_s.no_snoop_needed OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040122 OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0002 ocr.other.l3_hit_e.snoop_miss Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200208000 ocr.other.l3_hit_m.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80108000 Counts L1 data cache hardware prefetch requests and software prefetch requests Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwd ocr.pf_l1d_and_sw.l3_hit_m.snoop_miss Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP ocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE ocr.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwd ocr.pf_l2_rfo.l3_hit_f.snoop_none Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100080 ocr.pf_l3_rfo.l3_hit_m.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100100 offcore_response.all_data_rd.l3_hit_f.any_snoop This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE offcore_response.all_pf_rfo.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED offcore_response.all_reads.l3_hit_f.no_snoop_needed This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004007F7 offcore_response.all_rfo.pmm_hit_local_pmm.snoop_none offcore_response.demand_code_rd.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.demand_data_rd.l3_hit_m.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.demand_rfo.l3_hit.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.l3_hit.snoop_none This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS offcore_response.pf_l1d_and_sw.l3_hit_f.hitm_other_core offcore_response.pf_l1d_and_sw.l3_hit_m.hitm_other_core offcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.pf_l2_data_rd.l3_hit_f.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020020 offcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD offcore_response.pf_l3_rfo.l3_hit_m.snoop_none This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x840007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8100007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000122 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD ocr.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD ocr.other.l3_miss.hit_other_core_fwd ocr.other.l3_miss_remote_hop1_dram.hitm_other_core Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.pf_l2_data_rd.l3_miss.hit_other_core_no_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000010 ocr.pf_l2_rfo.l3_miss_local_dram.snoop_none ocr.pf_l3_rfo.l3_miss.hitm_other_core event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000100 ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoop Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED offcore_response.all_reads.l3_miss_local_dram.snoop_none offcore_response.all_rfo.l3_miss_remote_hop1_dram.any_snoop offcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwd offcore_response.demand_code_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED offcore_response.pf_l2_data_rd.l3_miss_local_dram.no_snoop_needed This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS offcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_miss.hit_other_core_no_fwd ocr.all_data_rd.pmm_hit_local_pmm.snoop_none ocr.all_data_rd.supplier_none.hit_other_core_fwd ocr.all_reads.supplier_none.no_snoop_needed ocr.all_rfo.pmm_hit_local_pmm.snoop_not_needed ocr.demand_code_rd.supplier_none.snoop_none Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD ocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_needed Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD ocr.pf_l3_rfo.supplier_none.no_snoop_needed TOR Inserts : DRds issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0004 Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0010 Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent Store Read transactions pending for off-core. Highly correlated Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element event=0xc6,period=100007,umask=0x1,frontend=0x508006 event=0xa3,cmask=6,period=1000003,umask=0x6 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00400 ocr.hwpf_l2_rfo.l3_miss Counts the number of times an RTM execution aborted due to incompatible memory type event=0x54,period=100003,umask=0x4 Counts hardware prefetch data reads (which bring data to L2) that have any type of response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000020 br_inst_retired.cond_taken Taken conditional branch instructions retired (Precise event) br_misp_retired.cond Number of instructions retired. Fixed Counter - architectural event (Precise event) Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event) Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use TBD Supports address when precise (Precise event) SMT;TmaL1 Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket ocr.reads_to_core.l3_hit.snoop_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0477 For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache event=0xef,period=1000003,umask=0x10 Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster event=0xd3,umask=0x04 event=0x83 DRAM Activate Count : All Activates. Unit: uncore_imc PMM Write Pending Queue Occupancy. Unit: uncore_imc Local write requests that miss the SF/LLC and are sent to the CHA's home agent. Unit: uncore_cha event=0x35,umask=0xC001FD04 event=0x36,umask=0xC001FF01 event=0x36,umask=0xC80FFE01 event=0x35,umask=0xC807FF01 unc_cha_tor_inserts.ia_crd event=0x36,umask=0xC817FF01 TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha unc_iio_txn_req_of_cpu.mem_write.part6 PCIe Completion Buffer Occupancy of completions with data : Part 4. Unit: uncore_iio event=0x12,umask=0x78 event=0x2,umask=0x0F mem_bound_stalls.load_l2_hit ocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_no_fwd ocr.hwpf_l2_code_rd.l3_hit.snoop_hit_no_fwd bus_lock.block_cycles bus_lock.lock_cycles Counts all code reads that were supplied by DRAM ocr.l1wb_m.any_response Counts the total number of mispredicted branch instructions retired for all branch types (Precise event) event=0x74,period=1000003,umask=0x1 topdown_be_bound.store_buffer topdown_fe_bound.decode event=0x71,period=1000003,umask=0x10 TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed). Unit: cpu_core TOPDOWN_BAD_SPECULATION.ALL / (5 * CPU_CLK_UNHALTED.CORE) Instruction per (near) call (lower number means higher occurrence rate). Unit: cpu_atom CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSC TBD. Unit: cpu_core Retired store instructions that split across a cacheline boundary Supports address when precise (Precise event). Unit: cpu_core event=0x21,period=100003,umask=0x80 event=0xb3,period=2000003,umask=0x1 Counts the number of instruction cache misses. Unit: cpu_atom event=0xc6,period=100007,umask=0x1,frontend=0x600206 Cycles DSB is delivering optimal number of Uops. Unit: cpu_core Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled. Unit: cpu_core Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk when load subsequently retires. Unit: cpu_atom Counts demand data reads that were not supplied by the L3 cache. Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke). Unit: cpu_atom Counts the total number of uops retired (Precise event). Unit: cpu_atom Cycles total of 2 uops are executed on all ports and Reservation Station was not empty. Unit: cpu_core event=0xe7,period=1000003,umask=0x10 event=0xb2,period=2000003,umask=0x2 unc_m_act_count_rd event=0x12,cmask=1,period=100003,umask=0x10 event=0x12,period=100003,umask=0x2 Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity event=0x2a,period=100003,umask=0x1,offcore_rsp=0x733004477 CPU_CLK_UNHALTED.PAUSE Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions INT_VEC_RETIRED.VNNI_256 Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of specualtive operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction DRAM underfill read CAS commands issued. Unit: uncore_imc event=0x3,umask=0x0000000088 event=0xe0,umask=0x0000000008 unc_m_pre_count.rd_pch0 event=0xe0,umask=0x0000000020 event=0x35,umask=0x00cd43ff04 event=0x2,umask=0x0000000080 unc_upi_rxl_flits.slot2 unc_upi_rxl_occupancy.slot1 Tx Flit Buffer Allocations. Unit: uncore_upi Read request for 4 bytes made by IIO Part0 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000004 event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000001 event=0xc1,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000001 event=0xc1,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000004 event=0xc2,ch_mask=0x10,fc_mask=0x07,umask=0x0000000004 Tracker Inserts : Channel 1. Unit: uncore_m2m unc_cha_tor_inserts.io_miss_rfo event=0x35,umask=0x0000000001 unc_cha_tor_inserts.prq_iosf TOR Inserts : PRQ - IOSF. Unit: uncore_cha TOR Inserts; RFO from local IO. Unit: uncore_cha TOR Occupancy; All from local IA. Unit: uncore_cha TOR Occupancy; LLCPrefRFO misses from local IA. Unit: uncore_cha TOR Occupancy; All from local IO. Unit: uncore_cha TOR Occupancy : All from Remote. Unit: uncore_cha TOR Occupancy; DRd Pref hits from local IA. Unit: uncore_cha TOR Occupancy; DRd Opt Pref misses from local IA. Unit: uncore_cha TOR Occupancy; RFO prefetch from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_local unc_cha_tor_occupancy.ia_miss_drd_pref_remote event=0x35,umask=0x00cd43fd04 unc_cha_tor_inserts.ia_miss_crd_pref_local event=0x35,umask=0x00C877DE01 unc_cha_tor_inserts.ia_wcilf event=0x35,umask=0x00C86FFE01 unc_cha_tor_occupancy.ia_miss_drd_pref_remote_pmm TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha TOR Inserts : DDR Access. Unit: uncore_cha l2_request_g1.rd_blk_x l2_request_g2.bus_locks_originator event=0x64,umask=0x20 l2_cache_req_stat.ls_rd_blk_c event=0x64,umask=0x04 l2_cache_req_stat.ic_fill_miss l2_pf_miss_l2_l3 L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches event=0x6,umask=0xfe The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX) The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions Tagged IBS Ops. Number of Ops tagged by IBS that retired event=0x47,umask=0x38 dram_channel_data_controller_7 event=0,umask=0x10 fp_retx87_fp_ops.mul_ops event=0x3,umask=0x10 Double precision add/subtract FLOPS Number of SSE Move Ops eliminated ls_dispatch.ld_dispatch The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss Total Page Table Walks IC Type 0 Total Page Table Walks DC Type 1 event=0x4b,umask=0x02 L2 Cache Accesses from L2 HWPF L2 Cache Hits from L2 HWPF bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss Retired lock instructions. Non-speculative lock succeeded A non-cacheable store and the non-cacheable commit buffer is full ls_tlb_flush de_dis_dispatch_token_stalls1.int_phy_reg_file_token_stall All Op Cache accesses. Counts Op Cache micro-tag hit/miss events The number of CPUID instructions retired ls_hw_pf_dc_fills.ext_cache_remote event=0xab,umask=0x04 de_dis_dispatch_token_stalls2.agsq_token_stall Cycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 1 available l1_data_cache_fills_from_remote_node Demand data cache fills from cache of another CCX when the address was in a different NUMA node ls_any_fills_from_sys.local_l2 Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX Hardware prefetch data cache fills from all types of data sources Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2 Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2 Core to L2 cache requests (not including L2 prefetch) for data cache hits Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2NextLine (fetch the next line into L2 cache) L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2NextLine (fetch the next line into L2 cache) event=0x72,umask=0x10 L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous) l3_xi_sampled_latency.dram_far event=0xd6,umask=0x08 event=0xd6,umask=0x10 event=0xd6,umask=0x1b event=0x1df,umask=0x7fe remote_processor_read_data_beats_cs11 event=0x15f,umask=0xbff remote_socket_upstream_read_beats_iom2 local_socket_inf0_inbound_data_beats_ccm4 event=0x41e,umask=0x7ff Data beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 0 remote_socket_inf1_inbound_data_beats_ccm2 Data beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 3 Retired SSE and AVX floating-point ops of all types event=0xa,umask=0x02 event=0xa,umask=0xb0 event=0xb,umask=0x0e sse_avx_ops_retired.sse_avx_mac event=0xb,umask=0xd0 fp_pack_ops_retired.fp128_cmp event=0xc,umask=0x0e event=0xc,umask=0x20 Retired 256-bit packed floating-point ops of other types packed_int_op_type.int128_add packed_int_op_type.int128_shuffle Retired 256-bit packed integer ops of all types Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store) event=0xaa,umask=0x07 Fraction of dispatch slots that remained unused because of backend stalls L3 misses (including cacheline state change requests) Mixed SSE/AVX stalls local_socket_upstream_write_beats_iom0 + local_socket_upstream_write_beats_iom1 + local_socket_upstream_write_beats_iom2 + local_socket_upstream_write_beats_iom3 hisi_sccl,ddrc BU_INTERNAL_L2_REQUEST PC_BRANCH_PRED MEM_ACCESS AXI_READ OPS_ISSUED EVENT_17H EVENT_1BH EVENT_32H EVENT_36H EVENT_71H EVENT_D4H SECOND_EXECUTION_UNIT_PIPE PLD_STALL DATA_MAIN_TLB_MISS_STALL EVENT_146H EVENT_15CH EVENT_185H EVENT_186H EVENT_191H EVENT_1BDH EVENT_1C3H EVENT_1C7H EVENT_1EBH EVENT_209H EVENT_22CH EVENT_240H EVENT_25DH EVENT_2C9H EVENT_2D0H EVENT_2F9H EVENT_345H EVENT_34BH EVENT_34CH EVENT_359H EVENT_39CH EVENT_3F2H EVENT_3F6H L1D_CACHE_WB_CLEAN L2D_CACHE_LD rnd_rrt_alloc rni_rrt_occ_ovfl cxha_rddatbyp cxha_snphaz_occ clkdiv2_medium_qos_depth clkdiv2_rdwr clk_cycle_count SPEC_BUFFER_CYCLES BRANCH_UNIT_STALL_CYCLES DATA_BKPT_MATCHES DTLB_MISSES L3_CACHE_HITS FXU0_IDLE_FXU1_BUSY LSU_COMPLETION_STALL INSTR_FETCHED CQ_REDIRECTS INSTR_L1_CACHE_RELOADS L2_CACHE_INSTR_ALLOCATIONS L2_CACHE_CLEAN_UPDATES L2_CACHE_LOCKS L2_CLEAN_LINE_INVALIDATIONS DAC2S_DTECTED TSC- add-pipe-junk-ops ss POWER8 BR_MISP_RETIRED.ALL_BRANCHES unrecognized kvpair: %s:%s
%s, "pmcid": "0x%08x", "pid": "%d", "tid": "%d", "cpuflags": "0x%08x", "cpuflags2": "0x%08x", "pc": [ GenuineIntel-6-2E This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU CoreIPC Ret;Flops Ret;Flops_SMT Actual per-core usage of the Floating Point execution units (regardless of the vector width) Instructions per (near) call (lower number means higher occurrence rate) INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache) Mem;Backend;CacheMisses C7_Pkg_Residency This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace event=0xf1,period=100003,umask=0x1 event=0x24,period=200003,umask=0x50 event=0xd2,period=20011,umask=0x1 This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type This event counts both cacheable and noncachaeble code read requests sq_misc.split_lock This event counts the number of split locks in the super queue fp_assist.x87_output dsb2mite_switches.penalty_cycles event=0x9c,cmask=1,period=2000003,umask=0x1 Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts) This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:
1. memory disambiguation,
2. external snoop, or
3. cross SMT-HW-thread snoop (stores) hitting load buffer Number of times an RTM execution aborted due to HLE-unfriendly instructions event=0x5d,period=2000003,umask=0x4 tx_exec.misc5 cpl_cycles.ring0_trans event=0x88,period=200003,umask=0x84 event=0xc4,period=400009,umask=0x1 Direct and indirect near call instructions retired. (Precise Event - PEBS) (Precise event) This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event) event=0x89,period=200003,umask=0xff Thread cycles when thread is not in halt state cycle_activity.cycles_l2_miss cycle_activity.stalls_ldm_pending Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke) lsd.cycles_4_uops This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end uops_executed_port.port_0_core uops_executed_port.port_1 uops_executed_port.port_2_core PCU clock ticks. Use to get percentages of PCU cycles events. Unit: uncore_pcu Cycles when PMH is busy with page walks Spec update: BDM69 Store misses in all DTLB levels that cause page walks Spec update: BDM69 Code miss in all TLB levels causes a page walk that completes. (2M/4M) Spec update: BDM69 event=0x85,period=100003,umask=0x10 This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache Supports address when precise. Spec update: BDM100 (Precise event) This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) This event counts retired load uops which data sources were hits in the mid-level (L2) cache Supports address when precise. Spec update: BDM35 (Precise event) offcore_response.all_data_rd.l3_hit.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010120 offcore_response.all_pf_rfo.l3_hit.any_snoop offcore_response.all_pf_rfo.supplier_none.any_snoop offcore_response.all_rfo.l3_hit.snoop_hitm offcore_response.all_rfo.l3_hit.snoop_not_needed Counts writebacks (modified to exclusive) have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0004 offcore_response.demand_rfo.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C8000 offcore_response.pf_l2_code_rd.l3_hit.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010080 Counts all prefetch (that bring data to LLC only) data reads have any response type event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000091 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0122 offcore_response.all_rfo.l3_miss_local_dram.snoop_hit_no_fwd offcore_response.corewb.l3_miss_local_dram.snoop_miss offcore_response.demand_data_rd.l3_miss_local_dram.snoop_non_dram offcore_response.other.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020020 offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_non_dram This event counts both direct and indirect near call instructions retired (Precise event) uncore_ncu Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd Counts all requests hit in the L3 offcore_response.all_reads.llc_miss.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x06040007F7 Counts prefetch (that bring data to LLC only) code reads miss in the L3 l2_ld.self.any.e_state event=0x29,period=200000,umask=0x44 l2_reject_busq.self.any.i_state l2_reject_busq.self.any.m_state event=0x2e,period=200000,umask=0x44 simd_sat_instr_retired Decode stall due to IQ full event=0x80,period=200000,umask=0x2 event=0xa9,cmask=1,period=2000000,umask=0x1 event=0x7,period=200000,umask=0x82 bus_hitm_drv.all_agents event=0x7a,period=200000,umask=0x20 event=0x60,period=200000,umask=0x40 event=0x70,period=200000,umask=0x40 event=0x69,period=200000,umask=0x40 Bus stalled for snoops Retired mispredicted branch instructions (precise event) (Precise event) event=0x88,period=2000000,umask=0x2 Bus cycles when core is not halted Cycles the divider is busy event=0xc3,period=200000,umask=0x1 Memory accesses that missed the DTLB event=0xd1,period=200003,umask=0x20 Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand cacheable data reads of full cache lines that hit the L2 cache Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) baclears.all Machine clears due to memory ordering issue event=0x13,period=200003,umask=0x2 event=0xc4,period=200003,umask=0xf7 Counts mispredicted branch instructions retired including all branch types (Must be precise) ld_blocks.4k_alias Uops issued to the back end per cycle event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000013010 Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event (Must be precise) dtlb_store_misses.walk_completed_1gb Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops which data sources were HitM responses from shared L3 Supports address when precise. Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event) Retired load uops which data sources were data hits in L3 without snoops required Supports address when precise. Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event) offcore_response.all_rfo.l3_hit.hit_other_core_no_fwd offcore_response.pf_l2_data_rd.l3_miss.any_response Counts all near executed branches (not necessarily retired) Stall cycles due to IQ is full Cycles at least 1 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 event=0xe,any=1,cmask=1,inv=1,period=2000003,umask=0x1 Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not event=0x22,umask=0x84 unc_cbo_xsnp_response.hit_external unc_arb_coh_trk_occupancy.all Misses in ITLB that causes a page walk of any page size offcore_response.pf_llc_data_rd.llc_hit.any_response offcore_response.demand_data_rd.llc_miss.local_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400002 Dirty L2 cache lines evicted by L2 prefetch event=0x27,period=200003,umask=0xf event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0244 Counts all data/code/rfo references (demand & prefetch) offcore_response.all_rfo.llc_hit.no_snoop_needed Counts all demand data reads event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10800 fp_comp_ops_exe.sse_packed_double fp_comp_ops_exe.sse_scalar_single Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC. Unit: uncore_arb Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC unc_cbo_cache_lookup.e Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response Counts prefetch (that bring data to L2) data reads that hit in the LLC Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode.demand. Unit: uncore_cbox (UNC_Q_TxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100. freq_ge_4000mhz_cycles % Counts the number of load micro-ops retired that miss in L1 D cache Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state Counts any Read request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts any request that accounts for responses which hit its own tile's L2 with data in M state offcore_response.demand_code_rd.l2_hit_far_tile offcore_response.demand_code_rd.l2_hit_near_tile_e_f event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000004 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000001 offcore_response.demand_rfo.l2_hit_far_tile_m offcore_response.demand_rfo.l2_hit_this_tile_e Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state offcore_response.pf_software.any_response offcore_response.pf_software.l2_hit_this_tile_e event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004001000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180608000 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080208000 Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far) offcore_response.partial_writes.mcdram Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600020 unc_e_rpq_inserts l2_transactions.wb l2_write.rfo.s_state mem_inst_retired.latency_above_threshold_8 mem_load_retired.llc_unshared_hit Offcore L1 data cache writebacks offcore_response.any_data.remote_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x244 Offcore code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x18FF Offcore RFO requests satisfied by the IO, CSR, MMIO unit offcore_response.corewb.any_location offcore_response.data_in.any_location Offcore request = all data, response = remote cache Offcore demand code reads satisfied by the LLC and HITM in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8002 Offcore demand RFO requests satisfied by the LLC offcore_response.other.llc_hit_other_core_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x130 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x710 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x140 Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core Offcore prefetch RFO requests satisfied by the LLC or local DRAM simd_int_128.packed_arith event=0x12,period=200000,umask=0x40 event=0xfd,period=200000,umask=0x1 SIMD integer 64 bit shuffle/move operations event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF811 offcore_response.any_request.any_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x60FF offcore_response.any_rfo.remote_dram offcore_response.demand_data_rd.local_dram offcore_response.demand_ifetch.local_dram Offcore other requests satisfied by a remote DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6010 arith.mul event=0xa7,period=2000000,umask=0x1 event=0xe5,period=2000000,umask=0x1 br_inst_exec.non_calls event=0xc5,period=2000,umask=0x2 event=0xa2,period=2000000,umask=0x1 SIMD Vector Integer Uops retired (Precise Event) Cycles no Uops are decoded This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF mem_inst_retired.stlb_miss_stores mem_load_misc_retired.uc offcore_response.demand_code_rd.l3_hit_e.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200400004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020001 offcore_response.demand_rfo.l3_hit_m.spl_hit Retired instructions after front-end starvation of at least 1 cycle (Must be precise) event=0xc6,period=100007,umask=0x1,frontend=0x410006 frontend_retired.latency_ge_2_bubbles_ge_3 Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6 offcore_response.demand_code_rd.l3_miss_local_dram.spl_hit offcore_response.demand_data_rd.l3_hit_e.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000001 rtm_retired.aborted_memtype exe_activity.3_ports_util exe_activity.bound_on_stores 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (10 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) ) Total pipeline cost of instruction fetch bandwidth related bottlenecks DSBmiss;Fed Cond_NT Bad;Branches Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault Counts the number of DTLB flush attempts of the thread-specific entries Counts any data read (demand & prefetch) that miss L2 with a snoop miss response Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache rehabq.lock Stalls due to FP assists This event counts all instruction fetches, not including most uncacheable
fetches IND_CALL counts the number of near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) RETURN counts the number of mispredicted near RET branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event) Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores offcore_response.demand_code_rd.llc_hit.snoop_miss offcore_response.demand_rfo.llc_hit_m.hitm REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2380408000 Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400040 Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS) (Precise event) This event counts the number of micro-ops retired. (Precise Event) (Precise event) event=0x60,period=2000000,umask=0x2 REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM offcore_response.demand_rfo.all_local_dram_and_remote_cache_hit REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f40 offcore_response.prefetch.local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0xf802 REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM event=0x85,period=2000000,umask=0x4 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5844 Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0491 OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0020 OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache offcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwd Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. SMT version; use when SMT is enabled and measuring per logical CPU Fraction of Core cycles where the core was running with power-delivery for license level 1 Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts??? unc_cha_requests.reads_remote 7.11E-06Bytes unc_iio_data_req_of_cpu.mem_write.part0 event=0x53,umask=0x02 Snoop filter capacity evictions for M-state entries. Unit: uncore_cha unc_cha_snoop_resp.rsp_wbwb PCIe Completion Buffer occupancy of completions with data: Part 0. Unit: uncore_iio event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x04 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x01 Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU. Unit: uncore_iio unc_iio_txn_req_by_cpu.peer_write.part0 unc_i_coherent_ops.pcitom RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache Traffic in which the M2M to iMC Bypass was not taken. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to A (SnoopAll) BL Ingress (from CMS) Allocations BL Egress (to CMS) Occupancy; All. Unit: uncore_m2m Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency Retired load instructions whose data sources was forwarded from a remote cache Supports address when precise ocr.all_data_rd.l3_hit_m.hit_other_core_no_fwd OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS ocr.all_data_rd.l3_hit_s.snoop_none OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200120 ocr.all_pf_rfo.l3_hit_f.snoop_none ocr.all_pf_rfo.l3_hit_s.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C07F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000807F7 OCR.ALL_READS.L3_HIT_E.SNOOP_NONE ocr.all_reads.l3_hit_f.hit_other_core_fwd OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED ocr.all_reads.l3_hit_s.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0122 OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040122 ocr.all_rfo.l3_hit_m.hit_other_core_fwd ocr.all_rfo.l3_hit_m.snoop_miss ocr.demand_data_rd.l3_hit_e.no_snoop_needed ocr.demand_rfo.l3_hit.hitm_other_core ocr.demand_rfo.l3_hit_f.snoop_miss ocr.demand_rfo.l3_hit_s.hit_other_core_no_fwd Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080400 ocr.pf_l1d_and_sw.l3_hit_m.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040010 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200020 ocr.pf_l2_rfo.l3_hit_m.hitm_other_core ocr.pf_l2_rfo.l3_hit_m.snoop_none ocr.pf_l3_data_rd.l3_hit_e.any_snoop Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED ocr.pf_l3_data_rd.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040100 offcore_response.all_data_rd.l3_hit_e.no_snoop_needed offcore_response.all_data_rd.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE offcore_response.all_data_rd.supplier_none.no_snoop_needed offcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400490 offcore_response.all_pf_rfo.l3_hit_s.hitm_other_core offcore_response.all_reads.l3_hit.snoop_hit_with_fwd This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED offcore_response.all_reads.l3_hit_f.snoop_miss offcore_response.all_reads.l3_hit_s.hit_other_core_fwd This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE offcore_response.demand_code_rd.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED offcore_response.demand_data_rd.l3_hit_f.hitm_other_core offcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_not_needed This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE offcore_response.other.l3_hit_e.hit_other_core_fwd This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE offcore_response.pf_l1d_and_sw.supplier_none.snoop_none This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400010 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP offcore_response.pf_l3_data_rd.supplier_none.hitm_other_core offcore_response.pf_l3_rfo.l3_hit_e.no_snoop_needed offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_hit_m.snoop_miss ocr.all_data_rd.l3_miss_local_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000491 ocr.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwd OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000490 ocr.all_pf_rfo.l3_miss.hitm_other_core OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2100007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000122 ocr.all_rfo.l3_miss_local_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000122 OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000004 ocr.demand_data_rd.l3_miss.hitm_other_core ocr.demand_data_rd.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000001 ocr.demand_data_rd.l3_miss_local_dram.any_snoop Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE ocr.demand_rfo.l3_miss.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000002 ocr.demand_rfo.l3_miss.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000002 ocr.demand_rfo.l3_miss_local_dram.hit_other_core_fwd Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD Counts any other requests OCR.OTHER.L3_MISS.SNOOP_MISS ocr.other.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B808000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000400 ocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwd ocr.pf_l2_rfo.l3_miss_local_dram.any_snoop Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000080 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD ocr.pf_l3_rfo.l3_miss_local_dram.no_snoop_needed ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD offcore_response.all_reads.l3_miss_local_dram.hitm_other_core This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD offcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_fwd offcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP ocr.demand_data_rd.supplier_none.hit_other_core_fwd Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xea,umask=0x4 unc_m2m_tag_hit.nm_rd_hit_dirty Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified ocr.demand_rfo.l3_hit.snoop_not_needed ocr.hwpf_l2_data_rd.l3_hit.snoop_sent Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified Cycles where at least 1 outstanding Demand RFO request is pending Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall (Precise event) ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED ) CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.) Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache Counts the number of times we entered an RTM region. Does not count nested transactions Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock ocr.demand_data_rd.local_dram Counts both direct and indirect near call instructions retired (Precise event) This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread Cycles where the Store Buffer was full and no loads caused an execution stall Cycles without actually retired instructions Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3 Flops;FpArith;InsType Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000477 ocr.hwpf_l3.l3_miss event=0xef,period=1000003,umask=0x8 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x90002380 All DRAM read CAS commands issued (including underfills). Unit: uncore_imc event=0x45,umask=0x02 unc_m_wpq_inserts.pch1 event=0x36,umask=0xC001FE04 TOR Inserts : RFOs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_drd unc_cha_tor_inserts.ia_miss_drd_pref_local TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_clflush unc_cha_tor_inserts.io_itomcachenear unc_cha_tor_inserts.ia_miss_full_streaming_wr TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC. Unit: uncore_cha Four byte data request of the CPU : Card writing to DRAM. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_read.part6 event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x80 event=0x16 Cycles in L1. Unit: uncore_upi TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory. Unit: uncore_cha event=0x34,period=200003,umask=0x2 ocr.all_code_rd.l3_hit.snoop_miss Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded ocr.hwpf_l2_code_rd.l3_hit.snoop_not_needed ocr.partial_streaming_wr.l3_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008003C0000 Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000004 Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x102184000000 This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000002 Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency) Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response Counts uncached memory reads that have any type of response Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS) event=0x71,period=1000003,umask=0x72 event=0x71,period=1000003,umask=0x4 unc_cha_tor_inserts.ia_miss_wcil Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 Clockticks of the IO coherency tracker (IRP) Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault Counts the number of page walks completed due to load DTLB misses to a 4K page Counts the number Extended Page Directory Pointer Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache Counts the total number of BACLEARS Branch instructions per taken branch. Unit: cpu_core Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Unit: cpu_core Ratio between Mispredicted branches and unknown branches. Unit: cpu_atom Counts the number of load ops retired that hit in the L3 cache (Precise event). Unit: cpu_atom mem_uops_retired.load_latency_gt_32 Counts the number of cache lines replaced in L1 data cache. Unit: cpu_core Demand requests that miss L2 cache. Unit: cpu_core Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event). Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0002 Demand Data Read requests sent to uncore. Unit: cpu_core Number of PREFETCHW instructions executed. Unit: cpu_core event=0xb3,period=2000003,umask=0x2 event=0xc6,period=100007,umask=0x1,frontend=0x608006 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core Number of machine clears due to memory ordering conflicts. Unit: cpu_core event=0xc1,period=100003,umask=0x1f event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10002 Counts the total number of branch instructions retired for all branch types (Precise event). Unit: cpu_atom event=0x73,period=1000003,umask=0x1 event=0xb0,cmask=1,period=1000003,umask=0x9 All branch instructions retired (Precise event). Unit: cpu_core Cycles total of 3 uops are executed on all ports and Reservation Station was not empty. Unit: cpu_core Execution stalls while memory subsystem has an outstanding load. Unit: cpu_core Loads blocked due to overlapping with a preceding store that cannot be forwarded. Unit: cpu_core Cycles Uops delivered by the LSD, but didn't come from the decoder. Unit: cpu_core event=0xb2,period=2000003,umask=0x20 incoming read request page status is Page Hit. Unit: uncore_imc event=0x1d Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels). Unit: uncore_imc unc_mc1_wrcas_count_freerun event=0x12,period=100003,umask=0x20 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008000002 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x80082380 FP_ARITH_INST_RETIRED2.512B_PACKED_HALF FRONTEND_RETIRED.UNKNOWN_BRANCH (Precise event) Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state int_misc.mba_stalls INT_VEC_RETIRED.SHUFFLES INT_VEC_RETIRED.VNNI_128 PMM Write Pending Queue inserts. Unit: uncore_imc Activate due to read, write, underfill, or bypass. Unit: uncore_imc event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000001 Write request of 4 bytes made by IIO Part2 to Memory. Unit: uncore_iio unc_iio_txn_req_of_cpu.peer_write.part6 event=0x50,umask=0x0000000004 unc_upi_txl_flits.slot1 unc_upi_txl_flits.null Valid Flits Sent : Idle. Unit: uncore_upi unc_upi_rxl_basic_hdr_match.ncs unc_upi_rxl_inserts.slot1 event=0xc1,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000004 event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000080 unc_m2m_prefcam_inserts.upi_allch event=0x35,umask=0x00c807fd01 TOR Inserts; LLCPrefRFO misses from local IA. Unit: uncore_cha unc_cha_tor_inserts.wbq event=0x36,umask=0x00ccc7fd01 event=0x36,umask=0x00cc43fe04 event=0x36,umask=0x0000000040 event=0x36,umask=0x00c827fe01 TOR Occupancy; ItoM from local IO. Unit: uncore_cha TOR Inserts : ItoMCacheNears issued by iA Cores. Unit: uncore_cha TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0x00c867ff01 event=0x36,umask=0x00c8678601 TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC. Unit: uncore_cha event=0x36,umask=0x00c86e8a01 bp_dyn_ind_pred ic_fw32_miss The number of 64 byte instruction cache line was fulfilled from the L2 cache l2_request_g1.prefetch_l2_cmd event=0x61,umask=0x04 event=0x63,umask=0x40 LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requests event=0x72,umask=0xff event=0xc7 Retired Indirect Branch Instructions Mispredicted event=0,umask=0x80 Total number of fp uOps on pipe 1 This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPS This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminated fp_retired_ser_ops.x87_ctrl_ret L1 DTLB Miss of a page of 4K size ls_tablewalker.ic_type1 ls_tablewalker.ic_type0 l2_cache_hits_from_dc_misses uops_dispatched Approximate: Outbound data bytes for all Remote Links for a node (die) event=0x85,umask=0x04 fp_disp_faults.xmm_fill_fault Retired lock instructions. Low speculative cacheable lock speculation succeeded ls_rdtsc Number of reads of the TSC (RDTSC instructions). The count is speculative LS MAB Allocates by Type. Loads ls_refills_from_sys.ls_mabresp_lcl_cache L1 DTLB Miss. DTLB reload hit a coalesced page ls_pref_instr_disp ls_sw_pf_dc_fill.ls_mabresp_rmt_dram de_dis_dispatch_token_stalls1.fp_misc_rsrc_stall de_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stall event=0xae,umask=0x10 The number of times a branch used the indirect predictor to make a prediction The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (1G page size) The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted Divide/square root FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent ls_alloc_mab_count Macro-ops Retired Retired branch instructions mispredicted event=0x1c8 ls_dmnd_fills_from_sys.near_cache ls_hw_pf_dc_fills.local_l2 Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2 l2_pf_miss_l2_hit_l3.l2_stride l2_pf_miss_l2_l3.l2_stream event=0x72,umask=0x01 event=0xac,umask=0x10 Retired Lock instructions which caused a bus lock Divide ops executed ex_no_retire.not_complete Retired microcode ops event=0x19f,umask=0x7fe event=0x2df,umask=0x7fe Write data beats (64 bytes) for local processor at Coherent Station (CS) 1 event=0x11f,umask=0x7ff Read data beats (64 bytes) for remote processor at Coherent Station (CS) 9 Write data beats (64 bytes) for remote processor at Coherent Station (CS) 1 remote_processor_write_data_beats_cs8 Write data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3 event=0x4df,umask=0x7fe event=0x51f,umask=0x7fe local_socket_inf0_outbound_data_beats_ccm5 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 4 Data beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 7 event=0x45f,umask=0xbff Data beats (64 bytes) for local socket outbound data from inter-socket xGMI link 7 Retired scalar floating-point multiply ops sse_avx_ops_retired.mmx_add sse_avx_ops_retired.mmx_logical Retired 128-bit packed floating-point subtract ops Retired 128-bit packed floating-point blend ops event=0xc,umask=0x30 event=0xc,umask=0xe0 Retired 128-bit packed integer shift ops packed_int_op_type.int256_shift Floating-point dispatch faults of all types for SSE and AVX ops ls_l1_d_tlb_miss.all_l2_miss de_src_op_disp.decoder Number of cycles dispatch is stalled for floating-point register file tokens PipelineL2;frontend_bound_group 6.103515625e-5MiB dram_read_data_for_local_processor event-two-hyph config=0x2c DTLB_REFILL PC_WRITE MEM_UNALIGNED_ACCESS EVENT_08H EVENT_11H EVENT_38H EVENT_53H EVENT_62H EVENT_9DH EVENT_A6H EVENT_F4H PLE_CACHE_LINE_REQ_COMPLETED BR_INDIRECT_SPEC EVENT_103H EVENT_154H EVENT_179H EVENT_189H EVENT_219H EVENT_222H EVENT_25BH EVENT_2A4H EVENT_2D5H EVENT_306H EVENT_307H EVENT_356H EVENT_369H EVENT_39AH EVENT_3C5H EVENT_3C7H EVENT_3D5H EXC_TRAP_DABORT L3D_CACHE_REFILL dn_rxreq_tlbi_dvmop rnd_txdat_flits cxha_chidat_up_stall cxra_snp_trk_occ clkdiv2_enqueue clkdiv2_write_depth clkdiv2_low_qos_depth clkdiv2_t_mac_tracker REFRESHED_DSTS FPU_RENORMALIZATION LSU_ALIAS_VS_FSQ_WB0_WB1 FP_LOAD_INSTR_COMPLETED_IN_LSU ITLB_NON_SPECULATIVE_MISSES GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY L2_CACHE_CASTOUTS OVERFLOW UOPS_COMPLETED LOAD_UOPS_COMPLETED TAKEN_BRANCHES_FINISHED CYCLES_BU_SCHED_STALLED STORES_COMPLETED DATA_L1_CACHE_RELOADS DATA_MMU_BUSY_CYCLES BIU_MASTER_INSTR_SIDE_REQUESTS BIU_MASTER_DATA_SIDE_REQUESTS PMC3_OVERFLOW STASH_HIT_DLFB os store-pipe-junk-ops invalid k8-fr-retired-taken-branches-mispredicted k8-ic-miss INVERT IAP INTEL_NEHALEM_EX INTEL_BROADWELL_XEON bad magic ex_ret_brn_misp ls_int_taken umask l3cache %s, "pid": "%d"}
UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD) Uops Per Instruction Floating Point Operations Per Cycle Backend;Cor;Pipeline;PortsUtil INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) MLP Average_Frequency This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects l2_rqsts.all_demand_miss l2_rqsts.code_rd_miss event=0x24,period=200003,umask=0x41 Demand Data Read requests that access L2 cache l2_trans.l1d_wb l2_trans.l2_wb mem_load_uops_l3_hit_retired.xsnp_miss This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required Supports address when precise. Spec update: BDM100 (Precise event) event=0xd1,period=50021,umask=0x4 mem_uops_retired.all_loads This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault Supports address when precise (Precise event) offcore_requests_outstanding.cycles_with_demand_rfo fp_arith_inst_retired.double Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element Number of SIMD FP assists due to Output values Number of X87 assists due to output value event=0xa0,period=2000003,umask=0x3 event=0x79,period=2000003,umask=0x3c idq.mite_cycles Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy event=0xc9,period=2000003,umask=0x4 rtm_retired.aborted_misc3 event=0x5d,period=2000003,umask=0x8 tx_mem.abort_capacity_write Speculative and retired indirect return branches Taken speculative and retired mispredicted macro conditional branches Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands event=0xc0,period=2000003 This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:
- preceding store conflicts with the load (incomplete overlap);
- store forwarding is impossible due to u-arch limitations;
- preceding lock RMW operations are not forwarded;
- store has the no-forward bit set (uncacheable/page-split/masked stores);
- all-blocking stores are used (mostly, fences and port I/O);
and others.
The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.
See the table of not supported store forwards in the Optimization Guide machine_clears.smc move_elimination.int_eliminated resource_stalls.sb Number of uops to be executed per-thread each cycle event=0xa1,any=1,period=2000003,umask=0x4 event=0xc2,period=2000003,umask=0x2 llc_misses.uncacheable power_self_refresh % dtlb_load_misses.walk_completed_1g event=0x8,period=2000003,umask=0x8 event=0x49,period=100003,umask=0x8 itlb_misses.miss_causes_a_walk tlb_flush.stlb_any UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\=0x81\,umask\=0x1@ This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement Supports address when precise (Precise event) Retired load uops with locked access Supports address when precise. Spec update: BDM35 (Precise event) Any memory transaction that reached the SQ offcore_response.all_pf_code_rd.any_response offcore_response.all_pf_code_rd.l3_hit.snoop_none offcore_response.all_pf_data_rd.supplier_none.any_snoop offcore_response.corewb.l3_hit.snoop_not_needed offcore_response.demand_rfo.l3_hit.snoop_none offcore_response.other.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020010 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020200 offcore_response.pf_l3_data_rd.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020080 Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element Counts randomly selected loads with latency value being above 128 Supports address when precise. Spec update: BDM100, BDM35 (Must be precise) offcore_response.all_data_rd.l3_miss.snoop_hit_no_fwd offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hit_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000090 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_not_needed offcore_response.all_rfo.l3_miss_local_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0008 offcore_response.demand_code_rd.l3_miss_local_dram.snoop_non_dram offcore_response.demand_data_rd.l3_miss.snoop_miss offcore_response.demand_data_rd.l3_miss_local_dram.any_snoop offcore_response.pf_l2_code_rd.l3_miss.snoop_hit_no_fwd offcore_response.pf_l2_rfo.l3_miss.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000020 offcore_response.pf_l3_rfo.l3_miss.snoop_hit_no_fwd offcore_response.pf_l3_rfo.l3_miss.snoop_miss L3 Lookup any request that access cache and found line in MESI-state. Unit: uncore_cbox L3 Lookup any request that access cache and found line in E or S-state. Unit: uncore_cbox Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic. Unit: uncore_arb event=0x80,cmask=1,umask=0x01 Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram qpi_data_bandwidth_tx unc_m_clockticks event=0x40,period=200000,umask=0x10 l2_ads.self l2_data_rqsts.self.mesi event=0x2c,period=200000,umask=0x4f l2_ifetch.self.m_state event=0x29,period=200000,umask=0x71 event=0x2b,period=200000,umask=0x44 l2_reject_busq.self.prefetch.i_state simd_inst_retired.scalar_double simd_uop_type_exec.logical.s SIMD unpacked micro-ops executed event=0x86,period=2000000,umask=0x1 event=0x5,period=200000,umask=0x8f prefetch.prefetchnta prefetch.prefetcht1 Number of Bus Not Ready signals asserted event=0x61,period=200000,umask=0x0 bus_hit_drv.all_agents bus_hit_drv.this_agent event=0x6d,period=200000,umask=0x40 event=0x6c,period=200000,umask=0x40 Cycles during which interrupts are disabled Cycles during which interrupts are pending and disabled ext_snoop.all_agents.hitm event=0x3b,period=200000,umask=0xc0 event=0x89,period=200000,umask=0x1 cpu_clk_unhalted.bus event=0x3c,period=2000000,umask=0x0 L0 DTLB misses due to store operations Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops dl1.dirty_eviction event=0xd0,period=200003,umask=0x43 Counts store uops retired where the data requested spans a 64 byte cache line boundary Supports address when precise (Must be precise) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000043091 offcore_response.any_data_rd.l2_miss.any event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600003091 Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required offcore_response.any_rfo.l2_miss.any offcore_response.demand_code_rd.outstanding Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module offcore_response.demand_rfo.outstanding Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000100 Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_needed event=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600004800 Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xe6,period=200003,umask=0x10 Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data Counts when a memory store of a uop spans a page boundary (a split) is retired (Must be precise) event=0xcb,period=200003,umask=0x4 Retired near return instructions (Precise event capable) (Must be precise) Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable) (Must be precise) Cycles the integer divide unit is busy event=0x3,period=200003,umask=0x10 Machine clears due to memory disambiguation offcore_response.any_data_rd.outstanding offcore_response.any_rfo.outstanding event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000400 Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l2_data_rd.outstanding event=0xc3,period=20003,umask=0x2 Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable) (Must be precise) Machines clear due to a page fault Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault Page walks outstanding due to an instruction fetch every cycle Counts all L2 HW prefetcher requests that hit L2 Miss in mid-level (L2) cache. Excludes Unknown data-source Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Retired load uops that miss the STLB Supports address when precise. Spec update: HSD29, HSM30 (Precise event) Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue Spec update: HSD78, HSD62, HSD61, HSM63, HSM80 offcore_response.demand_code_rd.l3_miss.any_response Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero event=0x5c,cmask=1,edge=1,period=100003,umask=0x1 Increments at the frequency of XCLK (100 MHz) when not halted Execution stalls due to L2 cache misses Spec update: HSM63, HSM80 Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch Number of uops executed on the core Spec update: HSD30, HSM31 unc_cbo_cache_lookup.extsnp_es L3 Lookup external snoop request that access cache and found line in I-state. Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in I-state An external snoop misses in some processor core. Unit: uncore_cbox dtlb_load_misses.pde_cache_miss dtlb_store_misses.pde_cache_miss Number of DTLB page walker hits in the L1+FB Number of DTLB page walker hits in Memory Spec update: HSD25 page_walker_loads.ept_itlb_l2 event=0xbd,period=100003,umask=0x1 l2_l1d_wb_rqsts.miss Retired load uops whose data source was local memory (cross-socket snoop not needed or missed) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0004 event=0xac,period=2000003,umask=0x8 Loads with latency value being above 64 (Must be precise) Cycles per thread when uops are dispatched to port 0 Cycles which a Uop is dispatched on port 3 Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles Cycle PMH is busy with a walk Counts all demand & prefetch code reads that miss the LLC event=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f800244 offcore_response.demand_data_rd.llc_miss.remote_hitm offcore_response.pf_l2_data_rd.llc_miss.any_dram llc_misses.pcie_non_snoop_read unc_p_freq_band2_transitions Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter. (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu (UNC_P_FREQ_GE_1200MHZ_CYCLES / UNC_P_CLOCKTICKS) * 100. event=0xe,filter_band3=40 l2_store_lock_rqsts.hit_e Retired store uops that miss the STLB (Precise event) Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING event=0xa2,period=2000003,umask=0x2 offcore_response.any_code_rd.outstanding Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state offcore_response.bus_locks.l2_hit_near_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000400 offcore_response.demand_code_rd.l2_hit_this_tile_s event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000001 offcore_response.demand_data_rd.l2_hit_this_tile_s event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080002 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400100 Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state Counts L2 code HW prefetches that accounts for any response Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000020 offcore_response.pf_l2_rfo.l2_hit_this_tile_s event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400044 offcore_response.any_data_rd.ddr offcore_response.any_data_rd.mcdram Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.demand_data_rd.ddr_far event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200002 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000040 offcore_response.pf_software.ddr event=0x3,umask=0x02 l1d_wb_l2.e_state event=0x26,period=200000,umask=0x4 event=0x26,period=200000,umask=0x80 All L2 misses l2_transactions.any All L2 transactions event=0x27,period=100000,umask=0x40 event=0x27,period=100000,umask=0xe mem_inst_retired.latency_above_threshold_16 event=0xb,period=50000,umask=0x10,ldlat=0x4 mem_inst_retired.latency_above_threshold_512 mem_load_retired.hit_lfb event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF11 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF44 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x444 offcore_response.any_ifetch.remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F22 event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF77 offcore_response.data_ifetch.local_cache Offcore code or data read requests that HITM in a remote cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x103 offcore_response.demand_data.local_cache offcore_response.demand_data.remote_cache_hit offcore_response.demand_data_rd.io_csr_mmio event=0xb7,period=100000,umask=0x1,offcore_rsp=0x8001 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1001 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x702 Offcore prefetch data requests satisfied by the LLC Offcore prefetch data reads satisfied by a remote cache or remote DRAM Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x420 offcore_response.pf_rfo.local_cache_dram offcore_response.pf_rfo.remote_cache_hit Offcore prefetch requests satisfied by a remote cache or remote DRAM event=0xf7,period=20000,umask=0x2 simd_int_128.pack simd_int_128.packed_logical event=0xb7,period=100000,umask=0x1,offcore_rsp=0x6022 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2004 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2070 Loads dispatched from stage 305 bpu_clears.late Unconditional call branches executed All non call branches executed Mispredicted conditional branches executed Mispredicted indirect call branches executed ild_stall.mru Total cycles (Precise Event) Uops issued on ports 0, 1 or 5 event=0xb1,period=2000000,umask=0x20 event=0xe,period=2000000,umask=0x1 uops_retired.active_cycles dtlb_load_misses.any itlb_miss_retired mem_load_l3_hit_retired.xsnp_none mem_load_retired.l1_hit Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C0004 offcore_response.demand_code_rd.l3_hit_e.snoop_not_needed offcore_response.demand_code_rd.l3_hit_s.any_snoop offcore_response.demand_data_rd.l4_hit_local_l4.spl_hit offcore_response.demand_data_rd.supplier_none.spl_hit offcore_response.demand_rfo.l3_hit_e.snoop_not_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C8000 Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events event=0xc6,period=100007,umask=0x1,frontend=0x401006 frontend_retired.latency_ge_4 Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4 Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency Supports address when precise (Must be precise) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C0004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000040001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC400002 Unfriendly TSX abort triggered by a vzeroupper instruction event=0xc0,cmask=10,inv=1,period=2000003,umask=0x1 Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues Ret dtlb_load_misses.walk_active Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store Loads missed L1 offcore_response.any_code_rd.l2_miss.hitm_other_core Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response offcore_response.pf_l2_data_rd.l2_miss.snoop_miss Loads blocked due to store data not ready This event counts the number of times that pipeline stalled due to FP operations needing assists TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event) Counts the number of cycles when no uops are allocated and a RATstall is asserted This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS) (Precise event) Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x17004001b3 REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff22 REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM REQUEST = CORE_WB and RESPONSE = ANY_LOCATION offcore_response.corewb.local_dram_and_remote_cache_hit event=0xb7,period=100000,umask=0x1,offcore_rsp=0xff33 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5080 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x250 REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM offcore_response.pf_rfo.all_local_dram_and_remote_cache_hit REQUEST = PREFETCH and RESPONSE = ANY_LOCATION event=0xb7,period=100000,umask=0x1,offcore_rsp=0x40ff REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4080 event=0xb4,period=100000,umask=0x2 event=0xb3,cmask=1,period=2000000,umask=0x4 snoopq_requests_outstanding.invalidate Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2701 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5804 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5880 mem_uncore_retired.local_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0120 Counts demand data reads that have any response type Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00004 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00001 offcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00400 core_power.lvl2_turbo_license Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory) DRAM Page Activate commands sent due to a write request. Unit: uncore_imc Streaming stores (partial cache line). Unit: uncore_cha LLC_MISSES.PCIE_READ unc_cha_snoop_resp.rspcnflcts Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory unc_iio_data_req_by_cpu.mem_read.part1 Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target. Unit: uncore_iio unc_iio_data_req_of_cpu.peer_read.part3 Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x04 Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU. Unit: uncore_iio event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x01 event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x04 Read request for up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline. Unit: uncore_irp Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket event=0x2e,umask=0x4 Multi-socket cacheline Directory update from S to A. Unit: uncore_m2m M2M Writes Issued to iMC; All, regardless of priority. Unit: uncore_m2m BL Egress (to CMS) Occupancy; All unc_upi_txl_flits.all_null event=0x2,umask=0x47 event=0x2,umask=0x97 ocr.all_data_rd.l3_hit_m.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100491 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100491 OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200490 ocr.all_pf_data_rd.l3_hit_m.no_snoop_needed OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS ocr.all_pf_rfo.l3_hit_e.hitm_other_core OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE ocr.all_reads.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2002007F7 OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100122 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_hit_e.no_snoop_needed Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE ocr.demand_data_rd.l3_hit_e.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040001 Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200002 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C8000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80048000 Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200400 Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED ocr.pf_l2_data_rd.l3_hit_s.no_snoop_needed ocr.pf_l2_rfo.l3_hit_e.no_snoop_needed Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100020 ocr.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100020 ocr.pf_l3_data_rd.l3_hit.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS offcore_response.all_data_rd.l3_hit_m.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020491 offcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwd offcore_response.all_pf_data_rd.l3_hit_s.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020490 This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD offcore_response.all_reads.l3_hit_f.hit_other_core_fwd offcore_response.all_reads.l3_hit_s.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.demand_data_rd.supplier_none.no_snoop_needed This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE offcore_response.demand_rfo.l3_hit_f.hitm_other_core This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD offcore_response.other.l3_hit_f.snoop_none offcore_response.pf_l1d_and_sw.l3_hit.snoop_miss offcore_response.pf_l1d_and_sw.l3_hit_s.snoop_miss offcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_needed offcore_response.pf_l1d_and_sw.supplier_none.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS offcore_response.pf_l2_data_rd.l3_hit_e.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE offcore_response.pf_l2_data_rd.l3_hit_f.snoop_none offcore_response.pf_l2_data_rd.l3_hit_s.hitm_other_core offcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020010 This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED offcore_response.pf_l2_rfo.l3_hit_m.any_snoop offcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_fwd offcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_fwd offcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS event=0xcf,period=2000003,umask=0x20 OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE ocr.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwd OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C0007F7 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2040007F7 ocr.all_reads.l3_miss_remote_hop1_dram.snoop_none ocr.all_rfo.l3_miss.hit_other_core_no_fwd OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS ocr.all_rfo.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000122 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000004 Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000004 ocr.demand_rfo.l3_miss.snoop_none Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000400 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000400 ocr.pf_l2_data_rd.l3_miss.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000020 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE event=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000080 Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE ocr.pf_l3_rfo.l3_miss.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.all_rfo.l3_miss_local_dram.no_snoop_needed offcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED offcore_response.other.l3_miss_local_dram.snoop_miss_or_no_fwd This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP offcore_response.pf_l2_data_rd.l3_miss.no_snoop_needed offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoop This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD offcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwd ocr.all_data_rd.pmm_hit_local_pmm.any_snoop ocr.all_reads.supplier_none.hitm_other_core ocr.all_rfo.pmm_hit_local_pmm.any_snoop OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD ocr.pf_l1d_and_sw.supplier_none.hit_other_core_fwd ocr.pf_l1d_and_sw.supplier_none.snoop_miss Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED ocr.pf_l2_data_rd.supplier_none.hitm_other_core ocr.pf_l2_rfo.supplier_none.hit_other_core_no_fwd Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED ocr.pf_l3_rfo.supplier_none.snoop_none Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full event=0xd1,period=50021,umask=0x20 Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C8000 Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events event=0xc6,period=100007,umask=0x1,frontend=0x500406 ocr.demand_rfo.dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000800 assists.any event=0xc5,period=50021,umask=0x2 A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0 (Precise event) Summary LSD ocr.demand_rfo.snc_cache.hitm ocr.hwpf_l1d_and_swpf.l3_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0477 ocr.demand_code_rd.l3_miss_local event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F844027F0 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FC00477 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x94000800 core_snoop_response.miss core_snoop_response.s_fwd_m Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster ocr.reads_to_core.any_response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F33000477 2LM Tag Check : Miss, no data in this line. Unit: uncore_imc DRAM Precharge commands. : Precharge due to read. Unit: uncore_imc event=0x4,umask=0x0f Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_rfo event=0x35,umask=0xC001FE01 unc_cha_tor_inserts.ia_drd_pref event=0x35,umask=0xC8077E01 event=0x35,umask=0xC8168A01 unc_cha_tor_occupancy.ia_miss_drd_pmm Data requested by the CPU : Core writing to Card's MMIO space. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_read.part4 unc_iio_data_req_of_cpu.mem_read.part4 unc_iio_num_req_of_cpu.commit.all unc_iio_comp_buf_occupancy.cmpd.part7 PCIe Completion Buffer Occupancy of completions with data : Part 0-7. Unit: uncore_iio Valid Flits Received : All Data. Unit: uncore_upi Valid Flits Sent : All Data. Unit: uncore_upi Valid Flits Sent : Null FLITs transmitted to any slot. Unit: uncore_upi unc_cha_tor_inserts.io_itom_local Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) Supports address when precise (Precise event) Counts all code reads that were supplied by the L3 cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD ocr.hwpf_l1d_and_swpf.l3_hit.snoop_hitm ocr.hwpf_l2_code_rd.l3_hit event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001F803C0000 ocr.uc_rd.l3_hit.snoop_hit_no_fwd Counts the number of BACLEARS due to a conditional jump Counts the number of requests that hit in the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000800 Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important ocr.all_code_rd.outstanding event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000040 ocr.uc_rd.local_dram machine_clears.any topdown_be_bound.serialization Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes Counts the number of uops issued by the front end every cycle TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC. Unit: uncore_cha PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 Clockticks of the mesh to memory (M2M) Counts the number of Extended Page Directory Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches Counts the number of Extended Page Directory Pointer Entry misses Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Unit: cpu_core Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based event=0x4,period=20003,umask=0x7 mem_uops_retired.load_latency_gt_8 Counts all the retired split loads Supports address when precise (Precise event). Unit: cpu_atom Number of L1D misses that are outstanding. Unit: cpu_core Retired store instructions that miss the STLB Supports address when precise (Precise event). Unit: cpu_core Retired load instructions which data sources missed L3 but serviced from local dram Supports address when precise. Unit: cpu_core event=0x40,period=100003,umask=0x2 event=0xb3,period=2000003,umask=0x4 Counts the number of requests to the instruction cache for one or more bytes of a cache line. Unit: cpu_atom event=0xc6,period=100007,umask=0x1,frontend=0x600406 icache_tag.stalls ld_head.l1_bound_at_ret event=0x5,period=1000003,umask=0xc0 Execution stalls while L1 cache miss demand load is outstanding. Unit: cpu_core Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Unit: cpu_core Counts the number of far branch instructions retired, includes far jump, far call and return, and Interrupt call and return (Precise event). Unit: cpu_atom serialization.non_c01_ms_scb Indirect near branch instructions retired (excluding returns) (Precise event). Unit: cpu_core TMA slots where uops got dropped. Unit: cpu_core integer ADD, SUB, SAD 128-bit vector instructions. Unit: cpu_core event=0xa4,period=10000003,umask=0x10 TMA slots available for an unhalted logical processor. Fixed counter - architectural event. Unit: cpu_core uops_dispatched.port_5_11 Cycles at least 1 micro-op is executed from any thread on physical core. Unit: cpu_core PRE command sent to DRAM due to page table idle timer expiration. Unit: uncore_imc event=0x12,period=100003,umask=0xe event=0x12,period=100003,umask=0x10 event=0x13,period=100003,umask=0x4 event=0x11,period=100003,umask=0x2 Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 Number of retired micro-operations (uops) for load or store memory accesses Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified) event=0xcf,period=100003,umask=0x4 fp_arith_inst_retired2.vector MEMORY_ACTIVITY.STALLS_L2_MISS ASSISTS.PAGE_FAULT event=0xb0,period=1000003,umask=0x8 Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions Uops executed on port 6 IMC Clockticks at HCLK frequency. Unit: uncore_imc event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000002 event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000002 event=0x50,umask=0x0000000008 Requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha event=0x2,umask=0x0000000020 unc_upi_rxl_occupancy.slot2 event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000004 event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000001 event=0xc2,ch_mask=0x08,fc_mask=0x07,umask=0x0000000004 event=0x1b,umask=0x07 event=0x21,umask=0x0302 event=0x2a TOR Inserts; RFO misses from local IO. Unit: uncore_cha TOR Inserts; RFO Pref hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c886fe01 event=0x35,umask=0x00c8877e01 unc_cha_tor_occupancy.ia_hit_crd event=0x36,umask=0x00c80ffd01 TOR Occupancy : PRQ - Non IOSF. Unit: uncore_cha TOR Occupancy : Just Local Targets. Unit: uncore_cha event=0x36,umask=0x00c88ffd01 unc_cha_tor_occupancy.ia_miss_drd_pref event=0x36,umask=0x00cc43fd04 unc_cha_tor_inserts.ia_wbeftoe event=0x36,umask=0x00c8f3fd04 unc_cha_tor_inserts.ia_miss_wcil_pmm unc_cha_tor_inserts.ia_miss_local_wcil_pmm unc_cha_tor_occupancy.ia_miss_local_wcilf_ddr TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0x00c8c3ff04 event=0x87,umask=0x01 event=0x61,umask=0x02 l2_cache_req_stat.ic_fill_hit_x l2_cache_req_stat.ic_fill_hit_s event=0x71,umask=0xff The number of retired taken branch instructions that were mispredicted ex_ret_near_ret_mispred dram_channel_data_controller_4 The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3 Double precision multiply FLOPS This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPS event=0x46,umask=0x0c Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched ls_pref_instr_disp.store_prefetch_w event=0x52,umask=0x02 de_dis_dispatch_token_stalls0.alu_token_stall L2 ITLB Misses & Instruction page walks event=0x43,umask=0x40 Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel de_dis_dispatch_token_stalls1.load_queue_token_stall Retired Ops. Use macro_ops_retired instead event=0x60,umask=0xe8 ls_dmnd_fills_from_sys.all In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle l2_pf_hit_l2.l1_region L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous) L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (aggressively fetch additional sequential lines into L2 cache) L3 cache hits. Unit: amd_l3 l3_xi_sampled_latency_requests.near_cache l3_xi_sampled_latency_requests.far_cache Number of cycles the divider is busy Cycles with no retire while the oldest op is waiting for load data remote_processor_read_data_beats_cs0 event=0x2df,umask=0xbfe Write data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0 event=0x89f,umask=0xbff event=0x45e,umask=0x7fe local_socket_inf1_inbound_data_beats_ccm2 event=0x49f,umask=0x7fe local_socket_inf1_outbound_data_beats_ccm7 Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 2 event=0x55e,umask=0xbfe Data beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 5 Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 4 remote_socket_inf1_outbound_data_beats_ccm7 event=0x8,umask=0x3f fp_ops_retired_by_type.vector_div event=0xb,umask=0x0b sse_avx_ops_retired.mmx_all sse_avx_ops_retired.sse_avx_pack event=0xb,umask=0xc0 event=0xb,umask=0xf0 Retired SSE and AVX integer ops of all types fp_pack_ops_retired.fp128_div Retired 128-bit packed floating-point divide ops fp_pack_ops_retired.fp128_blend event=0xc,umask=0x09 Retired 128-bit packed floating-point ops of all types Retired 256-bit packed floating-point subtract ops fp_pack_ops_retired.fp256_div Retired 256-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions) event=0xd,umask=0x40 packed_int_op_type.int256_all umc_act_cmd.rd umc_pchg_cmd.all Ops fetched from instruction cache and dispatched In each cycle counts dispatch slots left empty because the front-end did not supply ops l1_data_cache_fills_from_different_ccx All TLBs flushed Local socket upstream DMA write data DC_DCACHE_ACCESSES_BY_LOCKS FR_RETIRED_NEAR_RETURNS_MISPREDICTED PMUEXTIN0_EVT EVENT_0BH EVENT_16H EVENT_20H EVENT_45H EVENT_46H EVENT_4CH EVENT_57H EVENT_6EH EVENT_7FH EVENT_9CH EVENT_DEH EVENT_DFH DATA_CACHE_DEPENDENT_STALL EVENT_11FH EVENT_134H EVENT_148H EVENT_16EH EVENT_19FH EVENT_1D7H EVENT_1E4H EVENT_1E5H EVENT_1F7H EVENT_1FBH EVENT_20CH EVENT_214H EVENT_21EH EVENT_22DH EVENT_275H EVENT_291H EVENT_2AFH EVENT_2BAH EVENT_2DDH EVENT_2EFH EVENT_2F4H EVENT_2FFH EVENT_310H EVENT_314H EVENT_318H EVENT_31FH EVENT_327H EVENT_32DH EVENT_35EH EVENT_363H EVENT_368H EVENT_391H EVENT_3A5H EVENT_3A9H EVENT_3FAH L2D_CACHE_REFILL_LD L2D_CACHE_INVAL MEM_ACCESS_ST CRYPTO_SPEC L2D_TLB_REFILL_RD hnf_mc_retries hnf_txdat_stall hni_txrsp_retryack hni_awvalid_no_awready rnd_s2_wdata_beats cxla_tx_tlp_buffer_full VIU1_INSTR_COMPLETED INSTR_BKPT_MATCHES LOAD_MISS_ALIAS_ON_TOUCH L1_DATA_TOUCH_MISS_CYCLES L1_DATA_TOTAL_MISS TOUCHES_TRANSLATED low-op-pos-1 rdszdword k8-fr-retired-taken-branches INTEL_CORE2 kern.hwpmc.cpuid %s, "tsc": "%jd" %s, "tid": "%d", "pid": "%d", "flags": "0x%08x", "tdname": "%s"}
v5 GenuineIntel-6-7A This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example Pipeline;Ret;Retire 1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD) ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) ) ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES IpLoad L2_Cache_Fill_BW L2MPKI 1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses l2_rqsts.all_code_rd event=0x24,period=200003,umask=0xe4 Demand requests that miss L2 cache event=0x24,period=200003,umask=0xe2 L1D writebacks that access L2 cache event=0x2e,period=100003,umask=0x41 (null) mem_uops_retired.lock_loads event=0xb0,period=100003,umask=0x2 Number of SIMD FP assists due to input values Cycles Decode Stream Buffer (DSB) is delivering any Uop This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty idq.ms_dsb_occur Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled memory event=0xc3,period=100003,umask=0x2 This event counts loads with latency value being above 128 Spec update: BDM100, BDM35 (Must be precise) Number of times an RTM execution aborted due to incompatible memory type event=0xc9,period=2000003,umask=0x2 tx_mem.abort_conflict br_inst_exec.taken_indirect_near_call br_inst_retired.not_taken br_misp_retired.ret cpu_clk_unhalted.thread_any Stalls caused by changing prefix length of the instruction Cases when loads get true Block-on-Store blocking code preventing store forwarding Cycles per thread when uops are executed in port 2 This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2 event=0xb1,cmask=1,period=2000003,umask=0x1 Counts number of cycles no uops were dispatched to be executed on this thread Cycles per core when uops are exectuted in port 0 uops_executed_port.port_5 uops_issued.stall_cycles event=0x35,umask=0x3,filter_opc=0x1c8 unc_h_snoop_resp.rsps event=0x21,umask=0x2 unc_m_dclockticks freq_max_limit_thermal_cycles % (UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100. Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K) Spec update: BDM69 This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault Spec update: BDM69 Number of DTLB page walker hits in the L2 Spec update: BDM69, BDM98 page_walker_loads.itlb_l1 event=0x24,period=200003,umask=0xc2 This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on offcore_response.all_pf_code_rd.l3_hit.snoop_miss offcore_response.all_pf_rfo.l3_hit.snoop_hit_no_fwd offcore_response.all_rfo.supplier_none.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020122 offcore_response.demand_data_rd.any_response offcore_response.demand_data_rd.l3_hit.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0010 offcore_response.pf_l2_data_rd.supplier_none.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0020 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0080 offcore_response.pf_l3_rfo.l3_hit.snoop_hit_no_fwd Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element offcore_response.all_data_rd.l3_miss_local_dram.snoop_not_needed offcore_response.all_pf_data_rd.supplier_none.snoop_non_dram event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020090 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000120 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000122 offcore_response.corewb.l3_miss_local_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000001 offcore_response.demand_data_rd.l3_miss_local_dram.snoop_none event=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C008000 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004008000 offcore_response.other.l3_miss_local_dram.snoop_non_dram unc_cbo_xsnp_response.hit_xcore Number of Writes allocated - any write transactions: full/partials writes and evictions. Unit: uncore_arb unc_arb_coh_trk_requests.all Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;. Unit: uncore_arb offcore_response.all_data_rd.llc_hit.hitm_other_core offcore_response.demand_rfo.llc_miss.any_response uncore interconnect event=0x40,period=2000000,umask=0xa1 event=0x2d,period=200000,umask=0x44 L2 cache line modifications l2_no_req.self event=0x30,period=200000,umask=0x58 event=0x2e,period=200000,umask=0x74 SIMD packed logical micro-ops executed simd_uop_type_exec.mul.s event=0xb3,period=2000000,umask=0x4 simd_uop_type_exec.unpack.ar SIMD unpacked micro-ops retired macro_insts.all_decoded All Instructions decoded Non-CISC nacro instructions decoded Memory references that cross an 8-byte boundary (At Retirement) Store splits (Ar Retirement) event=0x62,period=200000,umask=0x0 IO requests waiting in the bus queue bus_trans_rfo.self ext_snoop.this_agent.hit Retired branch instructions event=0xa,period=2000000,umask=0x0 event=0x2,period=200000,umask=0x81 event=0xc2,period=2000000,umask=0x10 data_tlb_misses.l0_dtlb_miss_ld ITLB misses (Must be precise) Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000018000 offcore_response.bus_locks.any_response Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000800 Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.sw_prefetch.l2_miss.hit_other_core_no_fwd event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400001000 uops_retired.fpdiv event=0xc4,period=200003,umask=0x80 Retired conditional branch instructions (Precise event capable) (Must be precise) Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted (Must be precise) Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs) offcore_response.pf_l1_data_rd.outstanding offcore_response.streaming_stores.any_response Page walk completed due to a demand load to a 1GB page dtlb_load_misses.walk_pending event=0xf2,period=100003,umask=0x6 Cycles in which the L1D is locked Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram offcore_response.pf_l3_data_rd.l3_miss.any_response Any uop executed by the Divider. (This includes all divide uops, sqrt, ...) Mispredicted branch instructions at retirement Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle Cycles at least 4 micro-op is executed from any thread on physical core Spec update: HSD30, HSM31 Cycles which a uop is dispatched on port 5 in this thread Cycles which a uop is dispatched on port 7 in this thread Number of flags-merge uops allocated. Such uops add delay uops_retired.core_stall_cycles unc_cbo_xsnp_response.hitm_eviction event=0x83,umask=0x01 Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size Number of DTLB page walker loads from memory Spec update: HSD25 page_walker_loads.ept_dtlb_l3 Number of ITLB page walker loads that hit in the L2 offcore_response.pf_l2_data_rd.llc_hit.any_response Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.) event=0x24,period=200003,umask=0x8 All retired load uops. (Precise Event) offcore_response.demand_rfo.llc_hit.no_snoop_needed Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10400 event=0x10,period=2000003,umask=0x80 dsb2mite_switches.count Counts cycles MITE is delivered at least one uops. Set Cmask = 1 Cycles while L2 cache miss load* is outstanding Cycles the RS is empty for the thread Cycles per core when load or STA uops are dispatched to port 3 Counts the number of LLC evictions allocated. Unit: uncore_arb Counts the number of allocated write entries, include full, partial, and LLC evictions. Unit: uncore_arb LLC lookup request that access cache and found line in S-state Filter on processor core initiated cacheable write requests. Unit: uncore_cbox Filter on external snoop requests Page walk for a large page completed for Demand load Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G) offcore_response.all_pf_data_rd.llc_hit.hit_other_core_no_fwd Counts prefetch (that bring data to LLC only) data reads that hit in the LLC offcore_response.pf_llc_data_rd.llc_hit.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0080 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc00001 event=0x35,umask=0x3,filter_opc=0x1e4 Cycles where transmitting QPI link is in half-width mode. Unit: uncore_qpi freq_band0_cycles % unc_p_freq_ge_1200mhz_cycles event=0x28,period=200003,umask=0x2 Data from local DRAM either Snoop not needed or Snoop Miss (RspI) This event counts the number of load uops retired (Precise event) Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS) (Must be precise) Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized resource_stalls2.all_fl_empty Cycles when Allocator is stalled if BOB is full and new branch needs it offcore_response.any_code_rd.l2_hit_far_tile offcore_response.any_code_rd.l2_hit_far_tile_m Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000070 offcore_response.any_pf_l2.l2_hit_this_tile_m event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00080032f7 offcore_response.any_request.l2_hit_near_tile offcore_response.any_rfo.l2_hit_near_tile_m Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400004 Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000001 Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response offcore_response.partial_reads.l2_hit_this_tile_e event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400100 Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode Counts UC code reads (valid only for Outstanding response type) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state event=0xc2,period=200003,umask=0x40 Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far offcore_response.any_data_rd.ddr_near offcore_response.any_pf_l2.mcdram_near offcore_response.any_request.ddr Counts any request that accounts for responses from MCDRAM (local and far) offcore_response.bus_locks.mcdram_far Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far offcore_response.partial_writes.mcdram_near Counts L1 data HW prefetches that accounts for data responses from DRAM Far Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local offcore_response.pf_l2_code_rd.ddr_near Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local offcore_response.pf_l2_rfo.mcdram_near offcore_response.pf_l2_rfo.non_dram offcore_response.pf_software.mcdram Counts the number of mispredicted near CALL branch instructions retired (Precise event) no_alloc_cycles.mispredicts event=0x3,period=200003,umask=0x40 Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included l1d_cache_prefetch_lock_fb_hit event=0x28,period=100000,umask=0x4 All L1 writebacks to L2 L2 data demand requests event=0x24,period=200000,umask=0x3 event=0xf0,period=200000,umask=0x8 l2_write.lock.e_state event=0xb,period=100,umask=0x10,ldlat=0x400 Memory instructions retired above 2048 clocks (Precise Event) Retired loads that hit the L1 data cache (Precise Event) event=0xb7,period=100000,umask=0x1,offcore_rsp=0x711 offcore_response.any_rfo.llc_hit_other_core_hit offcore_response.corewb.remote_cache_hitm event=0xb7,period=100000,umask=0x1,offcore_rsp=0x203 Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit offcore_response.demand_rfo.local_cache event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1880 offcore_response.pf_data.local_cache_dram event=0xb7,period=100000,umask=0x1,offcore_rsp=0x110 Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core offcore_response.pf_data_rd.remote_cache_dram offcore_response.pf_ifetch.remote_cache_dram offcore_response.prefetch.llc_hit_other_core_hitm Offcore prefetch requests that HITM in a remote cache Super Queue lock splits across a cache line fp_comp_ops_exe.sse_single_precision SSE* FP single precision Uops offcore_response.any_data.any_llc_miss event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF810 offcore_response.prefetch.any_llc_miss Early Branch Prediciton Unit clears event=0x89,period=20000,umask=0x2 Mispredicted unconditional branches executed event=0x89,period=2000,umask=0x30 Mispredicted near retired calls (Precise Event) event=0x87,period=2000000,umask=0x8 inst_queue_write_cycles event=0xc0,period=2000000,umask=0x4 inst_retired.total_cycles inst_retired.total_cycles_ps machine_clears.mem_order resource_stalls.fpcw event=0x8,period=200000,umask=0x1 dtlb_misses.any dtlb_misses.walk_completed Counts the total number of L2 code requests Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache All retired store instructions Supports address when precise (Precise event) mem_load_l3_hit_retired.xsnp_hitm Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready Supports address when precise (Precise event) offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hit_no_fwd offcore_response.demand_data_rd.l3_hit_e.any_snoop offcore_response.demand_data_rd.l3_hit_m.snoop_miss Counts any other requestshave any response type offcore_response.other.l3_hit_m.snoop_miss frontend_retired.latency_ge_8 Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS event=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C400001 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000400002 Far branch instructions retired Spec update: SKL091 (Precise event) Taken branch instructions retired Spec update: SKL091 (Precise event) event=0xa3,cmask=16,period=2000003,umask=0x10 Mispredictions Fetch_UpC (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) DSB_Misses_Cost_SMT ( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES Page walk completed due to a demand data load to a 4K page Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture Counts any code reads (demand & prefetch) that miss L2 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000001 event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000040 Counts the number of branch instructions retired.. (Precise event) Counts the number of JCC branch instructions retired (Precise event) Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event) Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions "older" than this one will be allowed to finish. This instruction and all "younger" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY Total page walks that are completed (I-side and D-side) Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) (Precise event) offcore_response.all_pf_rfo.llc_hit.hitm_other_core Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0200 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0100 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400120 This event counts any requests that miss the LLC where the data was returned from local DRAM event=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400100 REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS event=0xb7,period=100000,umask=0x1,offcore_rsp=0x3008 REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM event=0xb7,period=100000,umask=0x1,offcore_rsp=0x4050 REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS event=0x3,period=200000,umask=0x2 snoopq_requests_outstanding.data_not_empty Outstanding snoop invalidate requests dtlb_load_misses.large_walk_completed DTLB load miss large page walks event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5808 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1850 event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5820 offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_core Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0100 offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00120 offcore_response.all_rfo.l3_miss.remote_hitm event=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00002 offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000010 Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwd core_power.throttle Streaming stores (full cache line). Unit: uncore_cha Ingress (from CMS) Request Queue Rejects; PhyAddr Match. Unit: uncore_cha Ingress (from CMS) Request Queue Rejects; PhyAddr Match Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline event=0x5c,umask=0x04 unc_iio_comp_buf_occupancy.cmpd.part2 Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x08 event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x02 Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x02 Multi-socket cacheline Directory lookups (any state found). Unit: uncore_m2m Multi-socket cacheline Directory update from A to I. Unit: uncore_m2m AD Egress (to CMS) Allocations. Unit: uncore_m2m unc_upi_l1_power_cycles unc_upi_txl_flits.idle Protocol header and credit FLITs transmitted across any slot. Unit: uncore_upi Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit ocr.all_data_rd.l3_hit_m.snoop_miss OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED ocr.all_pf_data_rd.l3_hit_e.hit_other_core_fwd OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200490 event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040490 OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200120 OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED ocr.all_reads.l3_hit_e.snoop_none ocr.all_reads.l3_hit_s.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200122 ocr.demand_code_rd.l3_hit.hitm_other_core ocr.demand_data_rd.l3_hit.snoop_none ocr.demand_data_rd.l3_hit_e.snoop_miss ocr.demand_data_rd.l3_hit_m.hitm_other_core Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040002 ocr.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080400 ocr.pf_l1d_and_sw.l3_hit_e.snoop_none ocr.pf_l1d_and_sw.l3_hit_f.snoop_miss ocr.pf_l2_data_rd.l3_hit.hitm_other_core ocr.pf_l2_data_rd.l3_hit_e.snoop_miss event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080010 Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP ocr.pf_l2_data_rd.l3_hit_m.any_snoop Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0020 Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080080 ocr.pf_l3_data_rd.l3_hit_e.snoop_none ocr.pf_l3_data_rd.l3_hit_f.no_snoop_needed ocr.pf_l3_rfo.l3_hit.no_snoop_needed Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200100 This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD offcore_response.all_data_rd.l3_hit_m.snoop_none offcore_response.all_data_rd.supplier_none.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020491 offcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP offcore_response.all_reads.l3_hit_s.snoop_miss This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE offcore_response.all_rfo.l3_hit_m.hit_other_core_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400122 This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020122 This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE offcore_response.pf_l2_data_rd.l3_hit_e.any_snoop offcore_response.pf_l2_data_rd.l3_hit_s.no_snoop_needed offcore_response.pf_l2_rfo.l3_hit_m.no_snoop_needed offcore_response.pf_l3_data_rd.l3_hit.hit_other_core_fwd offcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE offcore_response.pf_l3_rfo.l3_hit_f.hitm_other_core offcore_response.pf_l3_rfo.l3_hit_m.no_snoop_needed event=0xcf,period=2000003,umask=0x40 ocr.all_data_rd.l3_miss.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000491 OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP ocr.all_pf_data_rd.l3_miss_local_dram.no_snoop_needed event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000490 ocr.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoop event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000120 ocr.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_core OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD ocr.demand_code_rd.l3_miss.hitm_other_core Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE ocr.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwd Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP ocr.other.l3_miss_remote_hop1_dram.snoop_miss ocr.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_core ocr.pf_l2_rfo.l3_miss.hit_other_core_no_fwd event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000020 ocr.pf_l3_data_rd.l3_miss.hit_other_core_fwd ocr.pf_l3_rfo.l3_miss.any_snoop Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP offcore_response.all_pf_rfo.l3_miss.no_snoop_needed offcore_response.all_reads.l3_miss_local_dram.hit_other_core_no_fwd This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE offcore_response.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_needed offcore_response.other.l3_miss_local_dram.hit_other_core_no_fwd offcore_response.other.l3_miss_remote_hop1_dram.hitm_other_core This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD offcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_miss This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP offcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_none ocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_needed OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP ocr.all_reads.pmm_hit_local_pmm.snoop_not_needed OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE ocr.demand_code_rd.supplier_none.snoop_miss ocr.demand_data_rd.supplier_none.snoop_miss Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD ocr.pf_l3_data_rd.supplier_none.snoop_none UNC_M_PMM_READ_LATENCY Tag Hit; Underfill Rd Hit from NearMem, Clean Line ocr.hwpf_l3.l3_hit.any event=0x60,period=1000003,umask=0x8 Counts all microcode FP assists Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element Uops not delivered by IDQ when backend of the machine is not stalled TOPDOWN.SLOTS INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts) event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC08000 event=0xc9,period=100003,umask=0x20 event=0xc9,period=100003,umask=0x1 ocr.hwpf_l1d_and_swpf.dram This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread event=0xa3,cmask=8,period=1000003,umask=0x8 event=0x5e,period=1000003,umask=0x1 event=0xa4,period=10000003,umask=0x2 Counts the number of uops executed from any thread uops_executed.cycles_ge_2 uops_executed.cycles_ge_3 Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle MemoryBW;Offcore Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode) Supports address when precise (Precise event) Retired instructions with at least 1 uncacheable load or Bus Lock Supports address when precise (Precise event) Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core event=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000004 Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster ocr.reads_to_core.remote_pmm event=0xe0,umask=0x01 event=0x35,umask=0xC001FF04 unc_cha_tor_inserts.io_miss TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC. Unit: uncore_cha event=0x35,umask=0xC8977E01 TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha event=0x36,umask=0xc8f3fe04 unc_cha_tor_inserts.ia_miss_drd_remote_ddr unc_iio_data_req_of_cpu.cmpd.part0 unc_iio_txn_req_of_cpu.cmpd.part2 event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x01 unc_iio_txn_req_of_cpu.mem_write.part5 unc_iio_comp_buf_occupancy.cmpd.part6 unc_iio_comp_buf_occupancy.cmpd.part4 event=0x34,period=200003,umask=0x7 Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM) Counts the number of load uops retired that miss in the L1 data cache Supports address when precise (Precise event) Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0002 Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded Counts uncached memory writes that were supplied by the L3 cache This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000002 ocr.uc_rd.l3_miss_local ocr.uc_wr.l3_miss_local Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks ocr.corewb_m.outstanding event=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000020 ocr.uc_rd.outstanding Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) (Precise event) Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops event=0x74,period=1000003,umask=0x10 event=0xc2,period=1000003 Counts the total number of uops retired (Precise event) Number of DRAM Refreshes Issued : Counts the number of refreshes issued event=0x35,umask=0xC001FE01,config1=0x40040e33 unc_cha_tor_inserts.ia_hit_drd_opt_pref event=0x36,umask=0xC827FE01 PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault Counts the number of page walks completed due to instruction fetch misses to a 4K page Floating Point Operations Per Cycle. Unit: cpu_core Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in DRAM or MMIO (Non-DRAM). Unit: cpu_atom event=0x61,period=100003,umask=0x2 Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core Cycles Decode Stream Buffer (DSB) is delivering any Uop. Unit: cpu_core ld_head.st_addr_at_ret Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation. Unit: cpu_atom memory_activity.cycles_l1d_miss event=0x47,cmask=5,period=1000003,umask=0x5 Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles Supports address when precise (Must be precise). Unit: cpu_core Far branch instructions retired (Precise event). Unit: cpu_core event=0xc5,period=400009,umask=0x11 Mispredicted non-taken conditional branch instructions retired (Precise event). Unit: cpu_core Core crystal clock cycles when this thread is unhalted and the other thread is halted. Unit: cpu_core Execution stalls while L2 cache miss demand load is outstanding. Unit: cpu_core Uops executed on port 0. Unit: cpu_core uops_executed.stalls unc_m_vc1_requests_wr event=0x1e unc_m_pre_count_idle This 48-bit fixed counter counts the UCLK cycles. Unit: uncore_clock Counts the number of page walks completed due to load DTLB misses to any page size. Unit: cpu_atom This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0004 event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F803C0002 Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808004477 OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions Number of uops dispatch to execution port 1 event=0xe0,umask=0x0000000002 event=0x3,umask=0x0000000011 unc_m_cas_count.wr_pre unc_m_pmm_rpq_occupancy.gnt_wait_sch0 event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000001 TOR Inserts for CRd misses from local IA. Unit: uncore_cha Matches on Transmit path of a UPI Port : Non-Coherent Standard. Unit: uncore_upi Prefetch CAM Inserts : UPI - All Channels. Unit: uncore_m2m unc_m2m_prefcam_demand_merge.xpt_allch OSB Snoop Broadcast : Local Rd. Unit: uncore_cha event=0x34,umask=0x00001bc1ff event=0x35,umask=0x0000000004 event=0x35,umask=0x00C000FF04 event=0x36,umask=0x0000000001 TOR Occupancy : IRQ - iA. Unit: uncore_cha unc_cha_tor_occupancy.noncoh unc_cha_tor_occupancy.io_hit_itom TOR Occupancy; RFO from local IA. Unit: uncore_cha event=0x36,umask=0x00C8977E01 unc_cha_tor_occupancy.ia_llcprefdata TOR Occupancy; LLCPrefData from local IA. Unit: uncore_cha TOR Occupancy; LLCPrefData misses from local IA. Unit: uncore_cha event=0x35,umask=0x00C8970601 event=0x35,umask=0x00C80F7E01 event=0x35,umask=0x00C88EFE01 unc_cha_tor_inserts.ia_miss_remote_wcil_ddr event=0x36,umask=0x00c8170a01 event=0x36,umask=0x00c8970a01 TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_clflush TOR Occupancy : ItoMCacheNears issued by iA Cores. Unit: uncore_cha event=0x36,umask=0x00cc57ff01 event=0x36,umask=0x00c87fde01 TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC. Unit: uncore_cha event=0x36,umask=0x00cd43fe04 bp_l2_btb_correct ic_cache_inval.fill_invalidated event=0xc8 Retired Near Returns Mispredicted event=0x7c7,umask=0x02 Single-precision multiply FLOPS ls_locks.bus_lock event=0x41,umask=0x01 event=0x45,umask=0x80 L1 DTLB Miss of a page of 2M size ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit l2_cache_misses_from_dc_misses l2_cache_misses_from_l2_hwpf L1 ITLB Misses l2_itlb_misses L1 Branch Prediction Overrides Existing Prediction (speculative) All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15 fp_ret_sse_avx_ops.mac_flops Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes SSE bottom-executing uOps retired. The number of serializing Ops retired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retired fp_disp_faults.ymm_fill_fault Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss event=0x59,umask=0x10 event=0x5a,umask=0x02 de_dis_uops_from_decoder.opcache_dispatched The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 2M page The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS Demand Data Cache Fills by Data Source. From cache of different CCX in same node Any Data Cache Fills by Data Source. From DRAM or IO connected in same node ls_hw_pf_dc_fills.mem_io_remote ls_hw_pf_dc_fills.ext_cache_local Instruction Cache (32B) Fetch Miss Ratio Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts) Demand data cache fills from L3 cache or different L2 cache in the same CCX Software prefetch instructions dispatched (speculative) of all types Software prefetch data cache fills from cache of another CCX in the same NUMA node ls_hw_pf_dc_fills.near_cache L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss) L2 cache requests: data cache state change to writable, check L2 for current state l2_cache_req_stat.dc_hit_in_l2 event=0x70,umask=0x08 event=0x72,umask=0x20 event=0x72,umask=0x40 event=0xd6,umask=0x02 event=0x9f,umask=0x7fe Read data beats (64 bytes) for local processor at Coherent Station (CS) 7 local_processor_write_data_beats_cs4 local_processor_write_data_beats_cs7 Write data beats (64 bytes) for local processor at Coherent Station (CS) 9 event=0x1f,umask=0xbfe Write data beats (64 bytes) for remote processor at Coherent Station (CS) 2 event=0x85f,umask=0x7fe local_socket_inf0_inbound_data_beats_ccm0 local_socket_inf1_outbound_data_beats_ccm6 event=0x4de,umask=0xbfe Data beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 1 event=0x59e,umask=0xbff Retired SSE and AVX control word mispredict traps event=0xa,umask=0x90 event=0xb,umask=0x02 sse_avx_ops_retired.mmx_cmp sse_avx_ops_retired.mmx_mov sse_avx_ops_retired.mmx_other fp_pack_ops_retired.fp128_mac Retired 256-bit packed floating-point compare ops event=0xd,umask=0x0c umc_act_cmd.all l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all L3 cache accesses local_socket_inf0_outbound_data_beats_ccm0 + local_socket_inf1_outbound_data_beats_ccm0 + local_socket_inf0_outbound_data_beats_ccm1 + local_socket_inf1_outbound_data_beats_ccm1 + local_socket_inf0_outbound_data_beats_ccm2 + local_socket_inf1_outbound_data_beats_ccm2 + local_socket_inf0_outbound_data_beats_ccm3 + local_socket_inf1_outbound_data_beats_ccm3 + local_socket_inf0_outbound_data_beats_ccm4 + local_socket_inf1_outbound_data_beats_ccm4 + local_socket_inf0_outbound_data_beats_ccm5 + local_socket_inf1_outbound_data_beats_ccm5 + local_socket_inf0_outbound_data_beats_ccm6 + local_socket_inf1_outbound_data_beats_ccm6 + local_socket_inf0_outbound_data_beats_ccm7 + local_socket_inf1_outbound_data_beats_ccm7 Estimated memory read bandwidth l3_cache_rd uncore_hisi_l3c.rd_hit_cpipe ���������c���O�4����5�������
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