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Current File : /domains/highlandlabs/cqi-bin/ALFA_DATA/alfasymlink/root/usr/lib/libpmc.a
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NT_C1HEVENT_C2HEVENT_C3HEVENT_C4HEVENT_C5HEVENT_C6HEVENT_C7HEVENT_C8HEVENT_C9HEVENT_CAHEVENT_CBHEVENT_CCHEVENT_CDHEVENT_CEHEVENT_CFHEVENT_D0HEVENT_D1HEVENT_D2HEVENT_D3HEVENT_D4HEVENT_D5HEVENT_D6HEVENT_D7HEVENT_D8HEVENT_D9HEVENT_DAHEVENT_DBHEVENT_DCHEVENT_DDHEVENT_DEHEVENT_DFHEVENT_E0HEVENT_E1HEVENT_E2HEVENT_E3HEVENT_E4HEVENT_E5HEVENT_E6HEVENT_E7HEVENT_E8HEVENT_E9HEVENT_EAHEVENT_EBHEVENT_ECHEVENT_EDHEVENT_EEHEVENT_EFHEVENT_F0HEVENT_F1HEVENT_F2HEVENT_F3HEVENT_F4HEVENT_F5HEVENT_F6HEVENT_F7HEVENT_F8HEVENT_F9HEVENT_FAHEVENT_FBHEVENT_FCHEVENT_FDHEVENT_FEHEVENT_FFHJAVA_BYTECODESOFTWARE_JAVA_BYTECODEJAZELLE_BACKWARD_BRANCHCOHERENT_LINEFILL_MISSCCOHERENT_LINEFILL_HITCINSTR_CACHE_DEPENDENT_STALLDATA_CACHE_DEPENDENT_STALLMAIN_TLB_MISS_STALLSTREX_PASSEDSTREX_FAILEDDATA_EVICTIONISSUE_DNOT_DISPATCH_ANY_INSTRISSUE_IS_EMPTYINSTR_RENAMEDPREDICTABLE_FUNCTION_RETURNMAIN_EXECUTION_UNIT_PIPESECOND_EXECUTION_UNIT_PIPELOAD_STORE_PIPEFLOATING_POINT_INSTR_RENAMEDNEON_INSTRS_RENAMEDPLD_STALLWRITE_STALLINSTR_MAIN_TLB_MISS_STALLDATA_MAIN_TLB_MISS_STALLINSTR_MICRO_TLB_MISS_STALLDATA_MICRO_TLB_MISS_STALLDMB_STALLINTEGER_CORE_CLOCK_ENABLEDDATA_ENGINE_CLOCK_ENABLEDISBDSBDMBEXTERNAL_INTERRUPTPLE_CACHE_LINE_REQ_COMPLETEDPLE_CACHE_LINE_REQ_SKIPPEDPLE_FIFO_FLUSHPLE_REQUEST_COMPLETEDPLE_FIFO_OVERFLOWPLE_REQUEST_PROGRAMMEDSW_INCRL1I_CACHE_REFILLL1I_TLB_REFILLL1D_CACHE_REFILLL1D_CACHEL1D_TLB_REFILLINST_RETIREDEXC_RETURNCID_WRITE_RETIREDBR_MIS_PREDBR_PREDL1I_CACHEL1D_CACHE_WBL2D_CACHEL2D_CACHE_REFILLL2D_CACHE_WBMEMORY_ERRORCHAINBUS_ACCESS_LDBUS_ACCESS_STBR_INDIRECT_SPECEXC_IRQEXC_FIQLD_RETIREDST_RETIREDPC_WRITE_RETIREDBR_IMMED_RETIREDBR_RETURN_RETIREDUNALIGNED_LDST_RETIREDEVENT_100HEVENT_101HEVENT_102HEVENT_103HEVENT_104HEVENT_105HEVENT_106HEVENT_107HEVENT_108HEVENT_109HEVENT_10AHEVENT_10BHEVENT_10CHEVENT_10DHEVENT_10EHEVENT_10FHEVENT_110HEVENT_111HEVENT_112HEVENT_113HEVENT_114HEVENT_115HEVENT_116HEVENT_117HEVENT_118HEVENT_119HEVENT_11AHEVENT_11BHEVENT_11CHEVENT_11DHEVENT_11EHEVENT_11FHEVENT_120HEVENT_121HEVENT_122HEVENT_123HEVENT_124HEVENT_125HEVENT_126HEVENT_127HEVENT_128HEVENT_129HEVENT_12AHEVENT_12BHEVENT_12CHEVENT_12DHEVENT_12EHEVENT_12FHEVENT_130HEVENT_131HEVENT_132HEVENT_133HEVENT_134HEVENT_135HEVENT_136HEVENT_137HEVENT_138HEVENT_139HEVENT_13AHEVENT_13BHEVENT_13CHEVENT_13DHEVENT_13EHEVENT_13FHEVENT_140HEVENT_141HEVENT_142HEVENT_143HEVENT_144HEVENT_145HEVENT_146HEVENT_147HEVENT_148HEVENT_149HEVENT_14AHEVENT_14BHEVENT_14CHEVENT_14DHEVENT_14EHEVENT_14FHEVENT_150HEVENT_151HEVENT_152HEVENT_153HEVENT_154HEVENT_155HEVENT_156HEVENT_157HEVENT_158HEVENT_159HEVENT_15AHEVENT_15BHEVENT_15CHEVENT_15DHEVENT_15EHEVENT_15FHEVENT_160HEVENT_161HEVENT_162HEVENT_163HEVENT_164HEVENT_165HEVENT_166HEVENT_167HEVENT_168HEVENT_169HEVENT_16AHEVENT_16BHEVENT_16CHEVENT_16DHEVENT_16EHEVENT_16FHEVENT_170HEVENT_171HEVENT_172HEVENT_173HEVENT_174HEVENT_175HEVENT_176HEVENT_177HEVENT_178HEVENT_179HEVENT_17AHEVENT_17BHEVENT_17CHEVENT_17DHEVENT_17EHEVENT_17FHEVENT_180HEVENT_181HEVENT_182HEVENT_183HEVENT_184HEVENT_185HEVENT_186HEVENT_187HEVENT_188HEVENT_189HEVENT_18AHEVENT_18BHEVENT_18CHEVENT_18DHEVENT_18EHEVENT_18FHEVENT_190HEVENT_191HEVENT_192HEVENT_193HEVENT_194HEVENT_195HEVENT_196HEVENT_197HEVENT_198HEVENT_199HEVENT_19AHEVENT_19BHEVENT_19CHEVENT_19DHEVENT_19EHEVENT_19FHEVENT_1A0HEVENT_1A1HEVENT_1A2HEVENT_1A3HEVENT_1A4HEVENT_1A5HEVENT_1A6HEVENT_1A7HEVENT_1A8HEVENT_1A9HEVENT_1AAHEVENT_1ABHEVENT_1ACHEVENT_1ADHEVENT_1AEHEVENT_1AFHEVENT_1B0HEVENT_1B1HEVENT_1B2HEVENT_1B3HEVENT_1B4HEVENT_1B5HEVENT_1B6HEVENT_1B7HEVENT_1B8HEVENT_1B9HEVENT_1BAHEVENT_1BBHEVENT_1BCHEVENT_1BDHEVENT_1BEHEVENT_1BFHEVENT_1C0HEVENT_1C1HEVENT_1C2HEVENT_1C3HEVENT_1C4HEVENT_1C5HEVENT_1C6HEVENT_1C7HEVENT_1C8HEVENT_1C9HEVENT_1CAHEVENT_1CBHEVENT_1CCHEVENT_1CDHEVENT_1CEHEVENT_1CFHEVENT_1D0HEVENT_1D1HEVENT_1D2HEVENT_1D3HEVENT_1D4HEVENT_1D5HEVENT_1D6HEVENT_1D7HEVENT_1D8HEVENT_1D9HEVENT_1DAHEVENT_1DBHEVENT_1DCHEVENT_1DDHEVENT_1DEHEVENT_1DFHEVENT_1E0HEVENT_1E1HEVENT_1E2HEVENT_1E3HEVENT_1E4HEVENT_1E5HEVENT_1E6HEVENT_1E7HEVENT_1E8HEVENT_1E9HEVENT_1EAHEVENT_1EBHEVENT_1ECHEVENT_1EDHEVENT_1EEHEVENT_1EFHEVENT_1F0HEVENT_1F1HEVENT_1F2HEVENT_1F3HEVENT_1F4HEVENT_1F5HEVENT_1F6HEVENT_1F7HEVENT_1F8HEVENT_1F9HEVENT_1FAHEVENT_1FBHEVENT_1FCHEVENT_1FDHEVENT_1FEHEVENT_1FFHEVENT_200HEVENT_201HEVENT_202HEVENT_203HEVENT_204HEVENT_205HEVENT_206HEVENT_207HEVENT_208HEVENT_209HEVENT_20AHEVENT_20BHEVENT_20CHEVENT_20DHEVENT_20EHEVENT_20FHEVENT_210HEVENT_211HEVENT_212HEVENT_213HEVENT_214HEVENT_215HEVENT_216HEVENT_217HEVENT_218HEVENT_219HEVENT_21AHEVENT_21BHEVENT_21CHEVENT_21DHEVENT_21EHEVENT_21FHEVENT_220HEVENT_221HEVENT_222HEVENT_223HEVENT_224HEVENT_225HEVENT_226HEVENT_227HEVENT_228HEVENT_229HEVENT_22AHEVENT_22BHEVENT_22CHEVENT_22DHEVENT_22EHEVENT_22FHEVENT_230HEVENT_231HEVENT_232HEVENT_233HEVENT_234HEVENT_235HEVENT_236HEVENT_237HEVENT_238HEVENT_239HEVENT_23AHEVENT_23BHEVENT_23CHEVENT_23DHEVENT_23EHEVENT_23FHEVENT_240HEVENT_241HEVENT_242HEVENT_243HEVENT_244HEVENT_245HEVENT_246HEVENT_247HEVENT_248HEVENT_249HEVENT_24AHEVENT_24BHEVENT_24CHEVENT_24DHEVENT_24EHEVENT_24FHEVENT_250HEVENT_251HEVENT_252HEVENT_253HEVENT_254HEVENT_255HEVENT_256HEVENT_257HEVENT_258HEVENT_259HEVENT_25AHEVENT_25BHEVENT_25CHEVENT_25DHEVENT_25EHEVENT_25FHEVENT_260HEVENT_261HEVENT_262HEVENT_263HEVENT_264HEVENT_265HEVENT_266HEVENT_267HEVENT_268HEVENT_269HEVENT_26AHEVENT_26BHEVENT_26CHEVENT_26DHEVENT_26EHEVENT_26FHEVENT_270HEVENT_271HEVENT_272HEVENT_273HEVENT_274HEVENT_275HEVENT_276HEVENT_277HEVENT_278HEVENT_279HEVENT_27AHEVENT_27BHEVENT_27CHEVENT_27DHEVENT_27EHEVENT_27FHEVENT_280HEVENT_281HEVENT_282HEVENT_283HEVENT_284HEVENT_285HEVENT_286HEVENT_287HEVENT_288HEVENT_289HEVENT_28AHEVENT_28BHEVENT_28CHEVENT_28DHEVENT_28EHEVENT_28FHEVENT_290HEVENT_291HEVENT_292HEVENT_293HEVENT_294HEVENT_295HEVENT_296HEVENT_297HEVENT_298HEVENT_299HEVENT_29AHEVENT_29BHEVENT_29CHEVENT_29DHEVENT_29EHEVENT_29FHEVENT_2A0HEVENT_2A1HEVENT_2A2HEVENT_2A3HEVENT_2A4HEVENT_2A5HEVENT_2A6HEVENT_2A7HEVENT_2A8HEVENT_2A9HEVENT_2AAHEVENT_2ABHEVENT_2ACHEVENT_2ADHEVENT_2AEHEVENT_2AFHEVENT_2B0HEVENT_2B1HEVENT_2B2HEVENT_2B3HEVENT_2B4HEVENT_2B5HEVENT_2B6HEVENT_2B7HEVENT_2B8HEVENT_2B9HEVENT_2BAHEVENT_2BBHEVENT_2BCHEVENT_2BDHEVENT_2BEHEVENT_2BFHEVENT_2C0HEVENT_2C1HEVENT_2C2HEVENT_2C3HEVENT_2C4HEVENT_2C5HEVENT_2C6HEVENT_2C7HEVENT_2C8HEVENT_2C9HEVENT_2CAHEVENT_2CBHEVENT_2CCHEVENT_2CDHEVENT_2CEHEVENT_2CFHEVENT_2D0HEVENT_2D1HEVENT_2D2HEVENT_2D3HEVENT_2D4HEVENT_2D5HEVENT_2D6HEVENT_2D7HEVENT_2D8HEVENT_2D9HEVENT_2DAHEVENT_2DBHEVENT_2DCHEVENT_2DDHEVENT_2DEHEVENT_2DFHEVENT_2E0HEVENT_2E1HEVENT_2E2HEVENT_2E3HEVENT_2E4HEVENT_2E5HEVENT_2E6HEVENT_2E7HEVENT_2E8HEVENT_2E9HEVENT_2EAHEVENT_2EBHEVENT_2ECHEVENT_2EDHEVENT_2EEHEVENT_2EFHEVENT_2F0HEVENT_2F1HEVENT_2F2HEVENT_2F3HEVENT_2F4HEVENT_2F5HEVENT_2F6HEVENT_2F7HEVENT_2F8HEVENT_2F9HEVENT_2FAHEVENT_2FBHEVENT_2FCHEVENT_2FDHEVENT_2FEHEVENT_2FFHEVENT_300HEVENT_301HEVENT_302HEVENT_303HEVENT_304HEVENT_305HEVENT_306HEVENT_307HEVENT_308HEVENT_309HEVENT_30AHEVENT_30BHEVENT_30CHEVENT_30DHEVENT_30EHEVENT_30FHEVENT_310HEVENT_311HEVENT_312HEVENT_313HEVENT_314HEVENT_315HEVENT_316HEVENT_317HEVENT_318HEVENT_319HEVENT_31AHEVENT_31BHEVENT_31CHEVENT_31DHEVENT_31EHEVENT_31FHEVENT_320HEVENT_321HEVENT_322HEVENT_323HEVENT_324HEVENT_325HEVENT_326HEVENT_327HEVENT_328HEVENT_329HEVENT_32AHEVENT_32BHEVENT_32CHEVENT_32DHEVENT_32EHEVENT_32FHEVENT_330HEVENT_331HEVENT_332HEVENT_333HEVENT_334HEVENT_335HEVENT_336HEVENT_337HEVENT_338HEVENT_339HEVENT_33AHEVENT_33BHEVENT_33CHEVENT_33DHEVENT_33EHEVENT_33FHEVENT_340HEVENT_341HEVENT_342HEVENT_343HEVENT_344HEVENT_345HEVENT_346HEVENT_347HEVENT_348HEVENT_349HEVENT_34AHEVENT_34BHEVENT_34CHEVENT_34DHEVENT_34EHEVENT_34FHEVENT_350HEVENT_351HEVENT_352HEVENT_353HEVENT_354HEVENT_355HEVENT_356HEVENT_357HEVENT_358HEVENT_359HEVENT_35AHEVENT_35BHEVENT_35CHEVENT_35DHEVENT_35EHEVENT_35FHEVENT_360HEVENT_361HEVENT_362HEVENT_363HEVENT_364HEVENT_365HEVENT_366HEVENT_367HEVENT_368HEVENT_369HEVENT_36AHEVENT_36BHEVENT_36CHEVENT_36DHEVENT_36EHEVENT_36FHEVENT_370HEVENT_371HEVENT_372HEVENT_373HEVENT_374HEVENT_375HEVENT_376HEVENT_377HEVENT_378HEVENT_379HEVENT_37AHEVENT_37BHEVENT_37CHEVENT_37DHEVENT_37EHEVENT_37FHEVENT_380HEVENT_381HEVENT_382HEVENT_383HEVENT_384HEVENT_385HEVENT_386HEVENT_387HEVENT_388HEVENT_389HEVENT_38AHEVENT_38BHEVENT_38CHEVENT_38DHEVENT_38EHEVENT_38FHEVENT_390HEVENT_391HEVENT_392HEVENT_393HEVENT_394HEVENT_395HEVENT_396HEVENT_397HEVENT_398HEVENT_399HEVENT_39AHEVENT_39BHEVENT_39CHEVENT_39DHEVENT_39EHEVENT_39FHEVENT_3A0HEVENT_3A1HEVENT_3A2HEVENT_3A3HEVENT_3A4HEVENT_3A5HEVENT_3A6HEVENT_3A7HEVENT_3A8HEVENT_3A9HEVENT_3AAHEVENT_3ABHEVENT_3ACHEVENT_3ADHEVENT_3AEHEVENT_3AFHEVENT_3B0HEVENT_3B1HEVENT_3B2HEVENT_3B3HEVENT_3B4HEVENT_3B5HEVENT_3B6HEVENT_3B7HEVENT_3B8HEVENT_3B9HEVENT_3BAHEVENT_3BBHEVENT_3BCHEVENT_3BDHEVENT_3BEHEVENT_3BFHEVENT_3C0HEVENT_3C1HEVENT_3C2HEVENT_3C3HEVENT_3C4HEVENT_3C5HEVENT_3C6HEVENT_3C7HEVENT_3C8HEVENT_3C9HEVENT_3CAHEVENT_3CBHEVENT_3CCHEVENT_3CDHEVENT_3CEHEVENT_3CFHEVENT_3D0HEVENT_3D1HEVENT_3D2HEVENT_3D3HEVENT_3D4HEVENT_3D5HEVENT_3D6HEVENT_3D7HEVENT_3D8HEVENT_3D9HEVENT_3DAHEVENT_3DBHEVENT_3DCHEVENT_3DDHEVENT_3DEHEVENT_3DFHEVENT_3E0HEVENT_3E1HEVENT_3E2HEVENT_3E3HEVENT_3E4HEVENT_3E5HEVENT_3E6HEVENT_3E7HEVENT_3E8HEVENT_3E9HEVENT_3EAHEVENT_3EBHEVENT_3ECHEVENT_3EDHEVENT_3EEHEVENT_3EFHEVENT_3F0HEVENT_3F1HEVENT_3F2HEVENT_3F3HEVENT_3F4HEVENT_3F5HEVENT_3F6HEVENT_3F7HEVENT_3F8HEVENT_3F9HEVENT_3FAHEVENT_3FBHEVENT_3FCHEVENT_3FDHEVENT_3FEHEVENT_3FFHINST_SPECTTBR_WRITE_RETIREDL1D_CACHE_LDL1D_CACHE_STL1D_CACHE_REFILL_LDL1D_CACHE_REFILL_STL1D_CACHE_WB_VICTIML1D_CACHE_WB_CLEANL1D_CACHE_INVALL1D_TLB_REFILL_LDL1D_TLB_REFILL_STL2D_CACHE_LDL2D_CACHE_STL2D_CACHE_REFILL_LDL2D_CACHE_REFILL_STL2D_CACHE_WB_VICTIML2D_CACHE_WB_CLEANL2D_CACHE_INVALMEM_ACCESS_LDMEM_ACCESS_STUNALIGNED_LD_SPECUNALIGNED_ST_SPECUNALIGNED_LDST_SPECLDREX_SPECSTREX_PASS_SPECSTREX_FAIL_SPECLD_SPECST_SPECLDST_SPECDP_SPECASE_SPECVFP_SPECPC_WRITE_SPECCRYPTO_SPECBR_IMMED_SPECBR_RETURN_SPECISB_SPECDSB_SPECDMB_SPECEXC_UNDEFEXC_SVCEXC_PABORTEXC_DABORTEXC_SMCEXC_HVCEXC_TRAP_PABORTEXC_TRAP_DABORTEXC_TRAP_OTHEREXC_TRAP_IRQEXC_TRAP_FIQRC_LD_SPECRC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ELF	>HYb@@GenuineIntel-6-56v5coreGenuineIntel-6-3Dv17GenuineIntel-6-47GenuineIntel-6-4Fv10GenuineIntel-6-1Cv4GenuineIntel-6-26GenuineIntel-6-27GenuineIntel-6-36GenuineIntel-6-35GenuineIntel-6-5Cv8GenuineIntel-6-5FGenuineIntel-6-7Av1GenuineIntel-6-3Cv24GenuineIntel-6-45GenuineIntel-6-46GenuineIntel-6-3FGenuineIntel-6-3Av18GenuineIntel-6-3Ev19GenuineIntel-6-2Dv20GenuineIntel-6-57v9GenuineIntel-6-85GenuineIntel-6-1Ev2GenuineIntel-6-1FGenuineIntel-6-1AGenuineIntel-6-2EGenuineIntel-6-[4589]EGenuineIntel-6-A[56]GenuineIntel-6-37v13GenuineIntel-6-4DGenuineIntel-6-4CGenuineIntel-6-2Av15GenuineIntel-6-2CGenuineIntel-6-25GenuineIntel-6-2FGenuineIntel-6-55-[01234]GenuineIntel-6-55-[56789ABCDEF]GenuineIntel-6-7DGenuineIntel-6-7EGenuineIntel-6-8[CD]GenuineIntel-6-A7GenuineIntel-6-6AGenuineIntel-6-6CGenuineIntel-6-86GenuineIntel-6-96GenuineIntel-6-97GenuineIntel-6-9AGenuineIntel-6-8FAuthenticAMD-23-[012][0-9A-F]AuthenticAMD-23-[[:xdigit:]]+AuthenticAMD-25-[0245][[:xdigit:]]AuthenticAMD-25-[[:xdigit:]]+HygonGenuine-24-00testcpupme_test_soc_sysThis category represents fraction of slots where the processor's Frontend undersupplies its Backendbdwde metricsThis category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend BoundIDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)Frontend_BoundTopdownL1This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPUThis category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPUIDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))Frontend_Bound_SMTTopdownL1_SMTThis category represents fraction of slots wasted due to incorrect speculationsThis category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)Bad_SpeculationThis category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPUThis category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))Bad_Speculation_SMTThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the BackendThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )Backend_BoundNO_NMI_WATCHDOGThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPUThis category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )Backend_Bound_SMTThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retiredThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoidedUOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)RetiringThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPUThis category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPUUOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))Retiring_SMTInstructions Per Cycle (per Logical Processor)INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREADIPCRet;SummaryUops Per InstructionUOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANYUPIPipeline;Ret;RetireInstruction per taken branchUOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKENUpTBBranches;Fed;FetchBWCycles Per Instruction (per Logical Processor)1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)CPIPipeline;MemPer-Logical Processor actual clocks when the Logical Processor is activeCPU_CLK_UNHALTED.THREADCLKSPipelineTotal issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)4 * CPU_CLK_UNHALTED.THREADSLOTSTmaL14 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )SLOTS_SMTTmaL1_SMTThe ratio of Executed- by Issued-UopsThe ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of "execute" at rename stageUOPS_EXECUTED.THREAD / UOPS_ISSUED.ANYExecute_per_IssueCor;PipelineInstructions Per Cycle across hyper-threads (per physical core)CoreIPCRet;SMT;TmaL1INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )CoreIPC_SMTRet;SMT;TmaL1_SMTFloating Point Operations Per Cycle( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREADFLOPcRet;Flops( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )FLOPc_SMTRet;Flops_SMTActual per-core usage of the Floating Point execution units (regardless of the vector width)Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )FP_Arith_UtilizationCor;Flops;HPCActual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPUActual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )FP_Arith_Utilization_SMTCor;Flops;HPC_SMTInstruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)ILPBackend;Cor;Pipeline;PortsUtilBranch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHESBranch_Misprediction_CostBad;BrMispredicts( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHESBranch_Misprediction_Cost_SMTBad;BrMispredicts_SMTNumber of Instructions per non-speculative Branch Misprediction (JEClear)INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHESIpMispredictBad;BadSpec;BrMispredictsCore actual clocks when any Logical Processor is active on the Physical Core( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )CORE_CLKSSMTInstructions per Load (lower number means higher occurrence rate)INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADSIpLoadInsTypeInstructions per Store (lower number means higher occurrence rate)INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORESIpStoreInstructions per Branch (lower number means higher occurrence rate)INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHESIpBranchBranches;Fed;InsTypeInstructions per (near) call (lower number means higher occurrence rate)INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALLIpCallBranches;Fed;PGOINST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKENIpTBBranches;Fed;FetchBW;Frontend;PGOBranch instructions per taken branchBR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKENBpTkBranchInstructions per Floating Point (FP) Operation (lower number means higher occurrence rate)INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )IpFLOPFlops;InsTypeInstructions per FP Arithmetic instruction (lower number means higher occurrence rate)Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDWINST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )IpArithInstructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double countingINST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLEIpArith_Scalar_SPFlops;FpScalar;InsTypeInstructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double countingINST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLEIpArith_Scalar_DPInstructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double countingINST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )IpArith_AVX128Flops;FpVector;InsTypeInstructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double countingINST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )IpArith_AVX256Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DISTINST_RETIRED.ANYInstructionsSummary;TmaL1Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )DSB_CoverageDSB;Fed;FetchBWActual Average Latency for L1 data-cache miss demand load instructions (in core cycles)Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat stringsL1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )Load_Miss_Real_LatencyMem;MemoryBound;MemoryLatMemory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLESMLPMem;MemoryBound;MemoryBWAverage data fill bandwidth to the L1 data cache [GB / sec]64 * L1D.REPLACEMENT / 1000000000 / duration_timeL1D_Cache_Fill_BWMem;MemoryBWAverage data fill bandwidth to the L2 cache [GB / sec]64 * L2_LINES_IN.ALL / 1000000000 / duration_timeL2_Cache_Fill_BWAverage per-core data fill bandwidth to the L3 cache [GB / sec]64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_timeL3_Cache_Fill_BWL1 cache true misses per kilo instruction for retired demand loads1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANYL1MPKIMem;CacheMissesL2 cache true misses per kilo instruction for retired demand loads1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANYL2MPKIMem;Backend;CacheMissesL2 cache misses per kilo instruction for all request types (including speculative)1000 * L2_RQSTS.MISS / INST_RETIRED.ANYL2MPKI_AllMem;CacheMisses;OffcoreL2 cache misses per kilo instruction for all demand loads  (including speculative)1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANYL2MPKI_LoadL2 cache hits per kilo instruction for all request types (including speculative)1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANYL2HPKI_AllL2 cache hits per kilo instruction for all demand loads  (including speculative)1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANYL2HPKI_LoadL3 cache true misses per kilo instruction for retired demand loads1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANYL3MPKIUtilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses( cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CPU_CLK_UNHALTED.THREADPage_Walks_UtilizationMem;MemoryTLB( cpu@ITLB_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\,cmask\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\,cmask\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )Page_Walks_Utilization_SMTMem;MemoryTLB_SMTAverage CPU UtilizationCPU_CLK_UNHALTED.REF_TSC / msr@tsc@CPU_UtilizationHPC;SummaryMeasured Average Frequency for unhalted processors [GHz](CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_timeAverage_FrequencySummary;PowerGiga Floating Point Operations Per Second( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_timeGFLOPsAverage Frequency Utilization relative nominal frequencyCPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSCTurbo_UtilizationPowerFraction of cycles where both hardware Logical Processors were active1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0SMT_2T_UtilizationFraction of cycles spent in the Operating System (OS) Kernel modeCPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREADKernel_UtilizationOSCycles Per Instruction for the Operating System (OS) Kernel modeCPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:kKernel_CPIAverage external Memory Bandwidth Use for reads and writes [GB / sec]( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_timeDRAM_BW_UseHPC;Mem;MemoryBW;SoCAverage latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches1000000000 * ( cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x35\,umask\=0x3\,filter_opc\=0x182@ ) / ( cbox_0@event\=0x0@ / duration_time )MEM_Read_LatencyMem;MemoryLat;SoCAverage number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetchescbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182\,thresh\=1@MEM_Parallel_ReadsMem;MemoryBW;SoCSocket actual clocks when any core is active on that socketcbox_0@event\=0x0@Socket_CLKSSoCInstructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:uIpFarBranchBranches;OSC3 residency percent per core(cstate_core@c3\-residency@ / msr@tsc@) * 100C3_Core_ResidencyC6 residency percent per core(cstate_core@c6\-residency@ / msr@tsc@) * 100C6_Core_ResidencyC7 residency percent per core(cstate_core@c7\-residency@ / msr@tsc@) * 100C7_Core_ResidencyC2 residency percent per package(cstate_pkg@c2\-residency@ / msr@tsc@) * 100C2_Pkg_ResidencyC3 residency percent per package(cstate_pkg@c3\-residency@ / msr@tsc@) * 100C3_Pkg_ResidencyC6 residency percent per package(cstate_pkg@c6\-residency@ / msr@tsc@) * 100C6_Pkg_ResidencyC7 residency percent per package(cstate_pkg@c7\-residency@ / msr@tsc@) * 100C7_Pkg_Residencyl1d.replacementevent=0x51,period=2000003,umask=0x1L1D data line replacementscacheThis event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replacel1d_pend_miss.fb_fullevent=0x48,cmask=1,period=2000003,umask=0x2Cycles a demand request was blocked due to Fill Buffers inavailabilityl1d_pend_miss.pendingevent=0x48,period=2000003,umask=0x1L1D miss oustandings duration in cyclesThis event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.
Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request typel1d_pend_miss.pending_cyclesevent=0x48,cmask=1,period=2000003,umask=0x1Cycles with L1D load Misses outstandingThis event counts duration of L1D miss outstanding in cyclesl1d_pend_miss.pending_cycles_anyevent=0x48,any=1,cmask=1,period=2000003,umask=0x1Cycles with L1D load Misses outstanding from any thread on physical corel2_demand_rqsts.wb_hitevent=0x27,period=200003,umask=0x50Not rejected writebacks that hit L2 cacheThis event counts the number of WB requests that hit L2 cachel2_lines_in.allevent=0xf1,period=100003,umask=0x7L2 cache lines filling L2This event counts the number of L2 cache lines filling the L2. Counting does not cover rejectsl2_lines_in.eevent=0xf1,period=100003,umask=0x4L2 cache lines in E state filling L2This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejectsl2_lines_in.ievent=0xf1,period=100003,umask=0x1L2 cache lines in I state filling L2This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejectsl2_lines_in.sevent=0xf1,period=100003,umask=0x2L2 cache lines in S state filling L2This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejectsl2_lines_out.demand_cleanevent=0xf2,period=100003,umask=0x5Clean L2 cache lines evicted by demandl2_rqsts.all_code_rdevent=0x24,period=200003,umask=0xe4L2 code requestsThis event counts the total number of L2 code requestsl2_rqsts.all_demand_data_rdevent=0x24,period=200003,umask=0xe1Demand Data Read requestsThis event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are countedl2_rqsts.all_demand_missevent=0x24,period=200003,umask=0x27Demand requests that miss L2 cachel2_rqsts.all_demand_referencesevent=0x24,period=200003,umask=0xe7Demand requests to L2 cachel2_rqsts.all_pfevent=0x24,period=200003,umask=0xf8Requests from L2 hardware prefetchersThis event counts the total number of requests from the L2 hardware prefetchersl2_rqsts.all_rfoevent=0x24,period=200003,umask=0xe2RFO requests to L2 cacheThis event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetchesl2_rqsts.code_rd_hitevent=0x24,period=200003,umask=0x44L2 cache hits when fetching instructions, code readsl2_rqsts.code_rd_missevent=0x24,period=200003,umask=0x24L2 cache misses when fetching instructionsl2_rqsts.demand_data_rd_hitevent=0x24,period=200003,umask=0x41Demand Data Read requests that hit L2 cacheThis event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are countedl2_rqsts.demand_data_rd_missevent=0x24,period=200003,umask=0x21Demand Data Read miss L2, no rejectsThis event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are countedl2_rqsts.l2_pf_hitevent=0x24,period=200003,umask=0x50L2 prefetch requests that hit L2 cacheThis event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new typesl2_rqsts.l2_pf_missevent=0x24,period=200003,umask=0x30L2 prefetch requests that miss L2 cacheThis event counts the number of requests from the L2 hardware prefetchers that miss L2 cachel2_rqsts.missevent=0x24,period=200003,umask=0x3fAll requests that miss L2 cachel2_rqsts.referencesevent=0x24,period=200003,umask=0xffAll L2 requestsl2_rqsts.rfo_hitevent=0x24,period=200003,umask=0x42RFO requests that hit L2 cachel2_rqsts.rfo_missevent=0x24,period=200003,umask=0x22RFO requests that miss L2 cachel2_trans.all_pfevent=0xf0,period=200003,umask=0x8L2 or L3 HW prefetches that access L2 cacheThis event counts L2 or L3 HW prefetches that access L2 cache including rejectsl2_trans.all_requestsevent=0xf0,period=200003,umask=0x80Transactions accessing L2 pipeThis event counts transactions that access the L2 pipe including snoops, pagewalks, and so onl2_trans.code_rdevent=0xf0,period=200003,umask=0x4L2 cache accesses when fetching instructionsThis event counts the number of L2 cache accesses when fetching instructionsl2_trans.demand_data_rdevent=0xf0,period=200003,umask=0x1Demand Data Read requests that access L2 cacheThis event counts Demand Data Read requests that access L2 cache, including rejectsl2_trans.l1d_wbevent=0xf0,period=200003,umask=0x10L1D writebacks that access L2 cacheThis event counts L1D writebacks that access L2 cachel2_trans.l2_fillevent=0xf0,period=200003,umask=0x20L2 fill requests that access L2 cacheThis event counts L2 fill requests that access L2 cachel2_trans.l2_wbevent=0xf0,period=200003,umask=0x40L2 writebacks that access L2 cacheThis event counts L2 writebacks that access L2 cachel2_trans.rfoevent=0xf0,period=200003,umask=0x2RFO requests that access L2 cacheThis event counts Read for Ownership (RFO) requests that access L2 cachelock_cycles.cache_lock_durationevent=0x63,period=2000003,umask=0x2Cycles when L1D is lockedThis event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION)longest_lat_cache.missevent=0x2e,period=100003,umask=0x41Core-originated cacheable demand requests missed L3This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFUlongest_lat_cache.referenceevent=0x2e,period=100003,umask=0x4fCore-originated cacheable demand requests that refer to L3This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFUmem_load_uops_l3_hit_retired.xsnp_hitevent=0xd2,period=20011,umask=0x2Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_l3_hit_retired.xsnp_hitmevent=0xd2,period=20011,umask=0x4Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3)  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_l3_hit_retired.xsnp_missevent=0xd2,period=20011,umask=0x1Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_l3_hit_retired.xsnp_noneevent=0xd2,period=100003,umask=0x8Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_l3_miss_retired.local_dramevent=0xd3,period=100007,umask=0x1(null)This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event  Supports address when precise.  Spec update: BDE70, BDM100mem_load_uops_l3_miss_retired.remote_dramevent=0xd3,period=100007,umask=0x4Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)  Supports address when precise.  Spec update: BDE70mem_load_uops_l3_miss_retired.remote_fwdevent=0xd3,period=100007,umask=0x20Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)  Supports address when precise.  Spec update: BDE70mem_load_uops_l3_miss_retired.remote_hitmevent=0xd3,period=100007,umask=0x10Retired load uop whose Data Source was: Remote cache HITM (Precise Event)  Supports address when precise.  Spec update: BDE70mem_load_uops_retired.hit_lfbevent=0xd1,period=100003,umask=0x40Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load  Supports address when precise (Precise event)mem_load_uops_retired.l1_hitevent=0xd1,period=2000003,umask=0x1Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source  Supports address when precise (Precise event)mem_load_uops_retired.l1_missevent=0xd1,period=100003,umask=0x8Retired load uops misses in L1 cache as data sources. Uses PEBS  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)mem_load_uops_retired.l2_hitevent=0xd1,period=100003,umask=0x2Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM35 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache  Supports address when precise.  Spec update: BDM35 (Precise event)mem_load_uops_retired.l2_missevent=0xd1,period=50021,umask=0x10Retired load uops with L2 cache misses as data sources. Uses PEBS  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)mem_load_uops_retired.l3_hitevent=0xd1,period=50021,umask=0x4Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)mem_load_uops_retired.l3_missevent=0xd1,period=100007,umask=0x20Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM100, BDE70 (Precise event)mem_uops_retired.all_loadsevent=0xd0,period=2000003,umask=0x81All retired load uops. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches  Supports address when precise (Precise event)mem_uops_retired.all_storesevent=0xd0,period=2000003,umask=0x82Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement  Supports address when precise (Precise event)mem_uops_retired.lock_loadsevent=0xd0,period=100007,umask=0x21Retired load uops with locked access. (Precise Event - PEBS)  Supports address when precise.  Spec update: BDM35 (Precise event)This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path  Supports address when precise.  Spec update: BDM35 (Precise event)mem_uops_retired.split_loadsevent=0xd0,period=100003,umask=0x41Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)mem_uops_retired.split_storesevent=0xd0,period=100003,umask=0x42This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)mem_uops_retired.stlb_miss_loadsevent=0xd0,period=100003,umask=0x11Retired load uops that miss the STLB. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)mem_uops_retired.stlb_miss_storesevent=0xd0,period=100003,umask=0x12Retired store uops that miss the STLB. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)offcore_requests.all_data_rdevent=0xb0,period=100003,umask=0x8Demand and prefetch data readsThis event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request typeoffcore_requests.demand_code_rdevent=0xb0,period=100003,umask=0x2Cacheable and noncachaeble code read requestsThis event counts both cacheable and noncachaeble code read requestsoffcore_requests.demand_data_rdevent=0xb0,period=100003,umask=0x1Demand Data Read requests sent to uncoreThis event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncoreoffcore_requests.demand_rfoevent=0xb0,period=100003,umask=0x4Demand RFO requests including regular RFOs, locks, ItoMThis event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoMoffcore_requests_buffer.sq_fullevent=0xb2,period=2000003,umask=0x1Offcore requests buffer cannot take more entries for this thread coreThis event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.
Note: Writeback pending FIFO has six entriesoffcore_requests_outstanding.all_data_rdevent=0x60,period=2000003,umask=0x8Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_requests_outstanding.cycles_with_data_rdevent=0x60,cmask=1,period=2000003,umask=0x8Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_requests_outstanding.cycles_with_demand_data_rdevent=0x60,cmask=1,period=2000003,umask=0x1Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation)  Spec update: BDM76offcore_requests_outstanding.cycles_with_demand_rfoevent=0x60,cmask=1,period=2000003,umask=0x4Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: BDM76This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_requests_outstanding.demand_code_rdevent=0x60,period=2000003,umask=0x2Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: BDM76This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_requests_outstanding.demand_data_rdevent=0x60,period=2000003,umask=0x1Offcore outstanding Demand Data Read transactions in uncore queue  Spec update: BDM76This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.
Note: A prefetch promoted to Demand is counted from the promotion point  Spec update: BDM76offcore_requests_outstanding.demand_data_rd_ge_6event=0x60,cmask=6,period=2000003,umask=0x1Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue  Spec update: BDM76offcore_requests_outstanding.demand_rfoevent=0x60,period=2000003,umask=0x4Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore  Spec update: BDM76This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS  Spec update: BDM76offcore_responseevent=0xb7,period=100003,umask=0x1Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transactionsq_misc.split_lockevent=0xf4,period=100003,umask=0x10Split locks in SQThis event counts the number of split locks in the super queuefp_arith_inst_retired.128b_packed_doubleevent=0xc7,period=2000003,umask=0x4Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfloating pointfp_arith_inst_retired.128b_packed_singleevent=0xc7,period=2000003,umask=0x8Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.256b_packed_doubleevent=0xc7,period=2000003,umask=0x10Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.256b_packed_singleevent=0xc7,period=2000003,umask=0x20Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.doubleevent=0xc7,period=2000006,umask=0x15Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?fp_arith_inst_retired.packedevent=0xc7,period=2000004,umask=0x3cNumber of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.scalarevent=0xc7,period=2000003,umask=0x3Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.scalar_doubleevent=0xc7,period=2000003,umask=0x1Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.scalar_singleevent=0xc7,period=2000003,umask=0x2Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.singleevent=0xc7,period=2000005,umask=0x2aNumber of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?fp_assist.anyevent=0xca,cmask=1,period=100003,umask=0x1eCycles with any input/output SSE or FP assistThis event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1fp_assist.simd_inputevent=0xca,period=100003,umask=0x10Number of SIMD FP assists due to input valuesThis event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist interventionfp_assist.simd_outputevent=0xca,period=100003,umask=0x8Number of SIMD FP assists due to Output valuesThis event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist interventionfp_assist.x87_inputevent=0xca,period=100003,umask=0x4Number of X87 assists due to input valueThis event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalidfp_assist.x87_outputevent=0xca,period=100003,umask=0x2Number of X87 assists due to output valueThis event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalidmove_elimination.simd_eliminatedevent=0x58,period=1000003,umask=0x2Number of SIMD Move Elimination candidate uops that were eliminatedmove_elimination.simd_not_eliminatedevent=0x58,period=1000003,umask=0x8Number of SIMD Move Elimination candidate uops that were not eliminatedother_assists.avx_to_sseevent=0xc1,period=100003,umask=0x8Number of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: BDM30This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable  Spec update: BDM30other_assists.sse_to_avxevent=0xc1,period=100003,umask=0x10Number of transitions from SSE to AVX-256 when penalty applicable  Spec update: BDM30This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable  Spec update: BDM30uop_dispatches_cancelled.simd_prfevent=0xa0,period=2000003,umask=0x3Micro-op dispatches cancelled due to insufficient SIMD physical register file read portsThis event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more informationbaclears.anyevent=0xe6,period=100003,umask=0x1fCounts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front endfrontenddsb2mite_switches.penalty_cyclesevent=0xab,period=2000003,umask=0x2Decode Stream Buffer (DSB)-to-MITE switch true penalty cyclesThis event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. 
MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.
Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cyclesicache.hitevent=0x80,period=2000003,umask=0x1Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetchesThis event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetchesicache.ifdata_stallevent=0x80,period=2000003,umask=0x4Cycles where a code fetch is stalled due to L1 instruction-cache missThis event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit)icache.missesevent=0x80,period=200003,umask=0x2Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accessesThis event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accessesidq.all_dsb_cycles_4_uopsevent=0x79,cmask=4,period=2000003,umask=0x18Cycles Decode Stream Buffer (DSB) is delivering 4 UopsThis event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQidq.all_dsb_cycles_any_uopsevent=0x79,cmask=1,period=2000003,umask=0x18Cycles Decode Stream Buffer (DSB) is delivering any UopThis event counts the number of cycles  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQidq.all_mite_cycles_4_uopsevent=0x79,cmask=4,period=2000003,umask=0x24Cycles MITE is delivering 4 UopsThis event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)idq.all_mite_cycles_any_uopsevent=0x79,cmask=1,period=2000003,umask=0x24Cycles MITE is delivering any UopThis event counts the number of cycles  uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)idq.dsb_cyclesevent=0x79,cmask=1,period=2000003,umask=0x8Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathThis event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQidq.dsb_uopsevent=0x79,period=2000003,umask=0x8Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathThis event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQidq.emptyevent=0x79,period=2000003,umask=0x2Instruction Decode Queue (IDQ) empty cyclesThis counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is emptyidq.mite_all_uopsevent=0x79,period=2000003,umask=0x3cUops delivered to Instruction Decode Queue (IDQ) from MITE pathThis event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)idq.mite_cyclesevent=0x79,cmask=1,period=2000003,umask=0x4Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE pathThis event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQidq.mite_uopsevent=0x79,period=2000003,umask=0x4idq.ms_cyclesevent=0x79,cmask=1,period=2000003,umask=0x30Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITEidq.ms_dsb_cyclesevent=0x79,cmask=1,period=2000003,umask=0x10Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQidq.ms_dsb_occurevent=0x79,cmask=1,edge=1,period=2000003,umask=0x10Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busyThis event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQidq.ms_dsb_uopsevent=0x79,period=2000003,umask=0x10Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQidq.ms_mite_uopsevent=0x79,period=2000003,umask=0x20Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQidq.ms_switchesevent=0x79,cmask=1,edge=1,period=2000003,umask=0x30Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequenceridq.ms_uopsevent=0x79,period=2000003,umask=0x30Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busyThis event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITEidq_uops_not_delivered.coreevent=0x9c,period=2000003,umask=0x1Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalledThis event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:
 a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;
 b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); 
 c. Instruction Decode Queue (IDQ) delivers four uopsidq_uops_not_delivered.cycles_0_uops_deliv.coreevent=0x9c,cmask=4,period=2000003,umask=0x1Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalledThis event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4idq_uops_not_delivered.cycles_fe_was_okevent=0x9c,cmask=1,inv=1,period=2000003,umask=0x1Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FEidq_uops_not_delivered.cycles_le_1_uop_deliv.coreevent=0x9c,cmask=3,period=2000003,umask=0x1Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalledThis event counts, on the per-thread basis, cycles when less than 1 uop is  delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3idq_uops_not_delivered.cycles_le_2_uop_deliv.coreevent=0x9c,cmask=2,period=2000003,umask=0x1Cycles with less than 2 uops delivered by the front endidq_uops_not_delivered.cycles_le_3_uop_deliv.coreevent=0x9c,cmask=1,period=2000003,umask=0x1Cycles with less than 3 uops delivered by the front endhle_retired.abortedevent=0xc8,period=2000003,umask=0x4Number of times HLE abort was triggered (PEBS) (Precise event)memoryhle_retired.aborted_misc1event=0xc8,period=2000003,umask=0x8Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts)Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details)hle_retired.aborted_misc2event=0xc8,period=2000003,umask=0x10Number of times an HLE execution aborted due to uncommon conditionsNumber of times the TSX watchdog signaled an HLE aborthle_retired.aborted_misc3event=0xc8,period=2000003,umask=0x20Number of times an HLE execution aborted due to HLE-unfriendly instructionsNumber of times a disallowed operation caused an HLE aborthle_retired.aborted_misc4event=0xc8,period=2000003,umask=0x40Number of times an HLE execution aborted due to incompatible memory typeNumber of times HLE caused a faulthle_retired.aborted_misc5event=0xc8,period=2000003,umask=0x80Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)Number of times HLE aborted and was not due to the abort conditions in subevents 3-6hle_retired.commitevent=0xc8,period=2000003,umask=0x2Number of times HLE commit succeededhle_retired.startevent=0xc8,period=2000003,umask=0x1Number of times we entered an HLE region; does not count nested transactionsNumber of times we entered an HLE region
 does not count nested transactionsmachine_clears.memory_orderingevent=0xc3,period=100003,umask=0x2Counts the number of machine clears due to memory order conflictsThis event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:
1. memory disambiguation,
2. external snoop, or
3. cross SMT-HW-thread snoop (stores) hitting load buffermem_trans_retired.load_latency_gt_128event=0xcd,period=1009,umask=0x1,ldlat=0x80Loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 128  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_16event=0xcd,period=20011,umask=0x1,ldlat=0x10Loads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 16  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_256event=0xcd,period=503,umask=0x1,ldlat=0x100Loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 256  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_32event=0xcd,period=100007,umask=0x1,ldlat=0x20Loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 32  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_4event=0xcd,period=100003,umask=0x1,ldlat=0x4Loads with latency value being above 4  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above four  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_512event=0xcd,period=101,umask=0x1,ldlat=0x200Loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 512  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_64event=0xcd,period=2003,umask=0x1,ldlat=0x40Loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above 64  Spec update: BDM100, BDM35 (Must be precise)mem_trans_retired.load_latency_gt_8event=0xcd,period=50021,umask=0x1,ldlat=0x8Loads with latency value being above 8  Spec update: BDM100, BDM35 (Must be precise)This event counts loads with latency value being above eight  Spec update: BDM100, BDM35 (Must be precise)misalign_mem_ref.loadsevent=0x5,period=2000003,umask=0x1Speculative cache line split load uops dispatched to L1 cacheThis event counts speculative cache-line split load uops dispatched to the L1 cachemisalign_mem_ref.storesevent=0x5,period=2000003,umask=0x2Speculative cache line split STA uops dispatched to L1 cacheThis event counts speculative cache line split store-address (STA) uops dispatched to the L1 cachertm_retired.abortedevent=0xc9,period=2000003,umask=0x4Number of times RTM abort was triggered (PEBS) (Precise event)rtm_retired.aborted_misc1event=0xc9,period=2000003,umask=0x8Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details)rtm_retired.aborted_misc2event=0xc9,period=2000003,umask=0x10Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts)Number of times the TSX watchdog signaled an RTM abortrtm_retired.aborted_misc3event=0xc9,period=2000003,umask=0x20Number of times an RTM execution aborted due to HLE-unfriendly instructionsNumber of times a disallowed operation caused an RTM abortrtm_retired.aborted_misc4event=0xc9,period=2000003,umask=0x40Number of times an RTM execution aborted due to incompatible memory typeNumber of times a RTM caused a faultrtm_retired.aborted_misc5event=0xc9,period=2000003,umask=0x80Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)Number of times RTM aborted and was not due to the abort conditions in subevents 3-6rtm_retired.commitevent=0xc9,period=2000003,umask=0x2Number of times RTM commit succeededrtm_retired.startevent=0xc9,period=2000003,umask=0x1Number of times we entered an RTM region; does not count nested transactionsNumber of times we entered an RTM region
 does not count nested transactionstx_exec.misc1event=0x5d,period=2000003,umask=0x1Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional aborttx_exec.misc2event=0x5d,period=2000003,umask=0x2Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional regionUnfriendly TSX abort triggered by  a vzeroupper instructiontx_exec.misc3event=0x5d,period=2000003,umask=0x4Counts the number of times an instruction execution caused the transactional nest count supported to be exceededUnfriendly TSX abort triggered by a nest count that is too deeptx_exec.misc4event=0x5d,period=2000003,umask=0x8Counts the number of times a XBEGIN instruction was executed inside an HLE transactional regionRTM region detected inside HLEtx_exec.misc5event=0x5d,period=2000003,umask=0x10Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional regiontx_mem.abort_capacity_writeevent=0x54,period=2000003,umask=0x2Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflowtx_mem.abort_conflictevent=0x54,period=2000003,umask=0x1Number of times a TSX line had a cache conflicttx_mem.abort_hle_elision_buffer_mismatchevent=0x54,period=2000003,umask=0x10Number of times a TSX Abort was triggered due to release/commit but data and address mismatchtx_mem.abort_hle_elision_buffer_not_emptyevent=0x54,period=2000003,umask=0x8Number of times a TSX Abort was triggered due to commit but Lock Buffer not emptytx_mem.abort_hle_elision_buffer_unsupported_alignmentevent=0x54,period=2000003,umask=0x20Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffertx_mem.abort_hle_store_to_elided_lockevent=0x54,period=2000003,umask=0x4Number of times a TSX Abort was triggered due to a non-release/commit store to locktx_mem.hle_elision_buffer_fullevent=0x54,period=2000003,umask=0x40Number of times we could not allocate Lock Buffercpl_cycles.ring0event=0x5c,period=2000003,umask=0x1Unhalted core cycles when the thread is in ring 0otherThis event counts the unhalted core cycles during which the thread is in the ring 0 privileged modecpl_cycles.ring0_transevent=0x5c,cmask=1,edge=1,period=100007,umask=0x1Number of intervals between processor halts while thread is in ring 0This event counts when there is a transition from ring 1,2 or 3 to ring0cpl_cycles.ring123event=0x5c,period=2000003,umask=0x2Unhalted core cycles when thread is in rings 1, 2, or 3This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3lock_cycles.split_lock_uc_lock_durationevent=0x63,period=2000003,umask=0x1Cycles when L1 and L2 are locked due to UC or split lockThis event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such accessarith.fpu_div_activeevent=0x14,period=2000003,umask=0x1Cycles when divider is busy executing divide operationspipelineThis event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executedbr_inst_exec.all_branchesevent=0x88,period=200003,umask=0xffSpeculative and retired  branchesThis event counts both taken and not taken speculative and retired branch instructionsbr_inst_exec.all_conditionalevent=0x88,period=200003,umask=0xc1Speculative and retired macro-conditional branchesThis event counts both taken and not taken speculative and retired macro-conditional branch instructionsbr_inst_exec.all_direct_jmpevent=0x88,period=200003,umask=0xc2Speculative and retired macro-unconditional branches excluding calls and indirectsThis event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirectsbr_inst_exec.all_direct_near_callevent=0x88,period=200003,umask=0xd0Speculative and retired direct near callsThis event counts both taken and not taken speculative and retired direct near callsbr_inst_exec.all_indirect_jump_non_call_retevent=0x88,period=200003,umask=0xc4Speculative and retired indirect branches excluding calls and returnsThis event counts both taken and not taken speculative and retired indirect branches excluding calls and return branchesbr_inst_exec.all_indirect_near_returnevent=0x88,period=200003,umask=0xc8Speculative and retired indirect return branchesThis event counts both taken and not taken speculative and retired indirect branches that have a return mnemonicbr_inst_exec.nontaken_conditionalevent=0x88,period=200003,umask=0x41Not taken macro-conditional branchesThis event counts not taken macro-conditional branch instructionsbr_inst_exec.taken_conditionalevent=0x88,period=200003,umask=0x81Taken speculative and retired macro-conditional branchesThis event counts taken speculative and retired macro-conditional branch instructionsbr_inst_exec.taken_direct_jumpevent=0x88,period=200003,umask=0x82Taken speculative and retired macro-conditional branch instructions excluding calls and indirectsThis event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branchesbr_inst_exec.taken_direct_near_callevent=0x88,period=200003,umask=0x90Taken speculative and retired direct near callsThis event counts taken speculative and retired direct near callsbr_inst_exec.taken_indirect_jump_non_call_retevent=0x88,period=200003,umask=0x84Taken speculative and retired indirect branches excluding calls and returnsThis event counts taken speculative and retired indirect branches excluding calls and return branchesbr_inst_exec.taken_indirect_near_callevent=0x88,period=200003,umask=0xa0Taken speculative and retired indirect callsThis event counts taken speculative and retired indirect calls including both register and memory indirectbr_inst_exec.taken_indirect_near_returnevent=0x88,period=200003,umask=0x88Taken speculative and retired indirect branches with return mnemonicThis event counts taken speculative and retired indirect branches that have a return mnemonicbr_inst_retired.all_branchesevent=0xc4,period=400009All (macro) branch instructions retiredThis event counts all (macro) branch instructions retiredbr_inst_retired.all_branches_pebsevent=0xc4,period=400009,umask=0x4All (macro) branch instructions retired. (Precise Event - PEBS)  Spec update: BDW98 (Must be precise)This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired  Spec update: BDW98 (Must be precise)br_inst_retired.conditionalevent=0xc4,period=400009,umask=0x1Conditional branch instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired (Precise event)br_inst_retired.far_branchevent=0xc4,period=100007,umask=0x40Far branch instructions retired  Spec update: BDW98This event counts far branch instructions retired  Spec update: BDW98br_inst_retired.near_callevent=0xc4,period=100007,umask=0x2Direct and indirect near call instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired (Precise event)br_inst_retired.near_call_r3Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event)br_inst_retired.near_returnevent=0xc4,period=100007,umask=0x8Return instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts return instructions retired (Precise event)br_inst_retired.near_takenevent=0xc4,period=400009,umask=0x20Taken branch instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired (Precise event)br_inst_retired.not_takenevent=0xc4,period=400009,umask=0x10Not taken branch instructions retiredThis event counts not taken branch instructions retiredbr_misp_exec.all_branchesevent=0x89,period=200003,umask=0xffSpeculative and retired mispredicted macro conditional branchesThis event counts both taken and not taken speculative and retired mispredicted branch instructionsbr_misp_exec.all_conditionalevent=0x89,period=200003,umask=0xc1This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructionsbr_misp_exec.all_indirect_jump_non_call_retevent=0x89,period=200003,umask=0xc4Mispredicted indirect branches excluding calls and returnsThis event counts both taken and not taken mispredicted indirect branches excluding calls and returnsbr_misp_exec.nontaken_conditionalevent=0x89,period=200003,umask=0x41Not taken speculative and retired mispredicted macro conditional branchesThis event counts not taken speculative and retired mispredicted macro conditional branch instructionsbr_misp_exec.taken_conditionalevent=0x89,period=200003,umask=0x81Taken speculative and retired mispredicted macro conditional branchesThis event counts taken speculative and retired mispredicted macro conditional branch instructionsbr_misp_exec.taken_indirect_jump_non_call_retevent=0x89,period=200003,umask=0x84Taken speculative and retired mispredicted indirect branches excluding calls and returnsThis event counts taken speculative and retired mispredicted indirect branches excluding calls and returnsbr_misp_exec.taken_indirect_near_callevent=0x89,period=200003,umask=0xa0Taken speculative and retired mispredicted indirect callsbr_misp_exec.taken_return_nearevent=0x89,period=200003,umask=0x88Taken speculative and retired mispredicted indirect branches with return mnemonicThis event counts taken speculative and retired mispredicted indirect branches that have a return mnemonicbr_misp_retired.all_branchesevent=0xc5,period=400009All mispredicted macro branch instructions retiredThis event counts all mispredicted macro branch instructions retiredbr_misp_retired.all_branches_pebsevent=0xc5,period=400009,umask=0x4Mispredicted macro branch instructions retired. (Precise Event - PEBS) (Must be precise)This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired (Must be precise)br_misp_retired.conditionalevent=0xc5,period=400009,umask=0x1Mispredicted conditional branch instructions retired. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired (Precise event)br_misp_retired.near_takenevent=0xc5,period=400009,umask=0x20number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event)Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS) (Precise event)br_misp_retired.retevent=0xc5,period=100007,umask=0x8This event counts the number of mispredicted ret instructions retired.(Precise Event)This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retiredcpu_clk_thread_unhalted.one_thread_activeevent=0x3c,period=2000003,umask=0x2Count XClk pulses when this thread is unhalted and the other thread is haltedcpu_clk_thread_unhalted.ref_xclkevent=0x3c,period=2000003,umask=0x1Reference cycles when the thread is unhalted (counts at 100 MHz rate)This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhzcpu_clk_thread_unhalted.ref_xclk_anyevent=0x3c,any=1,period=2000003,umask=0x1Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)cpu_clk_unhalted.one_thread_activecpu_clk_unhalted.ref_tscevent=0,period=2000003,umask=0x3Reference cycles when the core is not in halt stateThis event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. 
Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this casecpu_clk_unhalted.ref_xclkcpu_clk_unhalted.ref_xclk_anycpu_clk_unhalted.threadevent=0,period=2000003,umask=0x2Core cycles when the thread is not in halt stateThis event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other eventscpu_clk_unhalted.thread_anyevent=0,any=1,period=2000003,umask=0x2Core cycles when at least one thread on the physical core is not in halt statecpu_clk_unhalted.thread_pevent=0x3c,period=2000003Thread cycles when thread is not in halt stateThis is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock timecpu_clk_unhalted.thread_p_anyevent=0x3c,any=1,period=2000003cycle_activity.cycles_l1d_missevent=0xa3,cmask=8,period=2000003,umask=0x8Cycles while L1 cache miss demand load is outstandingcycle_activity.cycles_l1d_pendingCounts number of cycles the CPU has at least one pending  demand load request missing the L1 data cachecycle_activity.cycles_l2_missevent=0xa3,cmask=1,period=2000003,umask=0x1Cycles while L2 cache miss demand load is outstandingcycle_activity.cycles_l2_pendingCounts number of cycles the CPU has at least one pending  demand* load request missing the L2 cachecycle_activity.cycles_ldm_pendingevent=0xa3,cmask=2,period=2000003,umask=0x2Cycles while memory subsystem has an outstanding loadCounts number of cycles the CPU has at least one pending  demand load request (that is cycles with non-completed load waiting for its data from memory subsystem)cycle_activity.cycles_mem_anycycle_activity.cycles_no_executeevent=0xa3,cmask=4,period=2000003,umask=0x4This event increments by 1 for every cycle where there was no execute for this threadCounts number of cycles nothing is executed on any execution portcycle_activity.stalls_l1d_missevent=0xa3,cmask=12,period=2000003,umask=0xcExecution stalls while L1 cache miss demand load is outstandingcycle_activity.stalls_l1d_pendingCounts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cachecycle_activity.stalls_l2_missevent=0xa3,cmask=5,period=2000003,umask=0x5Execution stalls while L2 cache miss demand load is outstandingcycle_activity.stalls_l2_pendingCounts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demandscycle_activity.stalls_ldm_pendingevent=0xa3,cmask=6,period=2000003,umask=0x6Execution stalls while memory subsystem has an outstanding loadCounts number of cycles nothing is executed on any execution port, while there was at least one pending demand load requestcycle_activity.stalls_mem_anycycle_activity.stalls_totalTotal execution stallsild_stall.lcpevent=0x87,period=2000003,umask=0x1Stalls caused by changing prefix length of the instructionThis event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunkinst_retired.anyevent=0,period=2000003,umask=0x1Instructions retired from executionThis event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. 
Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. 
Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructionsinst_retired.any_pevent=0xc0,period=2000003Number of instructions retired. General Counter   - architectural event  Spec update: BDM61This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two)  Spec update: BDM61inst_retired.prec_distevent=0xc0,period=2000003,umask=0x1Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: BDM11, BDM55 (Must be precise)This is a precise version (that is, uses PEBS) of the event that counts instructions retired  Spec update: BDM11, BDM55 (Must be precise)inst_retired.x87event=0xc0,period=2000003,umask=0x2FP operations  retired. X87 FP operations that have no exceptions:This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handlingint_misc.rat_stall_cyclesevent=0xd,period=2000003,umask=0x8Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the threadThis event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another threadint_misc.recovery_cyclesevent=0xd,cmask=1,period=2000003,umask=0x3Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clearint_misc.recovery_cycles_anyevent=0xd,any=1,cmask=1,period=2000003,umask=0x3Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)ld_blocks.no_srevent=0x3,period=100003,umask=0x8This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useld_blocks.store_forwardevent=0x3,period=100003,umask=0x2Cases when loads get true Block-on-Store blocking code preventing store forwardingThis event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:
 - preceding store conflicts with the load (incomplete overlap);
 - store forwarding is impossible due to u-arch limitations;
 - preceding lock RMW operations are not forwarded;
 - store has the no-forward bit set (uncacheable/page-split/masked stores);
 - all-blocking stores are used (mostly, fences and port I/O);
and others.
The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.
See the table of not supported store forwards in the Optimization Guideld_blocks_partial.address_aliasevent=0x7,period=100003,umask=0x1False dependencies in MOB due to partial compareThis event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliasedload_hit_pre.hw_pfevent=0x4c,period=100003,umask=0x2Not software-prefetch load dispatches that hit FB allocated for hardware prefetchThis event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetchload_hit_pre.sw_pfevent=0x4c,period=100003,umask=0x1Not software-prefetch load dispatches that hit FB allocated for software prefetchThis event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructionslsd.cycles_4_uopsevent=0xa8,cmask=4,period=2000003,umask=0x1Cycles 4 Uops delivered by the LSD, but didn't come from the decoderlsd.cycles_activeevent=0xa8,cmask=1,period=2000003,umask=0x1Cycles Uops delivered by the LSD, but didn't come from the decoderlsd.uopsevent=0xa8,period=2000003,umask=0x1Number of Uops delivered by the LSDmachine_clears.countevent=0xc3,cmask=1,edge=1,period=100003,umask=0x1Number of machine clears (nukes) of any typemachine_clears.cyclesevent=0xc3,period=2000003,umask=0x1Cycles there was a Nuke. Account for both thread-specific and All Thread NukesThis event counts both thread-specific (TS) and all-thread (AT) nukesmachine_clears.maskmovevent=0xc3,period=100003,umask=0x20This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a faultmachine_clears.smcevent=0xc3,period=100003,umask=0x4Self-modifying code (SMC) detectedThis event counts self-modifying code (SMC) detected, which causes a machine clearmove_elimination.int_eliminatedevent=0x58,period=1000003,umask=0x1Number of integer Move Elimination candidate uops that were eliminatedmove_elimination.int_not_eliminatedevent=0x58,period=1000003,umask=0x4Number of integer Move Elimination candidate uops that were not eliminatedother_assists.any_wb_assistevent=0xc1,period=100003,umask=0x40Number of times any microcode assist is invoked by HW upon uop writebackresource_stalls.anyevent=0xa2,period=2000003,umask=0x1Resource-related stall cyclesThis event counts resource-related stall cycles. Reasons for stalls can be as follows:
 - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)
 - *any* u-arch structure got empty (like INT/SIMD FreeLists)
 - FPU control word (FPCW), MXCSR
and others. This counts cycles that the pipeline backend blocked uop delivery from the front endresource_stalls.robevent=0xa2,period=2000003,umask=0x10Cycles stalled due to re-order buffer fullThis event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front endresource_stalls.rsevent=0xa2,period=2000003,umask=0x4Cycles stalled due to no eligible RS entry availableThis event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front endresource_stalls.sbevent=0xa2,period=2000003,umask=0x8Cycles stalled due to no store buffers available. (not including draining form sync)This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front endrob_misc_events.lbr_insertsevent=0xcc,period=2000003,umask=0x20Count cases of saving new LBRThis event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT registerrs_events.empty_cyclesevent=0x5e,period=2000003,umask=0x1Cycles when Reservation Station (RS) is empty for the threadThis event counts cycles during which the reservation station (RS) is empty for the thread.
Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issuesrs_events.empty_endevent=0x5e,cmask=1,edge=1,inv=1,period=200003,umask=0x1Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issuesuops_dispatched_port.port_0event=0xa1,period=2000003,umask=0x1Cycles per thread when uops are executed in port 0This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0uops_dispatched_port.port_1event=0xa1,period=2000003,umask=0x2Cycles per thread when uops are executed in port 1This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1uops_dispatched_port.port_2event=0xa1,period=2000003,umask=0x4Cycles per thread when uops are executed in port 2This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2uops_dispatched_port.port_3event=0xa1,period=2000003,umask=0x8Cycles per thread when uops are executed in port 3This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3uops_dispatched_port.port_4event=0xa1,period=2000003,umask=0x10Cycles per thread when uops are executed in port 4This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4uops_dispatched_port.port_5event=0xa1,period=2000003,umask=0x20Cycles per thread when uops are executed in port 5This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5uops_dispatched_port.port_6event=0xa1,period=2000003,umask=0x40Cycles per thread when uops are executed in port 6This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6uops_dispatched_port.port_7event=0xa1,period=2000003,umask=0x80Cycles per thread when uops are executed in port 7This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7uops_executed.coreevent=0xb1,period=2000003,umask=0x2Number of uops executed on the coreNumber of uops executed from any threaduops_executed.core_cycles_ge_1event=0xb1,cmask=1,period=2000003,umask=0x2Cycles at least 1 micro-op is executed from any thread on physical coreuops_executed.core_cycles_ge_2event=0xb1,cmask=2,period=2000003,umask=0x2Cycles at least 2 micro-op is executed from any thread on physical coreuops_executed.core_cycles_ge_3event=0xb1,cmask=3,period=2000003,umask=0x2Cycles at least 3 micro-op is executed from any thread on physical coreuops_executed.core_cycles_ge_4event=0xb1,cmask=4,period=2000003,umask=0x2Cycles at least 4 micro-op is executed from any thread on physical coreuops_executed.core_cycles_noneevent=0xb1,inv=1,period=2000003,umask=0x2Cycles with no micro-ops executed from any thread on physical coreuops_executed.cycles_ge_1_uop_execevent=0xb1,cmask=1,period=2000003,umask=0x1Cycles where at least 1 uop was executed per-threaduops_executed.cycles_ge_2_uops_execevent=0xb1,cmask=2,period=2000003,umask=0x1Cycles where at least 2 uops were executed per-threaduops_executed.cycles_ge_3_uops_execevent=0xb1,cmask=3,period=2000003,umask=0x1Cycles where at least 3 uops were executed per-threaduops_executed.cycles_ge_4_uops_execevent=0xb1,cmask=4,period=2000003,umask=0x1Cycles where at least 4 uops were executed per-threaduops_executed.stall_cyclesevent=0xb1,cmask=1,inv=1,period=2000003,umask=0x1Counts number of cycles no uops were dispatched to be executed on this threadThis event counts cycles during which no uops were dispatched from the Reservation Station (RS) per threaduops_executed.threadevent=0xb1,period=2000003,umask=0x1Counts the number of uops to be executed per-thread each cycleNumber of uops to be executed per-thread each cycleuops_executed_port.port_0uops_executed_port.port_0_coreevent=0xa1,any=1,period=2000003,umask=0x1Cycles per core when uops are exectuted in port 0uops_executed_port.port_1uops_executed_port.port_1_coreevent=0xa1,any=1,period=2000003,umask=0x2Cycles per core when uops are exectuted in port 1uops_executed_port.port_2uops_executed_port.port_2_coreevent=0xa1,any=1,period=2000003,umask=0x4Cycles per core when uops are dispatched to port 2uops_executed_port.port_3uops_executed_port.port_3_coreevent=0xa1,any=1,period=2000003,umask=0x8Cycles per core when uops are dispatched to port 3uops_executed_port.port_4uops_executed_port.port_4_coreevent=0xa1,any=1,period=2000003,umask=0x10Cycles per core when uops are exectuted in port 4uops_executed_port.port_5uops_executed_port.port_5_coreevent=0xa1,any=1,period=2000003,umask=0x20Cycles per core when uops are exectuted in port 5uops_executed_port.port_6uops_executed_port.port_6_coreevent=0xa1,any=1,period=2000003,umask=0x40Cycles per core when uops are exectuted in port 6uops_executed_port.port_7uops_executed_port.port_7_coreevent=0xa1,any=1,period=2000003,umask=0x80Cycles per core when uops are dispatched to port 7uops_issued.anyevent=0xe,period=2000003,umask=0x1Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS)uops_issued.flags_mergeevent=0xe,period=2000003,umask=0x10Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-archNumber of flags-merge uops being allocated. Such uops considered perf sensitive
 added by GSR u-archuops_issued.single_mulevent=0xe,period=2000003,umask=0x40Number of Multiply packed/scalar single precision uops allocateduops_issued.slow_leaevent=0xe,period=2000003,umask=0x20Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or notuops_issued.stall_cyclesevent=0xe,cmask=1,inv=1,period=2000003,umask=0x1Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the threadThis event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current threaduops_retired.allevent=0xc2,period=2000003,umask=0x1Actually retired uops. (Precise Event - PEBS)  Supports address when precise (Precise event)This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight  Supports address when precise (Precise event)uops_retired.retire_slotsevent=0xc2,period=2000003,umask=0x2Retirement slots used. (Precise Event - PEBS) (Precise event)This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used (Precise event)uops_retired.stall_cyclesevent=0xc2,cmask=1,inv=1,period=2000003,umask=0x1Cycles without actually retired uopsThis event counts cycles without actually retired uopsuops_retired.total_cyclesevent=0xc2,cmask=10,inv=1,period=2000003,umask=0x1Cycles with less than 10 actually retired uopsNumber of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired eventunc_c_clockticksevent=0Uncore cache clock ticks. Unit: uncore_cbox uncore cacheuncore_cbox1unc_c_llc_lookup.anyevent=0x34,umask=0x11,filter_state=0x1All LLC Misses (code+ data rd + data wr - including demand and prefetch). Unit: uncore_cbox 64Bytesunc_c_llc_victims.m_stateevent=0x37,umask=0x1M line evictions from LLC (writebacks to memory). Unit: uncore_cbox llc_misses.data_readevent=0x35,umask=0x3,filter_opc=0x182LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.uncacheableevent=0x35,umask=0x3,filter_opc=0x187LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.mmio_readevent=0x35,umask=0x3,filter_opc=0x187,filter_nc=1MMIO reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.mmio_writeevent=0x35,umask=0x3,filter_opc=0x18f,filter_nc=1MMIO writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.rfo_llc_prefetchevent=0x35,umask=0x3,filter_opc=0x190LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.code_llc_prefetchevent=0x35,umask=0x3,filter_opc=0x191LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.data_llc_prefetchevent=0x35,umask=0x3,filter_opc=0x192LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.pcie_readevent=0x35,umask=0x3,filter_opc=0x19eLLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.pcie_writeevent=0x35,umask=0x3,filter_opc=0x1c8ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_misses.pcie_non_snoop_writeevent=0x35,umask=0x3,filter_opc=0x1c8,filter_tid=0x3ePCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox llc_references.pcie_ns_partial_writeevent=0x35,umask=0x1,filter_opc=0x180,filter_tid=0x3ePCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.code_llc_prefetchevent=0x35,umask=0x1,filter_opc=0x181L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.streaming_fullevent=0x35,umask=0x1,filter_opc=0x18cStreaming stores (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.streaming_partialevent=0x35,umask=0x1,filter_opc=0x18dStreaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.pcie_readevent=0x35,umask=0x1,filter_opc=0x19ePCIe read current. Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox llc_references.pcie_writeevent=0x35,umask=0x1,filter_opc=0x1c8,filter_tid=0x3ePCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode. Unit: uncore_cbox unc_c_tor_occupancy.llc_data_readevent=0x36,umask=0x3,filter_opc=0x182Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode. Unit: uncore_cbox unc_h_requests.readsevent=0x1,umask=0x3read requests to home agent. Unit: uncore_ha uncore_haunc_h_requests.reads_localevent=0x1,umask=0x1read requests to local home agent. Unit: uncore_ha unc_h_requests.reads_remoteevent=0x1,umask=0x2read requests to remote home agent. Unit: uncore_ha unc_h_requests.writesevent=0x1,umask=0xCwrite requests to home agent. Unit: uncore_ha unc_h_requests.writes_localevent=0x1,umask=0x4write requests to local home agent. Unit: uncore_ha unc_h_requests.writes_remoteevent=0x1,umask=0x8write requests to remote home agent. Unit: uncore_ha unc_h_snoop_resp.rspcnflctevent=0x21,umask=0x40Conflict requests (requests for same address from multiple agents simultaneously). Unit: uncore_ha unc_h_snoop_resp.rsp_fwd_wbevent=0x21,umask=0x20M line forwarded from remote cache along with writeback to memory. Unit: uncore_ha unc_h_snoop_resp.rspifwdevent=0x21,umask=0x4M line forwarded from remote cache with no writeback to memory. Unit: uncore_ha unc_h_snoop_resp.rspsevent=0x21,umask=0x2Shared line response from remote cache. Unit: uncore_ha unc_h_snoop_resp.rspsfwdevent=0x21,umask=0x8Shared line forwarded from remote cache. Unit: uncore_ha llc_misses.mem_readevent=0x4,umask=0x3read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc uncore memoryuncore_imcllc_misses.mem_writeevent=0x4,umask=0xCwrite requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc unc_m_dclockticksMemory controller clock ticks. Unit: uncore_imc unc_m_power_channel_ppdevent=0x85Cycles where DRAM ranks are in power down (CKE) mode. Unit: uncore_imc (UNC_M_POWER_CHANNEL_PPD / UNC_M_DCLOCKTICKS) * 100.power_channel_ppd %unc_m_power_critical_throttle_cyclesevent=0x86Cycles all ranks are in critical thermal throttle. Unit: uncore_imc (UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_DCLOCKTICKS) * 100.power_critical_throttle_cycles %unc_m_power_self_refreshevent=0x43Cycles Memory is in self refresh power mode. Unit: uncore_imc (UNC_M_POWER_SELF_REFRESH / UNC_M_DCLOCKTICKS) * 100.power_self_refresh %unc_m_pre_count.page_missevent=0x2,umask=0x1Pre-charges due to page misses. Unit: uncore_imc unc_m_pre_count.rdevent=0x2,umask=0x4Pre-charge for reads. Unit: uncore_imc unc_m_pre_count.wrevent=0x2,umask=0x8Pre-charge for writes. Unit: uncore_imc unc_p_clockticksPCU clock ticks. Use to get percentages of PCU cycles events. Unit: uncore_pcu uncore poweruncore_pcuunc_p_power_state_occupancy.cores_c0event=0x80,occ_sel=1This is an occupancy event that tracks the number of cores that are in C0.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu (UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCKTICKS) * 100.power_state_occupancy.cores_c0 %unc_p_power_state_occupancy.cores_c3event=0x80,occ_sel=2This is an occupancy event that tracks the number of cores that are in C3.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. Unit: uncore_pcu (UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCKTICKS) * 100.power_state_occupancy.cores_c3 %unc_p_power_state_occupancy.cores_c6event=0x80,occ_sel=3This is an occupancy event that tracks the number of cores that are in C6.  It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events . Unit: uncore_pcu (UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCKTICKS) * 100.power_state_occupancy.cores_c6 %unc_p_prochot_external_cyclesevent=0xaCounts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip. Unit: uncore_pcu (UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) * 100.prochot_external_cycles %unc_p_freq_max_limit_thermal_cyclesevent=0x4Counts the number of cycles when temperature is the upper limit on frequency. Unit: uncore_pcu (UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_max_limit_thermal_cycles %unc_p_freq_max_os_cyclesevent=0x6Counts the number of cycles when the OS is the upper limit on frequency. Unit: uncore_pcu (UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_max_os_cycles %unc_p_freq_max_power_cyclesevent=0x5Counts the number of cycles when power is the upper limit on frequency. Unit: uncore_pcu (UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_max_power_cycles %unc_p_freq_trans_cyclesevent=0x74Counts the number of cycles when current is the upper limit on frequency. Unit: uncore_pcu (UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_trans_cycles %dtlb_load_misses.miss_causes_a_walkevent=0x8,period=100003,umask=0x1Load misses in all DTLB levels that cause page walks  Spec update: BDM69virtual memoryThis event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G)  Spec update: BDM69dtlb_load_misses.stlb_hitevent=0x8,period=2000003,umask=0x60Load operations that miss the first DTLB level but hit the second and do not cause page walksdtlb_load_misses.stlb_hit_2mevent=0x8,period=2000003,umask=0x40Load misses that miss the  DTLB and hit the STLB (2M)dtlb_load_misses.stlb_hit_4kevent=0x8,period=2000003,umask=0x20Load misses that miss the  DTLB and hit the STLB (4K)dtlb_load_misses.walk_completedevent=0x8,period=100003,umask=0xeDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size  Spec update: BDM69dtlb_load_misses.walk_completed_1gevent=0x8,period=2000003,umask=0x8Load miss in all TLB levels causes a page walk that completes. (1G)  Spec update: BDM69This event counts load misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault  Spec update: BDM69dtlb_load_misses.walk_completed_2m_4mevent=0x8,period=2000003,umask=0x4Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M)  Spec update: BDM69This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault  Spec update: BDM69dtlb_load_misses.walk_completed_4kevent=0x8,period=2000003,umask=0x2Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K)  Spec update: BDM69This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault  Spec update: BDM69dtlb_load_misses.walk_durationevent=0x8,period=2000003,umask=0x10Cycles when PMH is busy with page walks  Spec update: BDM69This event counts the number of cycles while PMH is busy with the page walk  Spec update: BDM69dtlb_store_misses.miss_causes_a_walkevent=0x49,period=100003,umask=0x1Store misses in all DTLB levels that cause page walks  Spec update: BDM69This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G)  Spec update: BDM69dtlb_store_misses.stlb_hitevent=0x49,period=100003,umask=0x60Store operations that miss the first TLB level but hit the second and do not cause page walksdtlb_store_misses.stlb_hit_2mevent=0x49,period=100003,umask=0x40Store misses that miss the  DTLB and hit the STLB (2M)dtlb_store_misses.stlb_hit_4kevent=0x49,period=100003,umask=0x20Store misses that miss the  DTLB and hit the STLB (4K)dtlb_store_misses.walk_completedevent=0x49,period=100003,umask=0xeStore misses in all DTLB levels that cause completed page walks  Spec update: BDM69dtlb_store_misses.walk_completed_1gevent=0x49,period=100003,umask=0x8Store misses in all DTLB levels that cause completed page walks (1G)  Spec update: BDM69This event counts store misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault  Spec update: BDM69dtlb_store_misses.walk_completed_2m_4mevent=0x49,period=100003,umask=0x4Store misses in all DTLB levels that cause completed page walks (2M/4M)  Spec update: BDM69This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault  Spec update: BDM69dtlb_store_misses.walk_completed_4kevent=0x49,period=100003,umask=0x2Store miss in all TLB levels causes a page walk that completes. (4K)  Spec update: BDM69This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault  Spec update: BDM69dtlb_store_misses.walk_durationevent=0x49,period=100003,umask=0x10ept.walk_cyclesevent=0x4f,period=2000003,umask=0x10Cycle count for an Extended Page table walkThis event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB cachesitlb.itlb_flushevent=0xae,period=100007,umask=0x1Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pagesThis event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific)itlb_misses.miss_causes_a_walkevent=0x85,period=100003,umask=0x1Misses at all ITLB levels that cause page walks  Spec update: BDM69itlb_misses.stlb_hitevent=0x85,period=100003,umask=0x60Operations that miss the first ITLB level but hit the second and do not cause any page walksitlb_misses.stlb_hit_2mevent=0x85,period=100003,umask=0x40Code misses that miss the  DTLB and hit the STLB (2M)itlb_misses.stlb_hit_4kevent=0x85,period=100003,umask=0x20Core misses that miss the  DTLB and hit the STLB (4K)itlb_misses.walk_completedevent=0x85,period=100003,umask=0xeMisses in all ITLB levels that cause completed page walks  Spec update: BDM69itlb_misses.walk_completed_1gevent=0x85,period=100003,umask=0x8Store miss in all TLB levels causes a page walk that completes. (1G)  Spec update: BDM69itlb_misses.walk_completed_2m_4mevent=0x85,period=100003,umask=0x4Code miss in all TLB levels causes a page walk that completes. (2M/4M)  Spec update: BDM69itlb_misses.walk_completed_4kevent=0x85,period=100003,umask=0x2Code miss in all TLB levels causes a page walk that completes. (4K)  Spec update: BDM69itlb_misses.walk_durationevent=0x85,period=100003,umask=0x10page_walker_loads.dtlb_l1event=0xbc,period=2000003,umask=0x11Number of DTLB page walker hits in the L1+FB  Spec update: BDM69, BDM98page_walker_loads.dtlb_l2event=0xbc,period=2000003,umask=0x12Number of DTLB page walker hits in the L2  Spec update: BDM69, BDM98page_walker_loads.dtlb_l3event=0xbc,period=2000003,umask=0x14Number of DTLB page walker hits in the L3 + XSNP  Spec update: BDM69, BDM98page_walker_loads.dtlb_memoryevent=0xbc,period=2000003,umask=0x18Number of DTLB page walker hits in Memory  Spec update: BDM69, BDM98page_walker_loads.itlb_l1event=0xbc,period=2000003,umask=0x21Number of ITLB page walker hits in the L1+FB  Spec update: BDM69, BDM98page_walker_loads.itlb_l2event=0xbc,period=2000003,umask=0x22Number of ITLB page walker hits in the L2  Spec update: BDM69, BDM98page_walker_loads.itlb_l3event=0xbc,period=2000003,umask=0x24Number of ITLB page walker hits in the L3 + XSNP  Spec update: BDM69, BDM98tlb_flush.dtlb_threadevent=0xbd,period=100007,umask=0x1DTLB flush attempts of the thread-specific entriesThis event counts the number of DTLB flush attempts of the thread-specific entriestlb_flush.stlb_anyevent=0xbd,period=100007,umask=0x20STLB flush attemptsThis event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on)bdw metrics ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHESIDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )64 * ( arb@event\=0x81\,umask\=0x1@ + arb@event\=0x84\,umask\=0x1@ ) / 1000000 / duration_time / 1000Average latency of all requests to external memory (in Uncore cycles)UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\=0x81\,umask\=0x1@MEM_Request_LatencyMem;SoCAverage number of parallel requests to external memory. Accounts for all requestsMEM_Parallel_Requestsevent=0x24,period=200003,umask=0xc4event=0x24,period=200003,umask=0xc1Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cacheevent=0x24,period=200003,umask=0xd0event=0x24,period=200003,umask=0xc2Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)Retired load uops which data sources were HitM responses from shared L3  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3)  Supports address when precise.  Spec update: BDM100 (Precise event)Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache  Supports address when precise.  Spec update: BDM100 (Precise event)Retired load uops which data sources were hits in L3 without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)Data from local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70, BDM100 (Precise event)Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70, BDM100 (Precise event)Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event)This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load  Supports address when precise (Precise event)Retired load uops with L1 cache hits as data sources  Supports address when precise (Precise event)This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.
Note: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source  Supports address when precise (Precise event)Retired load uops misses in L1 cache as data sources  Supports address when precise (Precise event)This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)Retired load uops with L2 cache hits as data sources  Supports address when precise.  Spec update: BDM35 (Precise event)This event counts retired load uops which data sources were hits in the mid-level (L2) cache  Supports address when precise.  Spec update: BDM35 (Precise event)Miss in mid-level (L2) cache. Excludes Unknown data-source  Supports address when precise (Precise event)This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source  Supports address when precise (Precise event)Retired load uops which data sources were data hits in L3 without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required  Supports address when precise.  Spec update: BDM100 (Precise event)Miss in last-level (L3) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: BDM100, BDE70 (Precise event)All retired load uops  Supports address when precise (Precise event)This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches  Supports address when precise (Precise event)All retired store uops  Supports address when precise (Precise event)This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.
Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement  Supports address when precise (Precise event)Retired load uops with locked access  Supports address when precise.  Spec update: BDM35 (Precise event)This event counts load uops with locked access retired to the architected path  Supports address when precise.  Spec update: BDM35 (Precise event)Retired load uops that split across a cacheline boundary  Supports address when precise (Precise event)This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)Retired store uops that split across a cacheline boundary  Supports address when precise (Precise event)This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K)  Supports address when precise (Precise event)Retired load uops that miss the STLB  Supports address when precise (Precise event)This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)Retired store uops that miss the STLB  Supports address when precise (Precise event)This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault  Supports address when precise (Precise event)offcore_requests.all_requestsevent=0xb0,period=100003,umask=0x80Any memory transaction that reached the SQThis event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so onoffcore_response.all_data_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010091Counts all demand & prefetch data reads have any response typeoffcore_response.all_data_rd.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0091Counts all demand & prefetch data readsoffcore_response.all_data_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0091offcore_response.all_data_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0091offcore_response.all_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0091offcore_response.all_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0091offcore_response.all_data_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0091offcore_response.all_data_rd.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020091offcore_response.all_data_rd.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020091offcore_response.all_data_rd.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020091offcore_response.all_data_rd.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020091offcore_response.all_data_rd.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020091offcore_response.all_data_rd.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020091offcore_response.all_pf_code_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010240Counts all prefetch code reads have any response typeoffcore_response.all_pf_code_rd.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0240Counts all prefetch code readsoffcore_response.all_pf_code_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0240offcore_response.all_pf_code_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0240offcore_response.all_pf_code_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0240offcore_response.all_pf_code_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0240offcore_response.all_pf_code_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0240offcore_response.all_pf_code_rd.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020240offcore_response.all_pf_code_rd.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020240offcore_response.all_pf_code_rd.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020240offcore_response.all_pf_code_rd.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020240offcore_response.all_pf_code_rd.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020240offcore_response.all_pf_code_rd.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020240offcore_response.all_pf_data_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010090Counts all prefetch data reads have any response typeoffcore_response.all_pf_data_rd.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0090Counts all prefetch data readsoffcore_response.all_pf_data_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0090offcore_response.all_pf_data_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0090offcore_response.all_pf_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0090offcore_response.all_pf_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0090offcore_response.all_pf_data_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0090offcore_response.all_pf_data_rd.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020090offcore_response.all_pf_data_rd.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020090offcore_response.all_pf_data_rd.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020090offcore_response.all_pf_data_rd.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020090offcore_response.all_pf_data_rd.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020090offcore_response.all_pf_data_rd.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020090offcore_response.all_pf_rfo.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010120Counts prefetch RFOs have any response typeoffcore_response.all_pf_rfo.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0120Counts prefetch RFOsoffcore_response.all_pf_rfo.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0120offcore_response.all_pf_rfo.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0120offcore_response.all_pf_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0120offcore_response.all_pf_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0120offcore_response.all_pf_rfo.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0120offcore_response.all_pf_rfo.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020120offcore_response.all_pf_rfo.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020120offcore_response.all_pf_rfo.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020120offcore_response.all_pf_rfo.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020120offcore_response.all_pf_rfo.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020120offcore_response.all_pf_rfo.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020120offcore_response.all_rfo.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010122Counts all demand & prefetch RFOs have any response typeoffcore_response.all_rfo.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0122Counts all demand & prefetch RFOsoffcore_response.all_rfo.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0122offcore_response.all_rfo.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0122offcore_response.all_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0122offcore_response.all_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0122offcore_response.all_rfo.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0122offcore_response.all_rfo.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020122offcore_response.all_rfo.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020122offcore_response.all_rfo.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020122offcore_response.all_rfo.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020122offcore_response.all_rfo.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020122offcore_response.all_rfo.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020122offcore_response.corewb.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010008Counts writebacks (modified to exclusive) have any response typeoffcore_response.corewb.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0008Counts writebacks (modified to exclusive)offcore_response.corewb.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0008offcore_response.corewb.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0008offcore_response.corewb.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0008offcore_response.corewb.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0008offcore_response.corewb.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0008offcore_response.corewb.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020008offcore_response.corewb.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020008offcore_response.corewb.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020008offcore_response.corewb.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020008offcore_response.corewb.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020008offcore_response.corewb.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020008offcore_response.demand_code_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010004Counts all demand code reads have any response typeoffcore_response.demand_code_rd.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0004Counts all demand code readsoffcore_response.demand_code_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0004offcore_response.demand_code_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0004offcore_response.demand_code_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0004offcore_response.demand_code_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0004offcore_response.demand_code_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0004offcore_response.demand_code_rd.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020004offcore_response.demand_code_rd.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020004offcore_response.demand_code_rd.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020004offcore_response.demand_code_rd.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020004offcore_response.demand_code_rd.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020004offcore_response.demand_code_rd.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020004offcore_response.demand_data_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010001Counts demand data reads have any response typeoffcore_response.demand_data_rd.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0001Counts demand data readsoffcore_response.demand_data_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0001offcore_response.demand_data_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0001offcore_response.demand_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0001offcore_response.demand_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0001offcore_response.demand_data_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0001offcore_response.demand_data_rd.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020001offcore_response.demand_data_rd.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020001offcore_response.demand_data_rd.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020001offcore_response.demand_data_rd.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020001offcore_response.demand_data_rd.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020001offcore_response.demand_data_rd.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020001offcore_response.demand_rfo.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010002Counts all demand data writes (RFOs) have any response typeoffcore_response.demand_rfo.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0002Counts all demand data writes (RFOs)offcore_response.demand_rfo.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0002offcore_response.demand_rfo.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0002offcore_response.demand_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0002offcore_response.demand_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0002offcore_response.demand_rfo.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0002offcore_response.other.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000018000Counts any other requests have any response typeoffcore_response.other.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C8000Counts any other requestsoffcore_response.other.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C8000offcore_response.other.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C8000offcore_response.other.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C8000offcore_response.other.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C8000offcore_response.other.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C8000offcore_response.other.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80028000offcore_response.other.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000028000offcore_response.other.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400028000offcore_response.other.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200028000offcore_response.other.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080028000offcore_response.other.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100028000offcore_response.pf_l2_code_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010040Counts all prefetch (that bring data to LLC only) code reads have any response typeoffcore_response.pf_l2_code_rd.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0040Counts all prefetch (that bring data to LLC only) code readsoffcore_response.pf_l2_code_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0040offcore_response.pf_l2_code_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0040offcore_response.pf_l2_code_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0040offcore_response.pf_l2_code_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0040offcore_response.pf_l2_code_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0040offcore_response.pf_l2_code_rd.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020040offcore_response.pf_l2_code_rd.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020040offcore_response.pf_l2_code_rd.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020040offcore_response.pf_l2_code_rd.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020040offcore_response.pf_l2_code_rd.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020040offcore_response.pf_l2_code_rd.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020040offcore_response.pf_l2_data_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010010Counts prefetch (that bring data to L2) data reads have any response typeoffcore_response.pf_l2_data_rd.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0010Counts prefetch (that bring data to L2) data readsoffcore_response.pf_l2_data_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0010offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0010offcore_response.pf_l2_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0010offcore_response.pf_l2_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0010offcore_response.pf_l2_data_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0010offcore_response.pf_l2_data_rd.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020010offcore_response.pf_l2_data_rd.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020010offcore_response.pf_l2_data_rd.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020010offcore_response.pf_l2_data_rd.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020010offcore_response.pf_l2_data_rd.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020010offcore_response.pf_l2_data_rd.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020010offcore_response.pf_l2_rfo.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010020Counts all prefetch (that bring data to L2) RFOs have any response typeoffcore_response.pf_l2_rfo.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0020Counts all prefetch (that bring data to L2) RFOsoffcore_response.pf_l2_rfo.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0020offcore_response.pf_l2_rfo.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0020offcore_response.pf_l2_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0020offcore_response.pf_l2_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0020offcore_response.pf_l2_rfo.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0020offcore_response.pf_l2_rfo.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020020offcore_response.pf_l2_rfo.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020020offcore_response.pf_l2_rfo.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020020offcore_response.pf_l2_rfo.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020020offcore_response.pf_l2_rfo.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020020offcore_response.pf_l2_rfo.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020020offcore_response.pf_l3_code_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010200Counts prefetch (that bring data to LLC only) code reads have any response typeoffcore_response.pf_l3_code_rd.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0200Counts prefetch (that bring data to LLC only) code readsoffcore_response.pf_l3_code_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0200offcore_response.pf_l3_code_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0200offcore_response.pf_l3_code_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0200offcore_response.pf_l3_code_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0200offcore_response.pf_l3_code_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0200offcore_response.pf_l3_code_rd.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020200offcore_response.pf_l3_code_rd.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020200offcore_response.pf_l3_code_rd.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020200offcore_response.pf_l3_code_rd.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020200offcore_response.pf_l3_code_rd.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020200offcore_response.pf_l3_code_rd.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020200offcore_response.pf_l3_data_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010080Counts all prefetch (that bring data to LLC only) data reads have any response typeoffcore_response.pf_l3_data_rd.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0080Counts all prefetch (that bring data to LLC only) data readsoffcore_response.pf_l3_data_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0080offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0080offcore_response.pf_l3_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0080offcore_response.pf_l3_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0080offcore_response.pf_l3_data_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0080offcore_response.pf_l3_data_rd.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020080offcore_response.pf_l3_data_rd.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020080offcore_response.pf_l3_data_rd.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020080offcore_response.pf_l3_data_rd.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020080offcore_response.pf_l3_data_rd.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020080offcore_response.pf_l3_data_rd.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020080offcore_response.pf_l3_rfo.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0000010100Counts all prefetch (that bring data to LLC only) RFOs have any response typeoffcore_response.pf_l3_rfo.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0100Counts all prefetch (that bring data to LLC only) RFOsoffcore_response.pf_l3_rfo.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0100offcore_response.pf_l3_rfo.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0100offcore_response.pf_l3_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x02003C0100offcore_response.pf_l3_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00803C0100offcore_response.pf_l3_rfo.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01003C0100offcore_response.pf_l3_rfo.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020100offcore_response.pf_l3_rfo.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020100offcore_response.pf_l3_rfo.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0400020100offcore_response.pf_l3_rfo.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0200020100offcore_response.pf_l3_rfo.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0080020100offcore_response.pf_l3_rfo.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100020100Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per elementNumber of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 4 calculations per elementNumber of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per elementNumber of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation.   Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementNumber of times HLE abort was triggered (Precise event)Randomly selected loads with latency value being above 128  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 128  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 16  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 16  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 256  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 256  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 32  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 32  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 4  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above four  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 512  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 512  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 64  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above 64  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Randomly selected loads with latency value being above 8  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)Counts randomly selected loads with latency value being above eight  Supports address when precise.  Spec update: BDM100, BDM35 (Must be precise)offcore_response.all_data_rd.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0091offcore_response.all_data_rd.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000091offcore_response.all_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000091offcore_response.all_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000091offcore_response.all_data_rd.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000091offcore_response.all_data_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000091offcore_response.all_data_rd.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000091offcore_response.all_data_rd.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020091offcore_response.all_pf_code_rd.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0240offcore_response.all_pf_code_rd.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000240offcore_response.all_pf_code_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000240offcore_response.all_pf_code_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000240offcore_response.all_pf_code_rd.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000240offcore_response.all_pf_code_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000240offcore_response.all_pf_code_rd.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000240offcore_response.all_pf_code_rd.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020240offcore_response.all_pf_data_rd.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0090offcore_response.all_pf_data_rd.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000090offcore_response.all_pf_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000090offcore_response.all_pf_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000090offcore_response.all_pf_data_rd.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000090offcore_response.all_pf_data_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000090offcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000090offcore_response.all_pf_data_rd.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020090offcore_response.all_pf_rfo.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0120offcore_response.all_pf_rfo.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000120offcore_response.all_pf_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000120offcore_response.all_pf_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000120offcore_response.all_pf_rfo.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000120offcore_response.all_pf_rfo.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000120offcore_response.all_pf_rfo.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000120offcore_response.all_pf_rfo.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020120offcore_response.all_rfo.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0122offcore_response.all_rfo.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000122offcore_response.all_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000122offcore_response.all_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000122offcore_response.all_rfo.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000122offcore_response.all_rfo.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000122offcore_response.all_rfo.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000122offcore_response.all_rfo.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000122offcore_response.all_rfo.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000122offcore_response.all_rfo.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000122offcore_response.all_rfo.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000122offcore_response.all_rfo.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000122offcore_response.all_rfo.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020122offcore_response.corewb.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0008offcore_response.corewb.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000008offcore_response.corewb.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000008offcore_response.corewb.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000008offcore_response.corewb.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000008offcore_response.corewb.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000008offcore_response.corewb.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000008offcore_response.corewb.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000008offcore_response.corewb.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000008offcore_response.corewb.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000008offcore_response.corewb.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000008offcore_response.corewb.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000008offcore_response.corewb.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020008offcore_response.demand_code_rd.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0004offcore_response.demand_code_rd.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000004offcore_response.demand_code_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000004offcore_response.demand_code_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000004offcore_response.demand_code_rd.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000004offcore_response.demand_code_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000004offcore_response.demand_code_rd.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000004offcore_response.demand_code_rd.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020004offcore_response.demand_data_rd.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0001offcore_response.demand_data_rd.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000001offcore_response.demand_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000001offcore_response.demand_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000001offcore_response.demand_data_rd.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000001offcore_response.demand_data_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000001offcore_response.demand_data_rd.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000001offcore_response.demand_data_rd.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020001offcore_response.demand_rfo.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0002offcore_response.demand_rfo.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000002offcore_response.demand_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000002offcore_response.demand_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000002offcore_response.demand_rfo.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000002offcore_response.demand_rfo.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000002offcore_response.other.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C8000offcore_response.other.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C008000offcore_response.other.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C008000offcore_response.other.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC008000offcore_response.other.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C008000offcore_response.other.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84008000offcore_response.other.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004008000offcore_response.other.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404008000offcore_response.other.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204008000offcore_response.other.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084008000offcore_response.other.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004008000offcore_response.other.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104008000offcore_response.other.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000028000offcore_response.pf_l2_code_rd.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0040offcore_response.pf_l2_code_rd.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000040offcore_response.pf_l2_code_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000040offcore_response.pf_l2_code_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000040offcore_response.pf_l2_code_rd.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000040offcore_response.pf_l2_code_rd.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000040offcore_response.pf_l2_code_rd.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020040offcore_response.pf_l2_data_rd.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0010offcore_response.pf_l2_data_rd.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000010offcore_response.pf_l2_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000010offcore_response.pf_l2_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000010offcore_response.pf_l2_data_rd.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000010offcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000010offcore_response.pf_l2_data_rd.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020010offcore_response.pf_l2_rfo.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0020offcore_response.pf_l2_rfo.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000020offcore_response.pf_l2_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000020offcore_response.pf_l2_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000020offcore_response.pf_l2_rfo.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000020offcore_response.pf_l2_rfo.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000020offcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000020offcore_response.pf_l2_rfo.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020020offcore_response.pf_l3_code_rd.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0200offcore_response.pf_l3_code_rd.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000200offcore_response.pf_l3_code_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000200offcore_response.pf_l3_code_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000200offcore_response.pf_l3_code_rd.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000200offcore_response.pf_l3_code_rd.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000200offcore_response.pf_l3_code_rd.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020200offcore_response.pf_l3_data_rd.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0080offcore_response.pf_l3_data_rd.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000080offcore_response.pf_l3_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000080offcore_response.pf_l3_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000080offcore_response.pf_l3_data_rd.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000080offcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000080offcore_response.pf_l3_data_rd.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020080offcore_response.pf_l3_rfo.l3_hit.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20003C0100offcore_response.pf_l3_rfo.l3_miss.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x043C000100offcore_response.pf_l3_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x023C000100offcore_response.pf_l3_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00BC000100offcore_response.pf_l3_rfo.l3_miss.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x013C000100offcore_response.pf_l3_rfo.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0404000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0204000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0084000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000100offcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0104000100offcore_response.pf_l3_rfo.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020100Number of times RTM abort was triggered (Precise event)Number of times RTM abort was triggered  (Precise event)Conditional branch instructions retired (Precise event)This event counts conditional branch instructions retired (Precise event)Direct and indirect near call instructions retired (Precise event)This event counts both direct and indirect near call instructions retired (Precise event)Direct and indirect macro near call instructions retired (captured in ring 3) (Precise event)This event counts both direct and indirect macro near call instructions retired (captured in ring 3) (Precise event)Return instructions retired (Precise event)This event counts return instructions retired (Precise event)Taken branch instructions retired (Precise event)This event counts taken branch instructions retired (Precise event)Mispredicted conditional branch instructions retired (Precise event)This event counts mispredicted conditional branch instructions retired (Precise event)number of near branch instructions retired that were mispredicted and taken (Precise event)Number of near branch instructions retired that were mispredicted and taken (Precise event)This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event)This event counts mispredicted return instructions retired (Precise event)event=0x3c,period=100003,umask=0x2event=0x3c,period=100003,umask=0x1event=0x3c,any=1,period=100003,umask=0x1This event counts resource-related stall cyclesActually retired uops (Precise event)This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight (Precise event)Retirement slots used (Precise event)This event counts the number of retirement slots used (Precise event)unc_cbo_xsnp_response.miss_xcoreevent=0x22,umask=0x41A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core. Unit: uncore_cbox uncoreA cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor coreunc_cbo_xsnp_response.miss_evictionevent=0x22,umask=0x81A cross-core snoop resulted from L3 Eviction which misses in some processor core. Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which misses in some processor coreunc_cbo_xsnp_response.hit_xcoreevent=0x22,umask=0x44A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core. Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor coreunc_cbo_xsnp_response.hitm_xcoreevent=0x22,umask=0x48A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core. Unit: uncore_cbox A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor coreunc_cbo_cache_lookup.read_mevent=0x34,umask=0x11L3 Lookup read request that access cache and found line in M-state. Unit: uncore_cbox L3 Lookup read request that access cache and found line in M-stateunc_cbo_cache_lookup.write_mevent=0x34,umask=0x21L3 Lookup write request that access cache and found line in M-state. Unit: uncore_cbox L3 Lookup write request that access cache and found line in M-stateunc_cbo_cache_lookup.any_mevent=0x34,umask=0x81L3 Lookup any request that access cache and found line in M-state. Unit: uncore_cbox L3 Lookup any request that access cache and found line in M-stateunc_cbo_cache_lookup.read_ievent=0x34,umask=0x18L3 Lookup read request that access cache and found line in I-state. Unit: uncore_cbox L3 Lookup read request that access cache and found line in I-stateunc_cbo_cache_lookup.any_ievent=0x34,umask=0x88L3 Lookup any request that access cache and found line in I-state. Unit: uncore_cbox L3 Lookup any request that access cache and found line in I-stateunc_cbo_cache_lookup.read_mesievent=0x34,umask=0x1fL3 Lookup read request that access cache and found line in any MESI-state. Unit: uncore_cbox L3 Lookup read request that access cache and found line in any MESI-stateunc_cbo_cache_lookup.write_mesievent=0x34,umask=0x2fL3 Lookup write request that access cache and found line in MESI-state. Unit: uncore_cbox L3 Lookup write request that access cache and found line in MESI-stateunc_cbo_cache_lookup.any_mesievent=0x34,umask=0x8fL3 Lookup any request that access cache and found line in MESI-state. Unit: uncore_cbox L3 Lookup any request that access cache and found line in MESI-stateunc_cbo_cache_lookup.any_esevent=0x34,umask=0x86L3 Lookup any request that access cache and found line in E or S-state. Unit: uncore_cbox L3 Lookup any request that access cache and found line in E or S-stateunc_cbo_cache_lookup.read_esevent=0x34,umask=0x16L3 Lookup read request that access cache and found line in E or S-state. Unit: uncore_cbox L3 Lookup read request that access cache and found line in E or S-stateunc_cbo_cache_lookup.write_esevent=0x34,umask=0x26L3 Lookup write request that access cache and found line in E or S-state. Unit: uncore_cbox L3 Lookup write request that access cache and found line in E or S-stateunc_arb_trk_occupancy.allevent=0x80,umask=0x01Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic. Unit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficuncore_arbunc_arb_trk_occupancy.drd_directevent=0x80,umask=0x02Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case. Unit: uncore_arb Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal caseunc_arb_trk_requests.allevent=0x81,umask=0x01Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic. Unit: uncore_arb Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent trafficunc_arb_trk_requests.drd_directevent=0x81,umask=0x02Number of Core coherent Data Read entries allocated in DirectData mode. Unit: uncore_arb Number of Core coherent Data Read entries allocated in DirectData modeunc_arb_trk_requests.writesevent=0x81,umask=0x20Number of Writes allocated - any write transactions: full/partials writes and evictions. Unit: uncore_arb Number of Writes allocated - any write transactions: full/partials writes and evictionsunc_arb_coh_trk_requests.allevent=0x84,umask=0x01Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc. Unit: uncore_arb Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etcunc_arb_trk_occupancy.cycles_with_any_requestevent=0x80,cmask=1,umask=0x01Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;. Unit: uncore_arb Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCunc_clock.socketevent=0,umask=0x01This 48-bit fixed counter counts the UCLK cycles. Unit: uncore_ncu This 48-bit fixed counter counts the UCLK cyclesuncore_ncubdx metrics( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: BDE70 (Precise event)Retired load uop whose Data Source was: forwarded from remote cache  Supports address when precise.  Spec update: BDE70 (Precise event)Retired load uop whose Data Source was: Remote cache HITM  Supports address when precise.  Spec update: BDE70 (Precise event)offcore_response.all_code_rd.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C0244Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_data_rd.llc_hit.hitm_other_coreCounts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_data_rd.llc_hit.hit_other_core_no_fwdCounts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_reads.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C07F7Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_reads.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x04003C07F7Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_requests.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C8FFFCounts all requests hit in the L3offcore_response.all_rfo.llc_hit.hitm_other_coreCounts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_rfo.llc_hit.hit_other_core_no_fwdCounts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_rfo.llc_hit.any_responseCounts all demand data writes (RFOs) hit in the L3offcore_response.demand_rfo.llc_hit.hitm_other_coreCounts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_llc_code_rd.llc_hit.any_responseCounts prefetch (that bring data to LLC only) code reads hit in the L3offcore_response.pf_llc_rfo.llc_hit.any_responseCounts all prefetch (that bring data to LLC only) RFOs hit in the L3offcore_response.all_code_rd.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00244Counts all demand & prefetch code reads miss in the L3offcore_response.all_code_rd.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0604000244Counts all demand & prefetch code reads miss the L3 and the data is returned from local dramoffcore_response.all_data_rd.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00091Counts all demand & prefetch data reads miss in the L3offcore_response.all_data_rd.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0604000091Counts all demand & prefetch data reads miss the L3 and the data is returned from local dramoffcore_response.all_data_rd.llc_miss.remote_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x063BC00091Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dramoffcore_response.all_data_rd.llc_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00091Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cacheoffcore_response.all_data_rd.llc_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x087FC00091Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_reads.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC007F7Counts all data/code/rfo reads (demand & prefetch) miss in the L3offcore_response.all_reads.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x06040007F7Counts all data/code/rfo reads (demand & prefetch)miss the L3 and the data is returned from local dramoffcore_response.all_reads.llc_miss.remote_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x063BC007F7Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dramoffcore_response.all_reads.llc_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC007F7Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cacheoffcore_response.all_reads.llc_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x087FC007F7Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_requests.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC08FFFCounts all requests miss in the L3offcore_response.all_rfo.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00122Counts all demand & prefetch RFOs miss in the L3offcore_response.all_rfo.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0604000122Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dramoffcore_response.demand_rfo.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00002Counts all demand data writes (RFOs) miss in the L3offcore_response.demand_rfo.llc_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00002Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cacheoffcore_response.pf_llc_code_rd.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00200Counts prefetch (that bring data to LLC only) code reads miss in the L3offcore_response.pf_llc_rfo.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00100Counts all prefetch (that bring data to LLC only) RFOs miss in the L3unc_q_clockticksevent=0x14QPI clock ticks. Unit: uncore_qpi uncore interconnectuncore_qpiqpi_data_bandwidth_txevent=0,umask=0x2Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data. Unit: uncore_qpi 8Bytesqpi_ctl_bandwidth_txevent=0,umask=0x4Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data. Unit: uncore_qpi unc_m_clockticks(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100.(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.l1d_cache.all_cache_refevent=0x40,period=2000000,umask=0xa3L1 Data Cacheable reads and writesl1d_cache.all_refevent=0x40,period=2000000,umask=0x83L1 Data reads and writesl1d_cache.evictevent=0x40,period=200000,umask=0x10Modified cache lines evicted from the L1 data cachel1d_cache.ldevent=0x40,period=2000000,umask=0xa1L1 Cacheable Data Readsl1d_cache.replevent=0x40,period=200000,umask=0x8L1 Data line replacementsl1d_cache.replmevent=0x40,period=200000,umask=0x48Modified cache lines allocated in the L1 data cachel1d_cache.stevent=0x40,period=2000000,umask=0xa2L1 Cacheable Data Writesl2_ads.selfevent=0x21,period=200000,umask=0x40Cycles L2 address bus is in usel2_data_rqsts.self.e_stateevent=0x2c,period=200000,umask=0x44All data requests from the L1 data cachel2_data_rqsts.self.i_stateevent=0x2c,period=200000,umask=0x41l2_data_rqsts.self.mesievent=0x2c,period=200000,umask=0x4fl2_data_rqsts.self.m_stateevent=0x2c,period=200000,umask=0x48l2_data_rqsts.self.s_stateevent=0x2c,period=200000,umask=0x42l2_dbus_busy.selfevent=0x22,period=200000,umask=0x40Cycles the L2 cache data bus is busyl2_dbus_busy_rd.selfevent=0x23,period=200000,umask=0x40Cycles the L2 transfers data to the corel2_ifetch.self.e_stateevent=0x28,period=200000,umask=0x44L2 cacheable instruction fetch requestsl2_ifetch.self.i_stateevent=0x28,period=200000,umask=0x41l2_ifetch.self.mesievent=0x28,period=200000,umask=0x4fl2_ifetch.self.m_stateevent=0x28,period=200000,umask=0x48l2_ifetch.self.s_stateevent=0x28,period=200000,umask=0x42l2_ld.self.any.e_stateevent=0x29,period=200000,umask=0x74L2 cache readsl2_ld.self.any.i_stateevent=0x29,period=200000,umask=0x71l2_ld.self.any.mesievent=0x29,period=200000,umask=0x7fl2_ld.self.any.m_stateevent=0x29,period=200000,umask=0x78l2_ld.self.any.s_stateevent=0x29,period=200000,umask=0x72l2_ld.self.demand.e_stateevent=0x29,period=200000,umask=0x44l2_ld.self.demand.i_stateevent=0x29,period=200000,umask=0x41l2_ld.self.demand.mesievent=0x29,period=200000,umask=0x4fl2_ld.self.demand.m_stateevent=0x29,period=200000,umask=0x48l2_ld.self.demand.s_stateevent=0x29,period=200000,umask=0x42l2_ld.self.prefetch.e_stateevent=0x29,period=200000,umask=0x54l2_ld.self.prefetch.i_stateevent=0x29,period=200000,umask=0x51l2_ld.self.prefetch.mesievent=0x29,period=200000,umask=0x5fl2_ld.self.prefetch.m_stateevent=0x29,period=200000,umask=0x58l2_ld.self.prefetch.s_stateevent=0x29,period=200000,umask=0x52l2_ld_ifetch.self.e_stateevent=0x2d,period=200000,umask=0x44All read requests from L1 instruction and data cachesl2_ld_ifetch.self.i_stateevent=0x2d,period=200000,umask=0x41l2_ld_ifetch.self.mesievent=0x2d,period=200000,umask=0x4fl2_ld_ifetch.self.m_stateevent=0x2d,period=200000,umask=0x48l2_ld_ifetch.self.s_stateevent=0x2d,period=200000,umask=0x42l2_lines_in.self.anyevent=0x24,period=200000,umask=0x70L2 cache missesl2_lines_in.self.demandevent=0x24,period=200000,umask=0x40l2_lines_in.self.prefetchevent=0x24,period=200000,umask=0x50l2_lines_out.self.anyevent=0x26,period=200000,umask=0x70L2 cache lines evictedl2_lines_out.self.demandevent=0x26,period=200000,umask=0x40l2_lines_out.self.prefetchevent=0x26,period=200000,umask=0x50l2_lock.self.e_stateevent=0x2b,period=200000,umask=0x44L2 locked accessesl2_lock.self.i_stateevent=0x2b,period=200000,umask=0x41l2_lock.self.mesievent=0x2b,period=200000,umask=0x4fl2_lock.self.m_stateevent=0x2b,period=200000,umask=0x48l2_lock.self.s_stateevent=0x2b,period=200000,umask=0x42l2_m_lines_in.selfevent=0x25,period=200000,umask=0x40L2 cache line modificationsl2_m_lines_out.self.anyevent=0x27,period=200000,umask=0x70Modified lines evicted from the L2 cachel2_m_lines_out.self.demandevent=0x27,period=200000,umask=0x40l2_m_lines_out.self.prefetchevent=0x27,period=200000,umask=0x50l2_no_req.selfevent=0x32,period=200000,umask=0x40Cycles no L2 cache requests are pendingl2_reject_busq.self.any.e_stateevent=0x30,period=200000,umask=0x74Rejected L2 cache requestsl2_reject_busq.self.any.i_stateevent=0x30,period=200000,umask=0x71l2_reject_busq.self.any.mesievent=0x30,period=200000,umask=0x7fl2_reject_busq.self.any.m_stateevent=0x30,period=200000,umask=0x78l2_reject_busq.self.any.s_stateevent=0x30,period=200000,umask=0x72l2_reject_busq.self.demand.e_stateevent=0x30,period=200000,umask=0x44l2_reject_busq.self.demand.i_stateevent=0x30,period=200000,umask=0x41l2_reject_busq.self.demand.mesievent=0x30,period=200000,umask=0x4fl2_reject_busq.self.demand.m_stateevent=0x30,period=200000,umask=0x48l2_reject_busq.self.demand.s_stateevent=0x30,period=200000,umask=0x42l2_reject_busq.self.prefetch.e_stateevent=0x30,period=200000,umask=0x54l2_reject_busq.self.prefetch.i_stateevent=0x30,period=200000,umask=0x51l2_reject_busq.self.prefetch.mesievent=0x30,period=200000,umask=0x5fl2_reject_busq.self.prefetch.m_stateevent=0x30,period=200000,umask=0x58l2_reject_busq.self.prefetch.s_stateevent=0x30,period=200000,umask=0x52l2_rqsts.self.any.e_stateevent=0x2e,period=200000,umask=0x74L2 cache requestsl2_rqsts.self.any.i_stateevent=0x2e,period=200000,umask=0x71l2_rqsts.self.any.mesievent=0x2e,period=200000,umask=0x7fl2_rqsts.self.any.m_stateevent=0x2e,period=200000,umask=0x78l2_rqsts.self.any.s_stateevent=0x2e,period=200000,umask=0x72l2_rqsts.self.demand.e_stateevent=0x2e,period=200000,umask=0x44l2_rqsts.self.demand.i_stateevent=0x2e,period=200000,umask=0x41L2 cache demand requests from this core that missed the L2l2_rqsts.self.demand.mesievent=0x2e,period=200000,umask=0x4fL2 cache demand requests from this corel2_rqsts.self.demand.m_stateevent=0x2e,period=200000,umask=0x48l2_rqsts.self.demand.s_stateevent=0x2e,period=200000,umask=0x42l2_rqsts.self.prefetch.e_stateevent=0x2e,period=200000,umask=0x54l2_rqsts.self.prefetch.i_stateevent=0x2e,period=200000,umask=0x51l2_rqsts.self.prefetch.mesievent=0x2e,period=200000,umask=0x5fl2_rqsts.self.prefetch.m_stateevent=0x2e,period=200000,umask=0x58l2_rqsts.self.prefetch.s_stateevent=0x2e,period=200000,umask=0x52l2_st.self.e_stateevent=0x2a,period=200000,umask=0x44L2 store requestsl2_st.self.i_stateevent=0x2a,period=200000,umask=0x41l2_st.self.mesievent=0x2a,period=200000,umask=0x4fl2_st.self.m_stateevent=0x2a,period=200000,umask=0x48l2_st.self.s_stateevent=0x2a,period=200000,umask=0x42mem_load_retired.l2_hitevent=0xcb,period=200000,umask=0x1Retired loads that hit the L2 cache (precise event)mem_load_retired.l2_missevent=0xcb,period=10000,umask=0x2Retired loads that miss the L2 cachefp_assist.arevent=0x11,period=10000,umask=0x81Floating point assists for retired operationsfp_assist.sevent=0x11,period=10000,umask=0x1Floating point assistssimd_assistevent=0xcd,period=100000,umask=0x0SIMD assists invokedsimd_comp_inst_retired.packed_singleevent=0xca,period=2000000,umask=0x1Retired computational Streaming SIMD Extensions (SSE) packed-single instructionssimd_comp_inst_retired.scalar_doubleevent=0xca,period=2000000,umask=0x8Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructionssimd_comp_inst_retired.scalar_singleevent=0xca,period=2000000,umask=0x2Retired computational Streaming SIMD Extensions (SSE) scalar-single instructionssimd_instr_retiredevent=0xce,period=2000000,umask=0x0SIMD Instructions retiredsimd_inst_retired.packed_singleevent=0xc7,period=2000000,umask=0x1Retired Streaming SIMD Extensions (SSE) packed-single instructionssimd_inst_retired.scalar_doubleevent=0xc7,period=2000000,umask=0x8Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructionssimd_inst_retired.scalar_singleevent=0xc7,period=2000000,umask=0x2Retired Streaming SIMD Extensions (SSE) scalar-single instructionssimd_inst_retired.vectorevent=0xc7,period=2000000,umask=0x10Retired Streaming SIMD Extensions 2 (SSE2) vector instructionssimd_sat_instr_retiredevent=0xcf,period=2000000,umask=0x0Saturated arithmetic instructions retiredsimd_sat_uop_exec.arevent=0xb1,period=2000000,umask=0x80SIMD saturated arithmetic micro-ops retiredsimd_sat_uop_exec.sevent=0xb1,period=2000000,umask=0x0SIMD saturated arithmetic micro-ops executedsimd_uops_exec.arevent=0xb0,period=2000000,umask=0x80SIMD micro-ops retired (excluding stores) (Must be precise)simd_uops_exec.sevent=0xb0,period=2000000,umask=0x0SIMD micro-ops executed (excluding stores)simd_uop_type_exec.arithmetic.arevent=0xb3,period=2000000,umask=0xa0SIMD packed arithmetic micro-ops retiredsimd_uop_type_exec.arithmetic.sevent=0xb3,period=2000000,umask=0x20SIMD packed arithmetic micro-ops executedsimd_uop_type_exec.logical.arevent=0xb3,period=2000000,umask=0x90SIMD packed logical micro-ops retiredsimd_uop_type_exec.logical.sevent=0xb3,period=2000000,umask=0x10SIMD packed logical micro-ops executedsimd_uop_type_exec.mul.arevent=0xb3,period=2000000,umask=0x81SIMD packed multiply micro-ops retiredsimd_uop_type_exec.mul.sevent=0xb3,period=2000000,umask=0x1SIMD packed multiply micro-ops executedsimd_uop_type_exec.pack.arevent=0xb3,period=2000000,umask=0x84SIMD packed micro-ops retiredsimd_uop_type_exec.pack.sevent=0xb3,period=2000000,umask=0x4SIMD packed micro-ops executedsimd_uop_type_exec.shift.arevent=0xb3,period=2000000,umask=0x82SIMD packed shift micro-ops retiredsimd_uop_type_exec.shift.sevent=0xb3,period=2000000,umask=0x2SIMD packed shift micro-ops executedsimd_uop_type_exec.unpack.arevent=0xb3,period=2000000,umask=0x88SIMD unpacked micro-ops retiredsimd_uop_type_exec.unpack.sevent=0xb3,period=2000000,umask=0x8SIMD unpacked micro-ops executedx87_comp_ops_exe.any.arevent=0x10,period=2000000,umask=0x81Floating point computational micro-ops retired (Must be precise)x87_comp_ops_exe.any.sevent=0x10,period=2000000,umask=0x1Floating point computational micro-ops executedx87_comp_ops_exe.fxch.arevent=0x10,period=2000000,umask=0x82FXCH uops retired (Must be precise)x87_comp_ops_exe.fxch.sevent=0x10,period=2000000,umask=0x2FXCH uops executedevent=0xe6,period=2000000,umask=0x1BACLEARS assertedcycles_icache_mem_stalled.icache_mem_stalledevent=0x86,period=2000000,umask=0x1Cycles during which instruction fetches are  stalleddecode_stall.iq_fullevent=0x87,period=2000000,umask=0x2Decode stall due to IQ fulldecode_stall.pfb_emptyevent=0x87,period=2000000,umask=0x1Decode stall due to PFB emptyicache.accessesevent=0x80,period=200000,umask=0x3Instruction fetchesevent=0x80,period=200000,umask=0x1Icache hitevent=0x80,period=200000,umask=0x2Icache missmacro_insts.all_decodedevent=0xaa,period=2000000,umask=0x3All Instructions decodedmacro_insts.cisc_decodedevent=0xaa,period=2000000,umask=0x2CISC macro instructions decodedmacro_insts.non_cisc_decodedevent=0xaa,period=2000000,umask=0x1Non-CISC nacro instructions decodeduops.ms_cyclesevent=0xa9,cmask=1,period=2000000,umask=0x1This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQmisalign_mem_ref.bubbleevent=0x5,period=200000,umask=0x97Nonzero segbase 1 bubblemisalign_mem_ref.ld_bubbleevent=0x5,period=200000,umask=0x91Nonzero segbase load 1 bubblemisalign_mem_ref.ld_splitevent=0x5,period=200000,umask=0x9Load splitsmisalign_mem_ref.ld_split.arevent=0x5,period=200000,umask=0x89Load splits (At Retirement)misalign_mem_ref.rmw_bubbleevent=0x5,period=200000,umask=0x94Nonzero segbase ld-op-st 1 bubblemisalign_mem_ref.rmw_splitevent=0x5,period=200000,umask=0x8cld-op-st splitsmisalign_mem_ref.splitevent=0x5,period=200000,umask=0xfMemory references that cross an 8-byte boundarymisalign_mem_ref.split.arevent=0x5,period=200000,umask=0x8fMemory references that cross an 8-byte boundary (At Retirement)misalign_mem_ref.st_bubbleevent=0x5,period=200000,umask=0x92Nonzero segbase store 1 bubblemisalign_mem_ref.st_splitevent=0x5,period=200000,umask=0xaStore splitsmisalign_mem_ref.st_split.arevent=0x5,period=200000,umask=0x8aStore splits (Ar Retirement)prefetch.hw_prefetchevent=0x7,period=2000000,umask=0x10L1 hardware prefetch requestprefetch.prefetchntaevent=0x7,period=200000,umask=0x88Streaming SIMD Extensions (SSE) Prefetch NTA instructions executedprefetch.prefetcht0event=0x7,period=200000,umask=0x81Streaming SIMD Extensions (SSE) PrefetchT0 instructions executedprefetch.prefetcht1event=0x7,period=200000,umask=0x82Streaming SIMD Extensions (SSE) PrefetchT1 instructions executedprefetch.prefetcht2event=0x7,period=200000,umask=0x84Streaming SIMD Extensions (SSE) PrefetchT2 instructions executedprefetch.software_prefetchevent=0x7,period=200000,umask=0xfAny Software prefetchprefetch.software_prefetch.arevent=0x7,period=200000,umask=0x8fprefetch.sw_l2event=0x7,period=200000,umask=0x86Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executedbusq_empty.selfevent=0x7d,period=200000,umask=0x40Bus queue is emptybus_bnr_drv.all_agentsevent=0x61,period=200000,umask=0x20Number of Bus Not Ready signals assertedbus_bnr_drv.this_agentevent=0x61,period=200000,umask=0x0bus_data_rcv.selfevent=0x64,period=200000,umask=0x40Bus cycles while processor receives databus_drdy_clocks.all_agentsevent=0x62,period=200000,umask=0x20Bus cycles when data is sent on the busbus_drdy_clocks.this_agentevent=0x62,period=200000,umask=0x0bus_hitm_drv.all_agentsevent=0x7b,period=200000,umask=0x20HITM signal assertedbus_hitm_drv.this_agentevent=0x7b,period=200000,umask=0x0bus_hit_drv.all_agentsevent=0x7a,period=200000,umask=0x20HIT signal assertedbus_hit_drv.this_agentevent=0x7a,period=200000,umask=0x0bus_io_wait.selfevent=0x7f,period=200000,umask=0x40IO requests waiting in the bus queuebus_lock_clocks.all_agentsevent=0x63,period=200000,umask=0xe0Bus cycles when a LOCK signal is assertedbus_lock_clocks.selfevent=0x63,period=200000,umask=0x40bus_request_outstanding.all_agentsevent=0x60,period=200000,umask=0xe0Outstanding cacheable data read bus requests durationbus_request_outstanding.selfevent=0x60,period=200000,umask=0x40bus_trans_any.all_agentsevent=0x70,period=200000,umask=0xe0All bus transactionsbus_trans_any.selfevent=0x70,period=200000,umask=0x40bus_trans_brd.all_agentsevent=0x65,period=200000,umask=0xe0Burst read bus transactionsbus_trans_brd.selfevent=0x65,period=200000,umask=0x40bus_trans_burst.all_agentsevent=0x6e,period=200000,umask=0xe0Burst (full cache-line) bus transactionsbus_trans_burst.selfevent=0x6e,period=200000,umask=0x40bus_trans_def.all_agentsevent=0x6d,period=200000,umask=0xe0Deferred bus transactionsbus_trans_def.selfevent=0x6d,period=200000,umask=0x40bus_trans_ifetch.all_agentsevent=0x68,period=200000,umask=0xe0Instruction-fetch bus transactionsbus_trans_ifetch.selfevent=0x68,period=200000,umask=0x40bus_trans_inval.all_agentsevent=0x69,period=200000,umask=0xe0Invalidate bus transactionsbus_trans_inval.selfevent=0x69,period=200000,umask=0x40bus_trans_io.all_agentsevent=0x6c,period=200000,umask=0xe0IO bus transactionsbus_trans_io.selfevent=0x6c,period=200000,umask=0x40bus_trans_mem.all_agentsevent=0x6f,period=200000,umask=0xe0Memory bus transactionsbus_trans_mem.selfevent=0x6f,period=200000,umask=0x40bus_trans_p.all_agentsevent=0x6b,period=200000,umask=0xe0Partial bus transactionsbus_trans_p.selfevent=0x6b,period=200000,umask=0x40bus_trans_pwr.all_agentsevent=0x6a,period=200000,umask=0xe0Partial write bus transactionbus_trans_pwr.selfevent=0x6a,period=200000,umask=0x40bus_trans_rfo.all_agentsevent=0x66,period=200000,umask=0xe0RFO bus transactionsbus_trans_rfo.selfevent=0x66,period=200000,umask=0x40bus_trans_wb.all_agentsevent=0x67,period=200000,umask=0xe0Explicit writeback bus transactionsbus_trans_wb.selfevent=0x67,period=200000,umask=0x40cycles_int_masked.cycles_int_maskedevent=0xc6,period=2000000,umask=0x1Cycles during which interrupts are disabledcycles_int_masked.cycles_int_pending_and_maskedevent=0xc6,period=2000000,umask=0x2Cycles during which interrupts are pending and disableddispatch_blocked.anyevent=0x9,period=200000,umask=0x20Memory cluster signals to block micro-op dispatch for any reasoneist_transevent=0x3a,period=200000,umask=0x0Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitionsext_snoop.all_agents.anyevent=0x77,period=200000,umask=0x2bExternal snoopsext_snoop.all_agents.cleanevent=0x77,period=200000,umask=0x21ext_snoop.all_agents.hitevent=0x77,period=200000,umask=0x22ext_snoop.all_agents.hitmevent=0x77,period=200000,umask=0x28ext_snoop.this_agent.anyevent=0x77,period=200000,umask=0xbext_snoop.this_agent.cleanevent=0x77,period=200000,umask=0x1ext_snoop.this_agent.hitevent=0x77,period=200000,umask=0x2ext_snoop.this_agent.hitmevent=0x77,period=200000,umask=0x8hw_int_rcvevent=0xc8,period=200000,umask=0x0Hardware interrupts receivedsegment_reg_loads.anyevent=0x6,period=200000,umask=0x80Number of segment register loadssnoop_stall_drv.all_agentsevent=0x7e,period=200000,umask=0xe0Bus stalled for snoopssnoop_stall_drv.selfevent=0x7e,period=200000,umask=0x40thermal_tripevent=0x3b,period=200000,umask=0xc0Number of thermal tripsbogus_brevent=0xe4,period=2000000,umask=0x1Bogus branchesbr_inst_decodedevent=0xe0,period=2000000,umask=0x1Branch instructions decodedbr_inst_retired.anyevent=0xc4,period=2000000,umask=0x0Retired branch instructionsbr_inst_retired.any1event=0xc4,period=2000000,umask=0xfbr_inst_retired.mispredevent=0xc5,period=200000,umask=0x0Retired mispredicted branch instructions (precise event) (Precise event)br_inst_retired.mispred_not_takenevent=0xc4,period=200000,umask=0x2Retired branch instructions that were mispredicted not-takenbr_inst_retired.mispred_takenevent=0xc4,period=200000,umask=0x8Retired branch instructions that were mispredicted takenbr_inst_retired.pred_not_takenevent=0xc4,period=2000000,umask=0x1Retired branch instructions that were predicted not-takenbr_inst_retired.pred_takenevent=0xc4,period=2000000,umask=0x4Retired branch instructions that were predicted takenbr_inst_retired.takenevent=0xc4,period=2000000,umask=0xcRetired taken branch instructionsbr_inst_type_retired.condevent=0x88,period=2000000,umask=0x1All macro conditional branch instructionsbr_inst_type_retired.cond_takenevent=0x88,period=2000000,umask=0x41Only taken macro conditional branch instructionsbr_inst_type_retired.dir_callevent=0x88,period=2000000,umask=0x10All non-indirect callsbr_inst_type_retired.indevent=0x88,period=2000000,umask=0x4All indirect branches that are not callsbr_inst_type_retired.ind_callevent=0x88,period=2000000,umask=0x20All indirect calls, including both register and memory indirectbr_inst_type_retired.retevent=0x88,period=2000000,umask=0x8All indirect branches that have a return mnemonicbr_inst_type_retired.uncondevent=0x88,period=2000000,umask=0x2All macro unconditional branch instructions, excluding calls and indirectsbr_missp_type_retired.condevent=0x89,period=200000,umask=0x1Mispredicted cond branch instructions retiredbr_missp_type_retired.cond_takenevent=0x89,period=200000,umask=0x11Mispredicted and taken cond branch instructions retiredbr_missp_type_retired.indevent=0x89,period=200000,umask=0x2Mispredicted ind branches that are not callsbr_missp_type_retired.ind_callevent=0x89,period=200000,umask=0x8Mispredicted indirect calls, including both register and memory indirectbr_missp_type_retired.returnevent=0x89,period=200000,umask=0x4Mispredicted return branchescpu_clk_unhalted.busevent=0x3c,period=200000,umask=0x1Bus cycles when core is not haltedcpu_clk_unhalted.coreevent=0xa,period=2000000,umask=0x0Core cycles when core is not haltedcpu_clk_unhalted.core_pevent=0x3c,period=2000000,umask=0x0cpu_clk_unhalted.refReference cycles when core is not haltedcycles_div_busyevent=0x14,period=2000000,umask=0x1Cycles the divider is busydiv.arevent=0x13,period=2000000,umask=0x81Divide operations retireddiv.sevent=0x13,period=2000000,umask=0x1Divide operations executedInstructions retiredevent=0xc0,period=2000000,umask=0x0Instructions retired (precise event) (Must be precise)event=0xc3,period=200000,umask=0x1Self-Modifying Code detectedmul.arevent=0x12,period=2000000,umask=0x81Multiply operations retiredmul.sevent=0x12,period=2000000,umask=0x1Multiply operations executedreissue.anyevent=0x3,period=200000,umask=0x7fMicro-op reissues for any causereissue.any.arevent=0x3,period=200000,umask=0xffMicro-op reissues for any cause (At Retirement)reissue.overlap_storeevent=0x3,period=200000,umask=0x1Micro-op reissues on a store-load collisionreissue.overlap_store.arevent=0x3,period=200000,umask=0x81Micro-op reissues on a store-load collision (At Retirement)resource_stalls.div_busyevent=0xdc,period=2000000,umask=0x2Cycles issue is stalled due to div busystore_forwards.anyevent=0x2,period=200000,umask=0x83All store forwardsstore_forwards.goodevent=0x2,period=200000,umask=0x81Good store forwardsuops_retired.anyevent=0xc2,period=2000000,umask=0x10Micro-ops retireduops_retired.stalled_cyclesCycles no micro-ops retireduops_retired.stallsPeriods no micro-ops retireddata_tlb_misses.dtlb_missevent=0x8,period=200000,umask=0x7Memory accesses that missed the DTLBdata_tlb_misses.dtlb_miss_ldevent=0x8,period=200000,umask=0x5DTLB misses due to load operationsdata_tlb_misses.dtlb_miss_stevent=0x8,period=200000,umask=0x6DTLB misses due to store operationsdata_tlb_misses.l0_dtlb_miss_ldevent=0x8,period=200000,umask=0x9L0 DTLB misses due to load operationsdata_tlb_misses.l0_dtlb_miss_stevent=0x8,period=200000,umask=0xaL0 DTLB misses due to store operationsitlb.flushevent=0x82,period=200000,umask=0x4ITLB flushesitlb.hitevent=0x82,period=200000,umask=0x1ITLB hitsitlb.missesevent=0x82,period=200000,umask=0x2ITLB misses (Must be precise)mem_load_retired.dtlb_missevent=0xcb,period=200000,umask=0x4Retired loads that miss the DTLB (precise event) (Precise event)page_walks.cyclesevent=0xc,period=2000000,umask=0x3Duration of page-walks in core cyclespage_walks.d_side_cyclesevent=0xc,period=2000000,umask=0x1Duration of D-side only page walkspage_walks.d_side_walksevent=0xc,period=200000,umask=0x1Number of D-side only page walkspage_walks.i_side_cyclesevent=0xc,period=2000000,umask=0x2Duration of I-Side page walkspage_walks.i_side_walksevent=0xc,period=200000,umask=0x2Number of I-Side page walkspage_walks.walksevent=0xc,period=200000,umask=0x3Number of page-walks executedcore_reject_l2q.allevent=0x31,period=200003Requests rejected by the L2QCounts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoopsdl1.dirty_evictionevent=0x51,period=200003,umask=0x1L1 Cache evictions for dirty dataCounts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory.  No count will occur if the evicted line is clean, and hence does not require a writebackfetch_stall.icache_fill_pending_cyclesevent=0x86,period=200003,umask=0x2Cycles code-fetch stalled due to an outstanding ICache missCounts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchyl2_reject_xq.allevent=0x30,period=200003Requests rejected by the XQCounts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victimsevent=0x2e,period=200003,umask=0x41L2 cache request missesCounts memory requests originating from the core that miss in the L2 cacheevent=0x2e,period=200003,umask=0x4fCounts memory requests originating from the core that reference a cache line in the L2 cachemem_load_uops_retired.dram_hitevent=0xd1,period=200003,umask=0x80Loads retired that came from DRAM (Precise event capable)  Supports address when precise (Must be precise)Counts memory load uops retired where the data is retrieved from DRAM.  Event is counted at retirement, so the speculative loads are ignored.  A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response  Supports address when precise (Must be precise)mem_load_uops_retired.hitmevent=0xd1,period=200003,umask=0x20Memory uop retired where cross core or cross module HITM occurred (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM).  More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data.  Loads that obtain a HITM response incur greater latency than most is typical for a load.  In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value.  This event is useful for locating sharing, false sharing, and contended locks  Supports address when precise (Must be precise)event=0xd1,period=200003,umask=0x1Load uops retired that hit L1 data cache (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that hit the L1 data cache  Supports address when precise (Must be precise)event=0xd1,period=200003,umask=0x8Load uops retired that missed L1 data cache (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that miss the L1 data cache  Supports address when precise (Must be precise)event=0xd1,period=200003,umask=0x2Load uops retired that hit L2 (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that hit in the L2 cache  Supports address when precise (Must be precise)event=0xd1,period=200003,umask=0x10Load uops retired that missed L2 (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that miss in the L2 cache  Supports address when precise (Must be precise)mem_load_uops_retired.wcb_hitevent=0xd1,period=200003,umask=0x40Loads retired that hit WCB (Precise event capable)  Supports address when precise (Must be precise)Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache.  Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache.  If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data.  When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs  Supports address when precise (Must be precise)mem_uops_retired.allevent=0xd0,period=200003,umask=0x83Memory uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts the number of memory uops retired that is either a loads or a store or both  Supports address when precise (Must be precise)event=0xd0,period=200003,umask=0x81Load uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts the number of load uops retired  Supports address when precise (Must be precise)event=0xd0,period=200003,umask=0x82Store uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts the number of store uops retired  Supports address when precise (Must be precise)event=0xd0,period=200003,umask=0x21Locked load uops retired (Precise event capable)  Supports address when precise (Must be precise)Counts locked memory uops retired.  This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.)  A locked access is one with a lock prefix, or an exchange to memory.  See the SDM for a complete description of which memory load accesses are locks  Supports address when precise (Must be precise)mem_uops_retired.splitevent=0xd0,period=200003,umask=0x43Memory uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise)Counts memory uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise)event=0xd0,period=200003,umask=0x41Load uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise)event=0xd0,period=200003,umask=0x42Stores uops retired that split a cache-line (Precise event capable)  Supports address when precise (Must be precise)Counts store uops retired where the data requested spans a 64 byte cache line boundary  Supports address when precise (Must be precise)event=0xb7,period=100007,umask=0x1Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000043091Counts data reads (demand & prefetch) that hit the L2 cacheCounts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600003091Counts data reads (demand & prefetch) that miss the L2 cacheCounts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000003091Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400003091Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200003091Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000043010Counts data reads generated by L1 or L2 prefetchers that hit the L2 cacheCounts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600003010Counts data reads generated by L1 or L2 prefetchers that miss the L2 cacheCounts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000003010Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400003010Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200003010Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000432b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cacheCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x36000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cacheCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x10000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x04000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x02000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000018000Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystemCounts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000048000Counts requests to the uncore subsystem that hit the L2 cacheCounts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000008000Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400008000Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200008000Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor moduleCounts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040022Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cacheCounts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000022Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cacheCounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000022Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000022Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000022Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010400Counts bus lock and split lock requests that have any transaction responses from the uncore subsystemCounts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040008Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cacheCounts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000008Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cacheCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000008Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000008Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000008Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor moduleCounts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cacheCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cacheCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040001Counts demand cacheable data reads of full cache lines that hit the L2 cacheCounts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000001Counts demand cacheable data reads of full cache lines that miss the L2 cacheCounts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000001Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000001Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000001Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_data_rd.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000001Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cacheCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cacheCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_rfo.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cacheCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cacheCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor moduleCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_reads.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000080Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cacheCounts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000044000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cacheCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600004000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cacheCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000004000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400004000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_streaming_stores.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200004000Counts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor moduleCounts partial cache line data writes to uncacheable write combining (USWC) memory region  that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.partial_writes.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000100Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cacheCounts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000042000Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cacheCounts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600002000Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cacheCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000002000Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400002000Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200002000Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040010Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000010Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000010Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000010Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000010Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040020Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cacheCounts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600000020Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cacheCounts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000020Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000020Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000020Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000044800Counts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cacheCounts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600004800Counts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cacheCounts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000041000Counts data cache lines requests by software prefetch instructions that hit the L2 cacheCounts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x3600001000Counts data cache lines requests by software prefetch instructions that miss the L2 cacheCounts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000001000Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400001000Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is requiredCounts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200001000Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)cycles_div_busy.fpdivevent=0xcd,period=200003,umask=0x2Cycles the FP divide unit is busyCounts core cycles the floating point divide unit is busymachine_clears.fp_assistevent=0xc3,period=200003,umask=0x4Machine clears due to FP assistsCounts machine clears due to floating point (FP) operations needing assists.  For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal resultuops_retired.fpdivevent=0xc2,period=2000003,umask=0x8Floating point divide uops retired. (Precise Event Capable) (Must be precise)Counts the number of floating point divide uops retired (Must be precise)baclears.allevent=0xe6,period=200003,umask=0x1BACLEARs asserted for any branch typeCounts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call,  Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returnsbaclears.condevent=0xe6,period=200003,umask=0x10BACLEARs asserted for conditional branchCounts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branchesbaclears.returnevent=0xe6,period=200003,umask=0x8BACLEARs asserted for return branchCounts BACLEARS on return instructionsdecode_restriction.predecode_wrongevent=0xe9,period=200003,umask=0x1Decode restrictions due to predicting wrong instruction lengthCounts the number of times the prediction (from the predecode cache) for instruction length is incorrectevent=0x80,period=200003,umask=0x3References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitectureCounts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.
This event counts differently than Intel processors based on Silvermont microarchitectureevent=0x80,period=200003,umask=0x1References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitectureCounts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).  The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitectureReferences per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitectureCounts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecturems_decoded.ms_entryevent=0xe7,period=200003,umask=0x1MS decode startsCounts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops.  The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clearevent=0xc3,period=200003,umask=0x2Machine clears due to memory ordering issueCounts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the datamisalign_mem_ref.load_page_splitevent=0x13,period=200003,umask=0x2Load uops that split a page (Precise event capable) (Must be precise)Counts when a memory load of a uop spans a page boundary (a split) is retired (Must be precise)misalign_mem_ref.store_page_splitevent=0x13,period=200003,umask=0x4Store uops that split a page (Precise event capable) (Must be precise)Counts when a memory store of a uop spans a page boundary (a split) is retired (Must be precise)fetch_stall.allevent=0x86,period=200003Cycles code-fetch stalled due to any reasonCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other eventsfetch_stall.itlb_fill_pending_cyclesevent=0x86,period=200003,umask=0x1Cycles code-fetch stalled due to an outstanding ITLB missCounts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss.  Note: this event is not the same as page walk cycles to retrieve an instruction translationhw_interrupts.maskedevent=0xcb,period=200003,umask=0x2Cycles hardware interrupts are maskedCounts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or nothw_interrupts.pending_and_maskedevent=0xcb,period=200003,umask=0x4Cycles pending interrupts are maskedCounts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0)hw_interrupts.receivedevent=0xcb,period=203,umask=0x1Counts hardware interrupts received by the processorevent=0xc4,period=200003Retired branch instructions (Precise event capable) (Must be precise)Counts branch instructions retired for all branch types.  This is an architectural performance event (Must be precise)br_inst_retired.all_taken_branchesevent=0xc4,period=200003,umask=0x80Retired taken branch instructions (Precise event capable) (Must be precise)Counts the number of taken branch instructions retired (Must be precise)br_inst_retired.callevent=0xc4,period=200003,umask=0xf9Retired near call instructions (Precise event capable) (Must be precise)Counts near CALL branch instructions retired (Must be precise)event=0xc4,period=200003,umask=0xbfRetired far branch instructions (Precise event capable) (Must be precise)Counts far branch instructions retired.  This includes far jump, far call and return, and Interrupt call and return (Must be precise)br_inst_retired.ind_callevent=0xc4,period=200003,umask=0xfbRetired near indirect call instructions (Precise event capable) (Must be precise)Counts near indirect CALL branch instructions retired (Must be precise)br_inst_retired.jccevent=0xc4,period=200003,umask=0x7eRetired conditional branch instructions (Precise event capable) (Must be precise)Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken (Must be precise)br_inst_retired.non_return_indevent=0xc4,period=200003,umask=0xebRetired instructions of near indirect Jmp or call (Precise event capable) (Must be precise)Counts near indirect call or near indirect jmp branch instructions retired (Must be precise)br_inst_retired.rel_callevent=0xc4,period=200003,umask=0xfdRetired near relative call instructions (Precise event capable) (Must be precise)Counts near relative CALL branch instructions retired (Must be precise)br_inst_retired.returnevent=0xc4,period=200003,umask=0xf7Retired near return instructions (Precise event capable) (Must be precise)Counts near return branch instructions retired (Must be precise)br_inst_retired.taken_jccevent=0xc4,period=200003,umask=0xfeRetired conditional branch instructions that were taken (Precise event capable) (Must be precise)Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken (Must be precise)event=0xc5,period=200003Retired mispredicted branch instructions (Precise event capable) (Must be precise)Counts mispredicted branch instructions retired including all branch types (Must be precise)br_misp_retired.ind_callevent=0xc5,period=200003,umask=0xfbRetired mispredicted near indirect call instructions (Precise event capable) (Must be precise)Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted (Must be precise)br_misp_retired.jccevent=0xc5,period=200003,umask=0x7eRetired mispredicted conditional branch instructions (Precise event capable) (Must be precise)Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition) (Must be precise)br_misp_retired.non_return_indevent=0xc5,period=200003,umask=0xebRetired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable) (Must be precise)Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted (Must be precise)br_misp_retired.returnevent=0xc5,period=200003,umask=0xf7Retired mispredicted near return instructions (Precise event capable) (Must be precise)Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted (Must be precise)br_misp_retired.taken_jccevent=0xc5,period=200003,umask=0xfeRetired mispredicted conditional branch instructions that were taken (Precise event capable) (Must be precise)Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken (Must be precise)Core cycles when core is not halted  (Fixed event)Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1.  You cannot collect a PEBs record for this eventCore cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counterReference cycles when core is not halted.  This event uses a programmable general purpose performance counterReference cycles when core is not halted  (Fixed event)Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  In mobile systems the core frequency may change from time.  This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  This event uses fixed counter 2.  You cannot collect a PEBs record for this eventcycles_div_busy.allevent=0xcd,period=2000003Cycles a divider is busyCounts core cycles if either divide unit is busycycles_div_busy.idivevent=0xcd,period=200003,umask=0x1Cycles the integer divide unit is busyCounts core cycles the integer divide unit is busyInstructions retired (Fixed event)Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this eventInstructions retired (Precise event capable) (Must be precise)Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.  Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time (Must be precise)issue_slots_not_consumed.anyevent=0xca,period=200003Unfilled issue slots per cycleCounts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource  in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY)issue_slots_not_consumed.recoveryevent=0xca,period=200003,umask=0x2Unfilled issue slots per cycle to recoverCounts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows).   Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queueissue_slots_not_consumed.resource_fullevent=0xca,period=200003,umask=0x1Unfilled issue slots per cycle because of a full resource in the backendCounts the number of issue slots per core cycle that were not consumed because of a full resource in the backend.  Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable.   Note that uops must be available for consumption in order for this event to fire.  If a uop is not available (Instruction Queue is empty), this event will not countld_blocks.4k_aliasevent=0x3,period=200003,umask=0x4Loads blocked because address has 4k partial address false dependence (Precise event capable) (Must be precise)Counts loads that block because their address modulo 4K matches a pending store (Must be precise)ld_blocks.all_blockevent=0x3,period=200003,umask=0x10Loads blocked (Precise event capable) (Must be precise)Counts anytime a load that retires is blocked for any reason (Must be precise)ld_blocks.data_unknownevent=0x3,period=200003,umask=0x1Loads blocked due to store data not ready (Precise event capable) (Must be precise)Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time.  The forward might occur subsequently when the data is available (Must be precise)event=0x3,period=200003,umask=0x2Loads blocked due to store forward restriction (Precise event capable) (Must be precise)Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted (Must be precise)ld_blocks.utlb_missevent=0x3,period=200003,umask=0x8Loads blocked because address in not in the UTLB (Precise event capable) (Must be precise)Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB) (Must be precise)machine_clears.allevent=0xc3,period=200003All machine clearsCounts machine clears for any reasonmachine_clears.disambiguationevent=0xc3,period=200003,umask=0x8Machine clears due to memory disambiguationCounts machine clears due to memory disambiguation.  Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load addressevent=0xc3,period=200003,umask=0x1Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel architecture processorsevent=0xe,period=200003Uops issued to the back end per cycleCounts uops issued by the front end and allocated into the back end of the machine.  This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clearuops_not_delivered.anyevent=0x9c,period=200003Uops requested but not-delivered to the back-end per cycleThis event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources.  When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all.  Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots.  These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots.  A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock.  The low uop issue rate for a stream of INC instructions is considered to be a back end issueevent=0xc2,period=2000003Uops retired (Precise event capable) (Must be precise)Counts uops which retired (Must be precise)uops_retired.idivevent=0xc2,period=2000003,umask=0x10Integer divide uops retired. (Precise Event Capable) (Must be precise)Counts the number of integer divide uops retired (Must be precise)uops_retired.msMS uops retired (Precise event capable) (Must be precise)Counts uops retired that are from the complex flows issued by the micro-sequencer (MS).  Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist (Must be precise)itlb.missevent=0x81,period=200003,umask=0x4ITLB missesCounts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch.  It counts when new translation are filled into the ITLB.  The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLBmem_uops_retired.dtlb_missevent=0xd0,period=200003,umask=0x13Memory uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise)Counts uops retired that had a DTLB miss on load, store or either.  Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss  Supports address when precise (Must be precise)mem_uops_retired.dtlb_miss_loadsevent=0xd0,period=200003,umask=0x11Load uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise)Counts load uops retired that caused a DTLB miss  Supports address when precise (Must be precise)mem_uops_retired.dtlb_miss_storesevent=0xd0,period=200003,umask=0x12Store uops retired that missed the DTLB (Precise event capable)  Supports address when precise (Must be precise)Counts store uops retired that caused a DTLB miss  Supports address when precise (Must be precise)event=0x5,period=200003,umask=0x3Duration of page-walks in cyclesCounts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetchevent=0x5,period=200003,umask=0x1Duration of D-side page-walks in cyclesCounts every core cycle when a Data-side (walks due to a data operation) page walk is in progressevent=0x5,period=200003,umask=0x2Duration of I-side pagewalks in cyclesCounts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progressCounts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoopsdl1.replacementoffcore_response.any_data_rd.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000013091Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystemCounts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) hit the L2 cacheCounts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_data_rd.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000003091Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000013010Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystemCounts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads generated by L1 or L2 prefetchers hit the L2 cacheCounts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor moduleCounts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_pf_data_rd.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000003010Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000132b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystemCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cacheCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor moduleCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_read.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x40000032b7Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem have any transaction responses from the uncore subsystemCounts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem hit the L2 cacheCounts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor moduleCounts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_request.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000008000Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010022Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystemCounts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cacheCounts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.any_rfo.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000022Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts bus lock and split lock requests have any transaction responses from the uncore subsystemCounts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.l2_hitevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000040400Counts bus lock and split lock requests hit the L2 cacheCounts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000400Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000400Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor moduleCounts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.bus_locks.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000400Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010008Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystemCounts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cacheCounts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor moduleCounts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.corewb.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000008Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystemCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cacheCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.demand_code_rd.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000004Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010001Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystemCounts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines hit the L2 cacheCounts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010002Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystemCounts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cacheCounts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor moduleCounts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystemCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cacheCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor moduleCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.full_streaming_stores.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000800Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000012000Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystemCounts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cacheCounts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l1_data_rd.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000002000Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010010Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystemCounts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cacheCounts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_data_rd.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000010Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010020Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystemCounts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cacheCounts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor moduleCounts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.pf_l2_rfo.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000020Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000014800Counts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystemCounts any data writes to uncacheable write combining (USWC) memory region  have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cacheCounts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000004800Counts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts any data writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.l2_miss.snoop_miss_or_no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200004800Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor moduleCounts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.streaming_stores.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000004800Counts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts any data writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000011000Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystemCounts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions hit the L2 cacheCounts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is requiredCounts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor moduleCounts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)offcore_response.sw_prefetch.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000001000Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)event=0xc3,period=20003,umask=0x4Floating point divide uops retired (Precise Event Capable) (Must be precise)event=0xc3,period=20003,umask=0x2Counts machine clears due to memory ordering issues.  This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the dataCycles the code-fetch stalls and an ITLB miss is outstandingRetired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable) (Must be precise)Reference cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counterInstructions retired (Fixed event) (Must be precise)Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this event (Must be precise)Instructions retired - using Reduced Skid PEBS feature (Must be precise)Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired (Must be precise)event=0xc3,period=20003event=0xc3,period=20003,umask=0x8machine_clears.page_faultevent=0xc3,period=20003,umask=0x20Machines clear due to a page faultCounts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violationevent=0xc3,period=20003,umask=0x1Integer divide uops retired (Precise Event Capable) (Must be precise)dtlb_load_misses.walk_completed_1gbevent=0x8,period=200003,umask=0x8Page walk completed due to a demand load to a 1GB pageCounts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages.  The page walks can end with or without a page faultevent=0x8,period=200003,umask=0x4Page walk completed due to a demand load to a 2M or 4M pageCounts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages.  The page walks can end with or without a page faultevent=0x8,period=200003,umask=0x2Page walk completed due to a demand load to a 4K pageCounts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages.  The page walks can end with or without a page faultdtlb_load_misses.walk_pendingevent=0x8,period=200003,umask=0x10Page walks outstanding due to a demand load every cycleCounts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walksdtlb_store_misses.walk_completed_1gbevent=0x49,period=2000003,umask=0x8Page walk completed due to a demand data store to a 1GB pageCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page faultevent=0x49,period=2000003,umask=0x4Page walk completed due to a demand data store to a 2M or 4M pageCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page faultevent=0x49,period=2000003,umask=0x2Page walk completed due to a demand data store to a 4K pageCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page faultdtlb_store_misses.walk_pendingevent=0x49,period=200003,umask=0x10Page walks outstanding due to a demand data store every cycleCounts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walksept.walk_pendingevent=0x4f,period=200003,umask=0x10Page walks outstanding due to walking the EPT every cycleCounts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation.  The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs).  Average cycles per walk can be calculated by dividing the count by number of walksitlb_misses.walk_completed_1gbevent=0x85,period=2000003,umask=0x8Page walk completed due to an instruction fetch in a 1GB pageCounts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages.  The page walks can end with or without a page faultevent=0x85,period=2000003,umask=0x4Page walk completed due to an instruction fetch in a 2M or 4M pageCounts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages.  The page walks can end with or without a page faultevent=0x85,period=2000003,umask=0x2Page walk completed due to an instruction fetch in a 4K pageCounts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page faultitlb_misses.walk_pendingevent=0x85,period=200003,umask=0x10Page walks outstanding due to an instruction fetch every cycleCounts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walkstlb_flushes.stlb_anyevent=0xbd,period=20003,umask=0x20STLB flushesCounts STLB flushes.  The TLBs are flushed on instructions like INVLPG and MOV to CR3This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cacheIncrements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrencesl1d_pend_miss.request_fb_fullevent=0x48,period=2000003,umask=0x2Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are eThis event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 missl2_lines_out.demand_dirtyevent=0xf2,period=100003,umask=0x6Dirty L2 cache lines evicted by demandCounts all L2 code requestsDemand Data Read requests  Spec update: HSD78, HSM80Counts any demand and L1 HW prefetch data load requests to L2  Spec update: HSD78, HSM80Demand requests that miss L2 cache  Spec update: HSD78, HSM80Demand requests to L2 cache  Spec update: HSD78, HSM80Counts all L2 HW prefetcher requestsCounts all L2 store RFO requestsNumber of instruction fetches that hit the L2 cacheNumber of instruction fetches that missed the L2 cacheDemand Data Read requests that hit L2 cache  Spec update: HSD78, HSM80Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache  Spec update: HSD78, HSM80Demand Data Read miss L2, no rejects  Spec update: HSD78, HSM80Demand data read requests that missed L2, no rejects  Spec update: HSD78, HSM80Counts all L2 HW prefetcher requests that hit L2Counts all L2 HW prefetcher requests that missed L2All requests that miss L2 cache  Spec update: HSD78, HSM80All requests that missed L2  Spec update: HSD78, HSM80All L2 requests  Spec update: HSD78, HSM80All requests to L2 cache  Spec update: HSD78, HSM80Counts the number of store RFO requests that hit the L2 cacheCounts the number of store RFO requests that miss the L2 cacheAny MLC or L3 HW prefetch accessing L2, including rejectsDemand data read requests that access L2 cacheCycles in which the L1D is lockedThis event counts each cache miss condition for references to the last level cacheThis event counts requests originating from the core that reference a cache line in the last level cacheRetired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops which data sources were HitM responses from shared L3  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise.  Spec update: HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops which data sources were hits in L3 without snoops required  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)event=0xd3,period=100003,umask=0x1Data from local DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event)This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM30 (Precise event)Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise.  Spec update: HSM30 (Precise event)Retired load uops with L1 cache hits as data sources  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops misses in L1 cache as data sources  Supports address when precise.  Spec update: HSM30 (Precise event)Retired load uops missed L1 cache as data sources  Supports address when precise.  Spec update: HSM30 (Precise event)Retired load uops with L2 cache hits as data sources  Supports address when precise.  Spec update: HSD76, HSD29, HSM30 (Precise event)Miss in mid-level (L2) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops missed L2. Unknown data source excluded  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops which data sources were data hits in L3 without snoops required  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops with L3 cache hits as data sources  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)event=0xd1,period=100003,umask=0x20Miss in last-level (L3) cache. Excludes Unknown data-source  Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)Retired load uops missed L3. Excludes unknown data source   Supports address when precise.  Spec update: HSD74, HSD29, HSD25, HSM26, HSM30 (Precise event)All retired load uops  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)All retired store uops  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)event=0xd0,period=100003,umask=0x21Retired load uops with locked access  Supports address when precise.  Spec update: HSD76, HSD29, HSM30 (Precise event)Retired load uops that split across a cacheline boundary  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired store uops that split across a cacheline boundary  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired load uops that miss the STLB  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Retired store uops that miss the STLB  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)Data read requests sent to uncore (demand and prefetch)Demand code read requests sent to uncoreDemand Data Read requests sent to uncore  Spec update: HSD78, HSM80Demand data read requests sent to uncore  Spec update: HSD78, HSM80Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoMOffcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61, HSM63Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61, HSM63Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61, HSM63Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore  Spec update: HSD78, HSD62, HSD61, HSM63, HSM80Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: HSD62, HSD61, HSM63Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle  Spec update: HSD62, HSD61, HSM63Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61, HSM63Offcore outstanding Demand Data Read transactions in uncore queue  Spec update: HSD78, HSD62, HSD61, HSM63, HSM80Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD78, HSD62, HSD61, HSM63, HSM80Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue  Spec update: HSD78, HSD62, HSD61, HSM63, HSM80Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore  Spec update: HSD62, HSD61, HSM63Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles  Spec update: HSD62, HSD61, HSM63offcore_response.all_code_rd.l3_hit.hit_other_core_no_fwdoffcore_response.all_data_rd.l3_hit.hitm_other_coreoffcore_response.all_data_rd.l3_hit.hit_other_core_no_fwdoffcore_response.all_reads.l3_hit.hitm_other_corehit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_reads.l3_hit.hit_other_core_no_fwdhit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_requests.l3_hit.any_responseoffcore_response.all_rfo.l3_hit.hitm_other_coreoffcore_response.all_rfo.l3_hit.hit_other_core_no_fwdoffcore_response.demand_code_rd.l3_hit.hitm_other_coreCounts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.demand_code_rd.l3_hit.hit_other_core_no_fwdCounts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_data_rd.l3_hit.hitm_other_coreCounts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.demand_data_rd.l3_hit.hit_other_core_no_fwdCounts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_rfo.l3_hit.hitm_other_coreoffcore_response.demand_rfo.l3_hit.hit_other_core_no_fwdCounts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_code_rd.l3_hit.any_responseCounts all prefetch (that bring data to LLC only) code reads hit in the L3offcore_response.pf_l2_data_rd.l3_hit.any_responseCounts prefetch (that bring data to L2) data reads hit in the L3offcore_response.pf_l2_rfo.l3_hit.any_responseCounts all prefetch (that bring data to L2) RFOs hit in the L3offcore_response.pf_l3_code_rd.l3_hit.any_responseoffcore_response.pf_l3_data_rd.l3_hit.any_responseCounts all prefetch (that bring data to LLC only) data reads hit in the L3offcore_response.pf_l3_rfo.l3_hit.any_responseavx_insts.allevent=0xc6,period=2000003,umask=0x7Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMXNote that a whole rep string only counts AVX_INST.ALL onceCycles with any input/output SSE* or FP assistsNumber of SIMD FP assists due to output valuesNumber of X87 FP assists due to input valuesNumber of X87 FP assists due to output valuesNumber of SIMD move elimination candidate uops that were eliminatedNumber of SIMD move elimination candidate uops that were not eliminatedNumber of transitions from AVX-256 to legacy SSE when penalty applicable  Spec update: HSD56, HSM57Number of transitions from SSE to AVX-256 when penalty applicable  Spec update: HSD56, HSM57Number of front end re-steers due to BPU mispredictionicache.ifetch_stallThis event counts Instruction Cache (ICACHE) missesCounts cycles DSB is delivered four uops. Set Cmask = 4Counts cycles DSB is delivered at least one uops. Set Cmask = 1Counts cycles MITE is delivered four uops. Set Cmask = 4Counts cycles MITE is delivered at least one uop. Set Cmask = 1Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cyclesInstruction Decode Queue (IDQ) empty cycles  Spec update: HSD135Counts cycles the IDQ is empty  Spec update: HSD135Number of uops delivered to IDQ from any pathIncrement each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cyclesThis event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performanceIncrement each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of deliveryIncrement each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cyclesThis event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performanceUops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled  Spec update: HSD135This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis  Spec update: HSD135Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled  Spec update: HSD135This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled.  This event is counted on a per-core basis  Spec update: HSD135Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE  Spec update: HSD135Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled  Spec update: HSD135Cycles with less than 2 uops delivered by the front end  Spec update: HSD135Cycles with less than 3 uops delivered by the front end  Spec update: HSD135hsw metrics( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\,cmask\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\,cmask\=1@)( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )Number of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise event)Number of times an HLE execution aborted due to incompatible memory type  Spec update: HSD65Number of times an HLE execution successfully committedNumber of times an HLE execution startedThis event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline.  Machine clears can have a significant performance impact if they are happening frequentlyRandomly selected loads with latency value being above 128  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 16  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 256  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise)event=0xcd,period=100003,umask=0x1,ldlat=0x20Randomly selected loads with latency value being above 32  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 4  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 512  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 64  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise)Randomly selected loads with latency value being above 8  Supports address when precise.  Spec update: HSD76, HSD25, HSM26 (Must be precise)Speculative cache-line split load uops dispatched to L1DSpeculative cache-line split store-address uops dispatched to L1Doffcore_response.all_code_rd.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00244offcore_response.all_code_rd.l3_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400244offcore_response.all_data_rd.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00091offcore_response.all_data_rd.l3_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400091offcore_response.all_reads.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC007F7miss in the L3offcore_response.all_reads.l3_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x01004007F7miss the L3 and the data is returned from local dramoffcore_response.all_requests.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC08FFFoffcore_response.all_rfo.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00122offcore_response.all_rfo.l3_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400122offcore_response.demand_code_rd.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00004Counts all demand code reads miss in the L3offcore_response.demand_code_rd.l3_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400004Counts all demand code reads miss the L3 and the data is returned from local dramoffcore_response.demand_data_rd.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00001Counts demand data reads miss in the L3offcore_response.demand_data_rd.l3_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400001Counts demand data reads miss the L3 and the data is returned from local dramoffcore_response.demand_rfo.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00002offcore_response.demand_rfo.l3_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0100400002Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dramoffcore_response.pf_l2_code_rd.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00040Counts all prefetch (that bring data to LLC only) code reads miss in the L3offcore_response.pf_l2_data_rd.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00010Counts prefetch (that bring data to L2) data reads miss in the L3offcore_response.pf_l2_rfo.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00020Counts all prefetch (that bring data to L2) RFOs miss in the L3offcore_response.pf_l3_code_rd.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00200offcore_response.pf_l3_data_rd.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00080Counts all prefetch (that bring data to LLC only) data reads miss in the L3offcore_response.pf_l3_rfo.l3_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00100Number of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise event)Number of times an RTM execution aborted due to incompatible memory type  Spec update: HSD65Number of times an RTM execution successfully committedNumber of times an RTM execution startedNumber of times a transactional abort was signaled due to a data capacity limitation for transactional writesNumber of times a transactional abort was signaled due to a data conflict on a transactionally accessed addressNumber of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision bufferNumber of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zeroNumber of times an HLE transactional execution aborted due to an unsupported read alignment from the elision bufferNumber of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision bufferNumber of times HLE lock could not be elided due to ElisionBufferAvailable being zeroevent=0x5c,cmask=1,edge=1,period=100003,umask=0x1Unhalted core cycles when the thread is not in ring 0Cycles in which the L1D and L2 are locked, due to a UC lock or split lockarith.divider_uopsevent=0x14,period=2000003,umask=0x2Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)Counts all near executed branches (not necessarily retired)Branch instructions at retirementAll (macro) branch instructions retired (Must be precise)Counts the number of conditional branch instructions retired (Precise event)event=0xc4,period=100003,umask=0x40Far branch instructions retiredNumber of far branches retiredevent=0xc4,period=100003,umask=0x2event=0xc4,period=100003,umask=0x8Counts the number of near return instructions retired (Precise event)Number of near taken branches retired (Precise event)Counts the number of not taken branch instructions retiredMispredicted branch instructions at retirementMispredicted macro branch instructions retired (Must be precise)This event counts all mispredicted branch instructions retired. This is a precise event (Must be precise)Number of near branch instructions retired that were taken but mispredicted (Precise event)Increments at the frequency of XCLK (100 MHz) when not haltedThis event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt stateReference cycles when the thread is unhalted. (counts at 100 MHz rate)This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttlingCounts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttlingCycles with pending L1 cache miss loadsCycles with pending L1 data cache miss loads. Set Cmask=8 to count cycleCycles with pending L2 cache miss loads  Spec update: HSD78, HSM63, HSM80Cycles with pending L2 miss loads. Set Cmask=2 to count cycle  Spec update: HSD78, HSM63, HSM80Cycles with pending memory loadsCycles with pending memory loads. Set Cmask=2 to count cycleThis event counts cycles during which no instructions were executed in the execution stage of the pipelineExecution stalls due to L1 data cache missesExecution stalls due to L1 data cache miss loads. Set Cmask=0CHExecution stalls due to L2 cache misses  Spec update: HSM63, HSM80Number of loads missed L2  Spec update: HSM63, HSM80Execution stalls due to memory subsystemThis event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data)ild_stall.iq_fullevent=0x87,period=2000003,umask=0x4Stall cycles because IQ is fullStall cycles due to IQ is fullThis event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP)Instructions retired from execution  Spec update: HSD140, HSD143This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions  Spec update: HSD140, HSD143Number of instructions retired. General Counter   - architectural event  Spec update: HSD11, HSD140Number of instructions at retirement  Spec update: HSD11, HSD140Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: HSD140 (Must be precise)FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handlingThis is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handlingThis event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etcThe number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useloads blocked by overlapping with store buffer that cannot be forwardedThis event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issuedFalse dependencies in MOB due to partial compare on addressAliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impactNon-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetchNon-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetchNumber of uops delivered by the LSDThis event is incremented when self-modifying code (SMC) is detected, which causes a machine clear.  Machine clears can have a significant performance impact if they are happening frequentlyNumber of integer move elimination candidate uops that were eliminatedNumber of integer move elimination candidate uops that were not eliminatedNumber of microcode assists invoked by HW upon uop writebackResource-related stall cycles  Spec update: HSD135Cycles allocation is stalled due to resource related reason  Spec update: HSD135This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were availableCount cases of saving new LBR records by hardwareThis event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-endNumber of uops executed on the core  Spec update: HSD30, HSM31Counts total number of uops to be executed per-core each cycle  Spec update: HSD30, HSM31Cycles at least 1 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles at least 2 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles at least 3 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles at least 4 micro-op is executed from any thread on physical core  Spec update: HSD30, HSM31Cycles with no micro-ops executed from any thread on physical core  Spec update: HSD30, HSM31Cycles where at least 1 uop was executed per-thread  Spec update: HSD144, HSD30, HSM31This events counts the cycles where at least one uop was executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31Cycles where at least 2 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31This events counts the cycles where at least two uop were executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31Cycles where at least 3 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31This events counts the cycles where at least three uop were executed. It is counted per thread  Spec update: HSD144, HSD30, HSM31Cycles where at least 4 uops were executed per-thread  Spec update: HSD144, HSD30, HSM31Counts number of cycles no uops were dispatched to be executed on this thread  Spec update: HSD144, HSD30, HSM31Cycles which a uop is dispatched on port 0 in this threadCycles per core when uops are executed in port 0Cycles which a uop is dispatched on port 1 in this threadCycles per core when uops are executed in port 1Cycles which a uop is dispatched on port 2 in this threadCycles which a uop is dispatched on port 3 in this threadCycles which a uop is dispatched on port 4 in this threadCycles per core when uops are executed in port 4Cycles which a uop is dispatched on port 5 in this threadCycles per core when uops are executed in port 5Cycles which a uop is dispatched on port 6 in this threadCycles per core when uops are executed in port 6Cycles which a uop is dispatched on port 7 in this threadThis event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uopsuops_issued.core_stall_cyclesevent=0xe,any=1,cmask=1,inv=1,period=2000003,umask=0x1Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threadsNumber of flags-merge uops allocated. Such uops add delayNumber of multiply packed/scalar single precision uops allocatedNumber of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or notCounts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles (Precise event)uops_retired.core_stall_cyclesevent=0xc2,any=1,cmask=1,inv=1,period=2000003,umask=0x1This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle (Precise event)unc_cbo_cache_lookup.extsnp_esevent=0x34,umask=0x46L3 Lookup external snoop request that access cache and found line in E or S-state. Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in E or S-stateunc_cbo_cache_lookup.extsnp_ievent=0x34,umask=0x48L3 Lookup external snoop request that access cache and found line in I-state. Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in I-stateunc_cbo_cache_lookup.extsnp_mevent=0x34,umask=0x41L3 Lookup external snoop request that access cache and found line in M-state. Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in M-stateunc_cbo_cache_lookup.extsnp_mesievent=0x34,umask=0x4fL3 Lookup external snoop request that access cache and found line in MESI-state. Unit: uncore_cbox L3 Lookup external snoop request that access cache and found line in MESI-stateunc_cbo_cache_lookup.write_ievent=0x34,umask=0x28L3 Lookup write request that access cache and found line in I-state. Unit: uncore_cbox L3 Lookup write request that access cache and found line in I-stateunc_cbo_xsnp_response.hitm_evictionevent=0x22,umask=0x88A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core. Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor coreunc_cbo_xsnp_response.hitm_externalevent=0x22,umask=0x28An external snoop hits a modified line in some processor core. Unit: uncore_cbox An external snoop hits a modified line in some processor coreunc_cbo_xsnp_response.hit_evictionevent=0x22,umask=0x84A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core. Unit: uncore_cbox A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor coreunc_cbo_xsnp_response.hit_externalevent=0x22,umask=0x24An external snoop hits a non-modified line in some processor core. Unit: uncore_cbox An external snoop hits a non-modified line in some processor coreunc_cbo_xsnp_response.miss_externalevent=0x22,umask=0x21An external snoop misses in some processor core. Unit: uncore_cbox An external snoop misses in some processor coreunc_arb_coh_trk_occupancy.allevent=0x83,umask=0x01Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory). Unit: uncore_arb uncore otherEach cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC. Unit: uncore_arb event=0xffLoad misses in all DTLB levels that cause page walksMisses in all TLB levels that cause a page walk of any page sizedtlb_load_misses.pde_cache_missevent=0x8,period=100003,umask=0x80DTLB demand load misses with low part of linear-to-physical address translation missedNumber of cache load STLB hits. No page walkThis event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walksThis event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walksDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page sizeCompleted page walks in any TLB of any page size due to demand load missesLoad miss in all TLB levels causes a page walk that completes. (1G)Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M)Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levelsDemand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K)Completed page walks due to demand load misses that caused 4K page walks in any TLB levelsCycles when PMH is busy with page walksThis event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load missesStore misses in all DTLB levels that cause page walksMiss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G)dtlb_store_misses.pde_cache_missevent=0x49,period=100003,umask=0x80DTLB store misses with low part of linear-to-physical address translation missedThis event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walksThis event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walksStore misses in all DTLB levels that cause completed page walksCompleted page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G)Store misses in all DTLB levels that cause completed page walks. (1G)Store misses in all DTLB levels that cause completed page walks (2M/4M)Completed page walks due to store misses in one or more TLB levels of 2M/4M page structureStore miss in all TLB levels causes a page walk that completes. (4K)Completed page walks due to store misses in one or more TLB levels of 4K page structureThis event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store missesevent=0xae,period=100003,umask=0x1Counts the number of ITLB flushes, includes 4k/2M/4M pagesMisses at all ITLB levels that cause page walksMisses in ITLB that causes a page walk of any page sizeITLB misses that hit STLB. No page walkITLB misses that hit STLB (2M)ITLB misses that hit STLB (4K)Misses in all ITLB levels that cause completed page walksCompleted page walks in ITLB of any page sizeStore miss in all TLB levels causes a page walk that completes. (1G)Code miss in all TLB levels causes a page walk that completes. (2M/4M)Completed page walks due to misses in ITLB 2M/4M page entriesCode miss in all TLB levels causes a page walk that completes. (4K)Completed page walks due to misses in ITLB 4K page entriesThis event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB missesNumber of DTLB page walker hits in the L1+FBNumber of DTLB page walker loads that hit in the L1+FBNumber of DTLB page walker hits in the L2Number of DTLB page walker loads that hit in the L2Number of DTLB page walker hits in the L3 + XSNP  Spec update: HSD25Number of DTLB page walker loads that hit in the L3  Spec update: HSD25Number of DTLB page walker hits in Memory  Spec update: HSD25Number of DTLB page walker loads from memory  Spec update: HSD25page_walker_loads.ept_dtlb_l1event=0xbc,period=2000003,umask=0x41Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FBpage_walker_loads.ept_dtlb_l2event=0xbc,period=2000003,umask=0x42Counts the number of Extended Page Table walks from the DTLB that hit in the L2page_walker_loads.ept_dtlb_l3event=0xbc,period=2000003,umask=0x44Counts the number of Extended Page Table walks from the DTLB that hit in the L3page_walker_loads.ept_dtlb_memoryevent=0xbc,period=2000003,umask=0x48Counts the number of Extended Page Table walks from the DTLB that hit in memorypage_walker_loads.ept_itlb_l1event=0xbc,period=2000003,umask=0x81Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FBpage_walker_loads.ept_itlb_l2event=0xbc,period=2000003,umask=0x82Counts the number of Extended Page Table walks from the ITLB that hit in the L2page_walker_loads.ept_itlb_l3event=0xbc,period=2000003,umask=0x84page_walker_loads.ept_itlb_memoryevent=0xbc,period=2000003,umask=0x88Counts the number of Extended Page Table walks from the ITLB that hit in memoryNumber of ITLB page walker hits in the L1+FBNumber of ITLB page walker loads that hit in the L1+FBNumber of ITLB page walker hits in the L2Number of ITLB page walker loads that hit in the L2Number of ITLB page walker hits in the L3 + XSNP  Spec update: HSD25Number of ITLB page walker loads that hit in the L3  Spec update: HSD25page_walker_loads.itlb_memoryevent=0xbc,period=2000003,umask=0x28Number of ITLB page walker hits in Memory  Spec update: HSD25Number of ITLB page walker loads from memory  Spec update: HSD25event=0xbd,period=100003,umask=0x1event=0xbd,period=100003,umask=0x20Count number of STLB flush attemptsevent=0xd3,period=100003,umask=0x4Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)  Supports address when precise.  Spec update: HSD29, HSM30 (Precise event)event=0xd3,period=100003,umask=0x20Retired load uop whose Data Source was: forwarded from remote cache  Supports address when precise.  Spec update: HSM30 (Precise event)event=0xd3,period=100003,umask=0x10Retired load uop whose Data Source was: Remote cache HITM  Supports address when precise.  Spec update: HSM30 (Precise event)offcore_response.demand_code_rd.llc_hit.hitm_other_coreoffcore_response.demand_code_rd.llc_hit.hit_other_core_no_fwdoffcore_response.demand_data_rd.llc_hit.hitm_other_coreoffcore_response.demand_data_rd.llc_hit.hit_other_core_no_fwdoffcore_response.demand_rfo.llc_hit.hit_other_core_no_fwdoffcore_response.pf_l2_code_rd.llc_hit.any_responseoffcore_response.pf_l2_data_rd.llc_hit.any_responseoffcore_response.pf_l2_rfo.llc_hit.any_responseoffcore_response.pf_llc_data_rd.llc_hit.any_responsehsx metricsevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400244event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400091event=0xb7,period=100003,umask=0x1,offcore_rsp=0x063F800091event=0xb7,period=100003,umask=0x1,offcore_rsp=0x083FC00091event=0xb7,period=100003,umask=0x1,offcore_rsp=0x06004007F7Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x063F8007F7event=0xb7,period=100003,umask=0x1,offcore_rsp=0x083FC007F7event=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400122offcore_response.demand_code_rd.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00004offcore_response.demand_code_rd.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400004offcore_response.demand_data_rd.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001offcore_response.demand_data_rd.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400001offcore_response.demand_rfo.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x0600400002offcore_response.pf_l2_code_rd.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00040offcore_response.pf_l2_data_rd.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00010offcore_response.pf_l2_rfo.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00020offcore_response.pf_llc_data_rd.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00080Counts the number of lines brought into the L1 data cachel2_l1d_wb_rqsts.allevent=0x28,period=200003,umask=0xfNot rejected writebacks from L1D to L2 cache lines in any statel2_l1d_wb_rqsts.hit_eevent=0x28,period=200003,umask=0x4Not rejected writebacks from L1D to L2 cache lines in E statel2_l1d_wb_rqsts.hit_mevent=0x28,period=200003,umask=0x8Not rejected writebacks from L1D to L2 cache lines in M statel2_l1d_wb_rqsts.missevent=0x28,period=200003,umask=0x1Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)Not rejected writebacks that missed LLCevent=0xf2,period=100003,umask=0x1event=0xf2,period=100003,umask=0x2l2_lines_out.dirty_allevent=0xf2,period=100003,umask=0xaDirty L2 cache lines filling the L2l2_lines_out.pf_cleanevent=0xf2,period=100003,umask=0x4Clean L2 cache lines evicted by L2 prefetchClean L2 cache lines evicted by the MLC prefetcherl2_lines_out.pf_dirtyevent=0xf2,period=100003,umask=0x8Dirty L2 cache lines evicted by L2 prefetchDirty L2 cache lines evicted by the MLC prefetcherevent=0x24,period=200003,umask=0x3Counts any demand and L1 HW prefetch data load requests to L2event=0x24,period=200003,umask=0xc0event=0x24,period=200003,umask=0xcevent=0x24,period=200003,umask=0x10event=0x24,period=200003,umask=0x20event=0x24,period=200003,umask=0x1l2_rqsts.pf_hitevent=0x24,period=200003,umask=0x40Requests from the L2 hardware prefetchers that hit L2 cachel2_rqsts.pf_missevent=0x24,period=200003,umask=0x80Requests from the L2 hardware prefetchers that miss L2 cacheevent=0x24,period=200003,umask=0x4event=0x24,period=200003,umask=0x8l2_store_lock_rqsts.allevent=0x27,period=200003,umask=0xfRFOs that access cache lines in any statel2_store_lock_rqsts.hit_mevent=0x27,period=200003,umask=0x8RFOs that hit cache lines in M statel2_store_lock_rqsts.missevent=0x27,period=200003,umask=0x1RFOs that miss cache linesL2 or LLC HW prefetches that access L2 cacheAny MLC or LLC HW prefetch accessing L2, including rejectsCore-originated cacheable demand requests missed LLCCore-originated cacheable demand requests that refer to LLCmem_load_uops_llc_hit_retired.xsnp_hitRetired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache (Precise event)mem_load_uops_llc_hit_retired.xsnp_hitmRetired load uops which data sources were HitM responses from shared LLC (Precise event)mem_load_uops_llc_hit_retired.xsnp_missRetired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache (Precise event)mem_load_uops_llc_hit_retired.xsnp_noneRetired load uops which data sources were hits in LLC without snoops required (Precise event)mem_load_uops_llc_miss_retired.local_dramRetired load uops which data sources missed LLC but serviced from local dramRetired load uops whose data source was local memory (cross-socket snoop not needed or missed)Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready (Precise event)Retired load uops with L1 cache hits as data sources (Precise event)Retired load uops which data sources following L1 data-cache miss (Precise event)Retired load uops with L2 cache hits as data sources (Precise event)Retired load uops with L2 cache misses as data sources (Precise event)mem_load_uops_retired.llc_hitRetired load uops which data sources were data hits in LLC without snoops required (Precise event)mem_load_uops_retired.llc_missMiss in last-level (L3) cache. Excludes Unknown data-source (Precise event)All retired load uops. (Precise Event)All retired store uops. (Precise Event)Retired load uops with locked access. (Precise Event)Retired load uops that split across a cacheline boundary. (Precise Event)Retired store uops that split across a cacheline boundary. (Precise Event)Retired load uops that miss the STLB. (Precise Event)Retired store uops that miss the STLB. (Precise Event)Demand data read requests sent to uncoreCases when offcore requests buffer cannot take more entries for coreOffcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncoreOffcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cyclesCycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncoreoffcore_requests_outstanding.cycles_with_demand_code_rdevent=0x60,cmask=1,period=2000003,umask=0x2Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycleCycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncoreOffcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycleOffcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cyclesOffcore outstanding Demand Data Read transactions in uncore queueOffcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cyclesCycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queueOffcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncoreOffcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cyclesoffcore_response.all_code_rd.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0244Counts all demand & prefetch code reads that hit in the LLCoffcore_response.all_code_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0244Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x000105B3offcore_response.all_data_rd.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0091Counts all demand & prefetch data reads that hit in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0091Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0091Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_data_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0091Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_reads.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x000107F7Counts all data/code/rfo references (demand & prefetch)event=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010122Counts all demand & prefetch prefetch RFOsoffcore_response.all_rfo.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0122Counts all demand & prefetch RFOs that hit in the LLCoffcore_response.all_rfo.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0122Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10008Counts all writebacks from the core to the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010004offcore_response.demand_code_rd.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0004Counts all demand code reads that hit in the LLCoffcore_response.demand_code_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0004Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010001Counts all demand data readsoffcore_response.demand_data_rd.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0001Counts all demand data reads that hit in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0001Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0001Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_data_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0001Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x00010002Counts all demand rfo'sevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0002Counts all demand data writes (RFOs) that hit in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0002Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.demand_rfo.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0002Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x18000Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core cachesoffcore_response.split_lock_uc_lock.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10400Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable addressevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10800Counts non-temporal storesfp_comp_ops_exe.sse_packed_doubleevent=0x10,period=2000003,umask=0x10Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cyclefp_comp_ops_exe.sse_packed_singleevent=0x10,period=2000003,umask=0x40Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cyclefp_comp_ops_exe.sse_scalar_doubleevent=0x10,period=2000003,umask=0x80Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycleCounts number of SSE* or AVX-128 double precision FP scalar uops executedfp_comp_ops_exe.sse_scalar_singleevent=0x10,period=2000003,umask=0x20Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cyclefp_comp_ops_exe.x87event=0x10,period=2000003,umask=0x1Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a sCounts number of X87 uops executedother_assists.avx_storeNumber of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operationsNumber of assists associated with 256-bit AVX store operationsNumber of transitions from AVX-256 to legacy SSE when penalty applicableevent=0xc1,period=100003,umask=0x20Number of transitions from SSE to AVX-256 when penalty applicablesimd_fp_256.packed_doubleevent=0x11,period=2000003,umask=0x2number of AVX-256 Computational FP double precision uops issued this cycleCounts 256-bit packed double-precision floating-point instructionssimd_fp_256.packed_singleevent=0x11,period=2000003,umask=0x1number of GSSE-256 Computational FP single precision uops issued this cycleCounts 256-bit packed single-precision floating-point instructionsdsb2mite_switches.countevent=0xab,period=2000003,umask=0x1Decode Stream Buffer (DSB)-to-MITE switchesNumber of DSB to MITE switchesCycles DSB to MITE switches caused delaydsb_fill.exceed_dsb_linesevent=0xac,period=2000003,umask=0x8Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) linesDSB Fill encountered > 3 DSB linesCycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB missInstruction cache, streaming buffer and victim cache missesNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accessesCounts cycles MITE is delivered at least one uops. Set Cmask = 1Counts cycles the IDQ is emptyIncrement each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cyclesCount issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stallivb metrics( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )1 / ( ((FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD) + ((FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD) )1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_timeLoads with latency value being above 128 (Must be precise)Loads with latency value being above 16 (Must be precise)Loads with latency value being above 256 (Must be precise)Loads with latency value being above 32 (Must be precise)Loads with latency value being above 4 (Must be precise)Loads with latency value being above 512 (Must be precise)Loads with latency value being above 64 (Must be precise)Loads with latency value being above 8 (Must be precise)mem_trans_retired.precise_storeevent=0xcd,period=2000003,umask=0x2Sample stores and collect precise store operation via PEBS record. PMC3 only (Must be precise)Speculative cache-line split Store-address uops dispatched to L1Doffcore_response.all_code_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400244Counts all demand & prefetch code reads that miss the LLC  and the data returned from dramoffcore_response.all_data_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400091Counts all demand & prefetch data reads that miss the LLC  and the data returned from dramoffcore_response.all_reads.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3004003f7Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dramoffcore_response.data_in_socket.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x6004001b3Counts LLC replacementsoffcore_response.demand_code_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400004Counts demand code reads that miss the LLC and the data returned from dramoffcore_response.demand_data_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400001Counts demand data reads that miss the LLC and the data returned from drampage_walks.llc_missevent=0xbe,period=100003,umask=0x1Number of any page walk that had a miss in LLCarith.fpu_divevent=0x14,cmask=1,edge=1,period=100003,umask=0x4Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of dividesCount XClk pulses when this thread is unhalted and the other is haltedReference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)Cycles with pending L1 cache miss loads. Set AnyThread to count per coreCycles while L2 cache miss load* is outstandingCycles with pending L2 cache miss loadsCycles with pending L2 miss loads. Set AnyThread to count per coreCycles with pending memory loads. Set AnyThread to count per coreExecution stalls while L2 cache miss load* is outstandingExecution stalls due to L2 cache missesNumber of loads missed L2Number of instructions retired. General Counter   - architectural eventNumber of instructions at retirementPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Must be precise)Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)int_misc.recovery_stalls_countevent=0xd,cmask=1,edge=1,period=2000003,umask=0x3Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)Loads blocked by overlapping with store buffer that cannot be forwardedCounts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0Number of self-modifying-code machine clears detectedevent=0xc1,period=100003,umask=0x80Cycles Allocation is stalled due to Resource Related reasonCycles stalled due to no store buffers available (not including draining form sync)Cycles the RS is empty for the threadCycles per thread when uops are dispatched to port 0Cycles which a Uop is dispatched on port 0uops_dispatched_port.port_0_coreCycles per core when uops are dispatched to port 0Cycles per thread when uops are dispatched to port 1Cycles which a Uop is dispatched on port 1uops_dispatched_port.port_1_coreCycles per core when uops are dispatched to port 1event=0xa1,period=2000003,umask=0xcCycles per thread when load or STA uops are dispatched to port 2Cycles which a Uop is dispatched on port 2uops_dispatched_port.port_2_coreevent=0xa1,any=1,period=2000003,umask=0xcUops dispatched to port 2, loads and stores per core (speculative and retired)event=0xa1,period=2000003,umask=0x30Cycles per thread when load or STA uops are dispatched to port 3Cycles which a Uop is dispatched on port 3uops_dispatched_port.port_3_coreevent=0xa1,any=1,period=2000003,umask=0x30Cycles per core when load or STA uops are dispatched to port 3Cycles per thread when uops are dispatched to port 4Cycles which a Uop is dispatched on port 4uops_dispatched_port.port_4_coreCycles per core when uops are dispatched to port 4Cycles per thread when uops are dispatched to port 5Cycles which a Uop is dispatched on port 5uops_dispatched_port.port_5_coreCycles per core when uops are dispatched to port 5Counts total number of uops to be executed per-core each cycleCounts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cyclesIncrements each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this coreNumber of flags-merge uops being allocatedNumber of flags-merge uops allocated. Such uops adds delayNumber of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or notRetired uops (Precise event)Cycles weighted by number of requests pending in Coherency Tracker. Unit: uncore_arb Cycles weighted by number of requests pending in Coherency TrackerNumber of requests allocated in Coherency Tracker. Unit: uncore_arb Number of requests allocated in Coherency TrackerCounts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC. Unit: uncore_arb Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLCunc_arb_trk_occupancy.cycles_over_half_fullevent=0x80,cmask=10,umask=0x01Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC. Unit: uncore_arb Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLCCounts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC. Unit: uncore_arb Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLCunc_arb_trk_requests.evictionsevent=0x81,umask=0x80Counts the number of LLC evictions allocated. Unit: uncore_arb Counts the number of LLC evictions allocatedCounts the number of allocated write entries, include full, partial, and LLC evictions. Unit: uncore_arb Counts the number of allocated write entries, include full, partial, and LLC evictionsThis 48-bit fixed counter counts the UCLK cycles. Unit: uncore_arb unc_cbo_xsnp_response.missevent=0x22,umask=0x01A snoop misses in some processor core. Unit: uncore_cbox A snoop misses in some processor coreunc_cbo_xsnp_response.invalevent=0x22,umask=0x02A snoop invalidates a non-modified line in some processor core. Unit: uncore_cbox A snoop invalidates a non-modified line in some processor coreunc_cbo_xsnp_response.hitevent=0x22,umask=0x04A snoop hits a non-modified line in some processor core. Unit: uncore_cbox A snoop hits a non-modified line in some processor coreunc_cbo_xsnp_response.hitmevent=0x22,umask=0x08A snoop hits a modified line in some processor core. Unit: uncore_cbox A snoop hits a modified line in some processor coreunc_cbo_xsnp_response.inval_mevent=0x22,umask=0x10A snoop invalidates a modified line in some processor core. Unit: uncore_cbox A snoop invalidates a modified line in some processor coreunc_cbo_xsnp_response.external_filterevent=0x22,umask=0x20Filter on cross-core snoops initiated by this Cbox due to external snoop request. Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to external snoop requestunc_cbo_xsnp_response.xcore_filterevent=0x22,umask=0x40Filter on cross-core snoops initiated by this Cbox due to processor core memory request. Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to processor core memory requestunc_cbo_xsnp_response.eviction_filterevent=0x22,umask=0x80Filter on cross-core snoops initiated by this Cbox due to LLC eviction. Unit: uncore_cbox Filter on cross-core snoops initiated by this Cbox due to LLC evictionunc_cbo_cache_lookup.mevent=0x34,umask=0x01LLC lookup request that access cache and found line in M-state. Unit: uncore_cbox LLC lookup request that access cache and found line in M-stateunc_cbo_cache_lookup.eevent=0x34,umask=0x02LLC lookup request that access cache and found line in E-state. Unit: uncore_cbox LLC lookup request that access cache and found line in E-stateunc_cbo_cache_lookup.sevent=0x34,umask=0x04LLC lookup request that access cache and found line in S-state. Unit: uncore_cbox LLC lookup request that access cache and found line in S-stateunc_cbo_cache_lookup.ievent=0x34,umask=0x08LLC lookup request that access cache and found line in I-state. Unit: uncore_cbox LLC lookup request that access cache and found line in I-stateunc_cbo_cache_lookup.read_filterevent=0x34,umask=0x10Filter on processor core initiated cacheable read requests. Unit: uncore_cbox Filter on processor core initiated cacheable read requestsunc_cbo_cache_lookup.write_filterevent=0x34,umask=0x20Filter on processor core initiated cacheable write requests. Unit: uncore_cbox Filter on processor core initiated cacheable write requestsunc_cbo_cache_lookup.extsnp_filterevent=0x34,umask=0x40Filter on external snoop requests. Unit: uncore_cbox Filter on external snoop requestsunc_cbo_cache_lookup.any_request_filterevent=0x34,umask=0x80Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests. Unit: uncore_cbox Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requestsunc_cbo_cache_lookup.esevent=0x34,umask=0x06LLC lookup request that access cache and found line in E-state or S-state. Unit: uncore_cbox LLC lookup request that access cache and found line in E-state or S-statedtlb_load_misses.large_page_walk_completedevent=0x8,period=100003,umask=0x88Page walk for a large page completed for Demand loadevent=0x8,period=100003,umask=0x81Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page sizeMisses in all TLB levels that cause a page walk of any page size from demand loadsevent=0x5f,period=100003,umask=0x4Counts load operations that missed 1st level DTLB but hit the 2nd levelevent=0x8,period=100003,umask=0x82Misses in all TLB levels that caused page walk completed of any size by demand loadsevent=0x8,period=2000003,umask=0x84Demand load cycles page miss handler (PMH) is busy with this walkCycle PMH is busy with a walk due to demand loadsMiss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G)Cycles PMH is busy with this walkCycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesitlb_misses.large_page_walk_completedevent=0x85,period=100003,umask=0x80Completed page walks in ITLB due to STLB load misses for large pagesMisses in all ITLB levels that cause page walksCycle PMH is busy with a walkevent=0xd3,period=100007,umask=0x3Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded)mem_load_uops_llc_miss_retired.remote_dramevent=0xd3,period=100007,umask=0xcRetired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded)mem_load_uops_llc_miss_retired.remote_fwdData forwarded from remote cachemem_load_uops_llc_miss_retired.remote_hitmRemote cache HITMoffcore_response.all_data_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0091Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean responseoffcore_response.all_pf_data_rd.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0090Counts all prefetch data reads that hit the LLCoffcore_response.all_pf_data_rd.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0090Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_pf_data_rd.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0090Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_pf_data_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0090Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_pf_data_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0090Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean responseoffcore_response.all_reads.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_reads.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_reads.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c03f7Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean responseoffcore_response.demand_data_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0001Counts demand data reads that hit in the LLC and sibling core snoop returned a clean responseoffcore_response.other.lru_hintsevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803c8000Counts L2 hints sent to LLC to keep a line from being evicted out of the core cachesoffcore_response.other.portio_mmio_ucevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23ffc08000Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accessesevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0040Counts all prefetch (that bring data to L2) code reads that hit in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0010Counts prefetch (that bring data to L2) data reads that hit in the LLCoffcore_response.pf_l2_data_rd.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0010Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l2_data_rd.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0010Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_data_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0010Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l2_data_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0010Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0200Counts all prefetch (that bring data to LLC only) code reads that hit in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLCoffcore_response.pf_llc_data_rd.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_llc_data_rd.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_llc_data_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_llc_data_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0080Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean responseivt metricsevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc00244Counts all demand & prefetch code reads that miss the LLCoffcore_response.all_code_rd.llc_miss.remote_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800244Counts all demand & prefetch code reads that miss the LLC  and the data returned from remote dramoffcore_response.all_code_rd.llc_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f800244Counts all demand & prefetch code reads that miss the LLC  and the data forwarded from remote cacheevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20091Counts all demand & prefetch data reads that hits the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc203f7Counts all data/code/rfo reads (demand & prefetch) that hit the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x6004003f7Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from local dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc003f7Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  the data is found in M state in remote cache and forwarded from thereevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f8203f7Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data forwarded from remote cacheevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20004Counts all demand code reads that miss the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400004Counts all demand code reads that miss the LLC  and the data returned from local dramoffcore_response.demand_code_rd.llc_miss.remote_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800004Counts all demand code reads that miss the LLC  and the data returned from remote dramoffcore_response.demand_code_rd.llc_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc00004Counts all demand code reads that miss the LLC  the data is found in M state in remote cache and forwarded from thereoffcore_response.demand_code_rd.llc_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f820004Counts all demand code reads that miss the LLC  and the data forwarded from remote cacheoffcore_response.demand_data_rd.llc_miss.any_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x67fc00001Counts demand data reads that miss the LLC  and the data returned from remote & local dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20001Counts demand data reads that miss in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400001Counts demand data reads that miss the LLC  and the data returned from local dramoffcore_response.demand_data_rd.llc_miss.remote_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800001Counts demand data reads that miss the LLC  and the data returned from remote dramoffcore_response.demand_data_rd.llc_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc00001Counts demand data reads that miss the LLC  the data is found in M state in remote cache and forwarded from thereoffcore_response.demand_data_rd.llc_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f820001Counts demand data reads that miss the LLC  and the data forwarded from remote cacheevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc20002Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from thereevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20040Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from remote & local dramoffcore_response.pf_l2_data_rd.llc_miss.any_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x67fc00010Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from remote & local dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20010Counts prefetch (that bring data to L2) data reads that miss in the LLCoffcore_response.pf_l2_data_rd.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400010Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data returned from local dramoffcore_response.pf_l2_data_rd.llc_miss.remote_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x67f800010Counts prefetch (that bring data to L2) data reads  that miss the LLC  and the data returned from remote dramoffcore_response.pf_l2_data_rd.llc_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x107fc00010Counts prefetch (that bring data to L2) data reads that miss the LLC  the data is found in M state in remote cache and forwarded from thereoffcore_response.pf_l2_data_rd.llc_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x87f820010Counts prefetch (that bring data to L2) data reads that miss the LLC  and the data forwarded from remote cacheevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20200Counts all prefetch (that bring data to LLC only) code reads that miss in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3fffc20080Counts prefetch (that bring data to LLC only) data reads that miss in the LLCNumber of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode.demand. Unit: uncore_cbox LLC misses - Uncacheable reads. Derived from unc_c_tor_inserts.miss_opcode.uncacheable. Unit: uncore_cbox LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode.rfo_prefetch. Unit: uncore_cbox LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode.code. Unit: uncore_cbox LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode.data_read. Unit: uncore_cbox event=0x35,umask=0x3,filter_opc=0x19cPCIe allocating writes that miss LLC - DDIO misses. Derived from unc_c_tor_inserts.miss_opcode.ddio_miss. Unit: uncore_cbox LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox llc_misses.itom_writeLLC misses for ItoM writes (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.miss_opcode.itom_write. Unit: uncore_cbox llc_misses.pcie_non_snoop_readevent=0x35,umask=0x3,filter_opc=0x1e4LLC misses for PCIe non-snoop reads. Derived from unc_c_tor_inserts.miss_opcode.pcie_read. Unit: uncore_cbox event=0x35,umask=0x3,filter_opc=0x1e6LLC misses for PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.miss_opcode.pcie_write. Unit: uncore_cbox Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode.streaming_full. Unit: uncore_cbox Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode.streaming_partial. Unit: uncore_cbox llc_references.pcie_partial_readevent=0x35,umask=0x1,filter_opc=0x195Partial PCIe reads. Derived from unc_c_tor_inserts.opcode.pcie_partial. Unit: uncore_cbox event=0x35,umask=0x1,filter_opc=0x19cPCIe allocating writes that hit in LLC (DDIO hits). Derived from unc_c_tor_inserts.opcode.ddio_hit. Unit: uncore_cbox PCIe read current. Derived from unc_c_tor_inserts.opcode.pcie_read_current. Unit: uncore_cbox llc_references.itom_writeevent=0x35,umask=0x1,filter_opc=0x1c8ItoM write hits (as part of fast string memcpy stores). Derived from unc_c_tor_inserts.opcode.itom_write_hit. Unit: uncore_cbox llc_references.pcie_ns_readevent=0x35,umask=0x1,filter_opc=0x1e4PCIe non-snoop reads. Derived from unc_c_tor_inserts.opcode.pcie_read. Unit: uncore_cbox event=0x35,umask=0x1,filter_opc=0x1e5PCIe non-snoop writes (partial). Derived from unc_c_tor_inserts.opcode.pcie_partial_write. Unit: uncore_cbox llc_references.pcie_ns_writeevent=0x35,umask=0x1,filter_opc=0x1e6PCIe non-snoop writes (full line). Derived from unc_c_tor_inserts.opcode.pcie_full_write. Unit: uncore_cbox unc_c_tor_occupancy.miss_localevent=0x36,umask=0x2AOccupancy for all LLC misses that are addressed to local memory. Unit: uncore_cbox Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode.llc_data_read. Unit: uncore_cbox unc_c_tor_occupancy.miss_remoteevent=0x36,umask=0x8AOccupancy for all LLC misses that are addressed to remote memory. Unit: uncore_cbox Read requests to home agent. Unit: uncore_ha Write requests to home agent. Unit: uncore_ha QPI clock ticks. Use to get percentages for QPI cycles events. Unit: uncore_qpi unc_q_rxl0p_power_cyclesevent=0x10Cycles where receiving QPI link is in half-width mode. Unit: uncore_qpi (UNC_Q_RxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100.rxl0p_power_cycles %unc_q_txl0p_power_cyclesevent=0xdCycles where transmitting QPI link is in half-width mode. Unit: uncore_qpi (UNC_Q_TxL0P_POWER_CYCLES / UNC_Q_CLOCKTICKS) * 100.txl0p_power_cycles %unc_q_txl_flits_g0.dataNumber of data flits transmitted . Unit: uncore_qpi unc_q_txl_flits_g0.non_dataNumber of non data (control) flits transmitted . Unit: uncore_qpi unc_m_act_count.rdMemory page activates for reads and writes. Unit: uncore_imc Read requests to memory controller. Derived from unc_m_cas_count.rd. Unit: uncore_imc Write requests to memory controller. Derived from unc_m_cas_count.wr. Unit: uncore_imc Memory controller clock ticks. Use to generate percentages for memory controller CYCLES events. Unit: uncore_imc Memory page conflicts. Unit: uncore_imc unc_p_freq_band0_cyclesevent=0xbCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (UNC_P_FREQ_BAND0_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_band0_cycles %unc_p_freq_band1_cyclesevent=0xcCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (UNC_P_FREQ_BAND1_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_band1_cycles %unc_p_freq_band2_cyclesCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (UNC_P_FREQ_BAND2_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_band2_cycles %unc_p_freq_band3_cyclesevent=0xeCounts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu (UNC_P_FREQ_BAND3_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_band3_cycles %unc_p_freq_band0_transitionsevent=0xb,edge=1Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu unc_p_freq_band1_transitionsevent=0xc,edge=1Counts the number of times that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu unc_p_freq_band2_transitionsevent=0xd,edge=1Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu unc_p_freq_band3_transitionsevent=0xe,edge=1Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band3=XXX, with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu unc_p_freq_max_current_cyclesevent=0x7(UNC_P_FREQ_MAX_CURRENT_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_max_current_cycles %event=0x60Cycles spent changing Frequency. Unit: uncore_pcu unc_p_freq_ge_1200mhz_cyclesevent=0xb,filter_band0=12Counts the number of cycles that the uncore was running at a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu (UNC_P_FREQ_GE_1200MHZ_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_ge_1200mhz_cycles %unc_p_freq_ge_2000mhz_cyclesevent=0xc,filter_band1=20Counts the number of cycles that the uncore was running at a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu (UNC_P_FREQ_GE_2000MHZ_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_ge_2000mhz_cycles %unc_p_freq_ge_3000mhz_cyclesevent=0xd,filter_band2=30Counts the number of cycles that the uncore was running at a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu (UNC_P_FREQ_GE_3000MHZ_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_ge_3000mhz_cycles %unc_p_freq_ge_4000mhz_cyclesevent=0xe,filter_band3=40Counts the number of cycles that the uncore was running at a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu (UNC_P_FREQ_GE_4000MHZ_CYCLES / UNC_P_CLOCKTICKS) * 100.freq_ge_4000mhz_cycles %unc_p_freq_ge_1200mhz_transitionsevent=0xb,edge=1,filter_band0=12Counts the number of times that the uncore transitioned to a frequency greater than or equal to 1.2Ghz. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu unc_p_freq_ge_2000mhz_transitionsevent=0xc,edge=1,filter_band1=20Counts the number of times that the uncore transitioned to a frequency greater than or equal to 2Ghz. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu unc_p_freq_ge_3000mhz_transitionsevent=0xd,edge=1,filter_band2=30Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 3Ghz. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu unc_p_freq_ge_4000mhz_transitionsevent=0xe,edge=1,filter_band3=40Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to 4Ghz. Derived from unc_p_freq_band3_cycles. Unit: uncore_pcu dtlb_load_misses.demand_ld_walk_completeddtlb_load_misses.demand_ld_walk_durationl1d.allocated_in_mevent=0x51,period=2000003,umask=0x2Allocated L1D data cache lines in M statel1d.all_m_replacementevent=0x51,period=2000003,umask=0x8Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacementl1d.evictionevent=0x51,period=2000003,umask=0x4L1D data cache lines in M state evicted due to replacementThis event counts L1D data line replacements.  Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlierl1d_blocks.bank_conflict_cyclesevent=0xbf,cmask=1,period=100003,umask=0x5Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load portsl2_l1d_wb_rqsts.hit_sevent=0x28,period=200003,umask=0x2Not rejected writebacks from L1D to L2 cache lines in S statel2_store_lock_rqsts.hit_eevent=0x27,period=200003,umask=0x4RFOs that hit cache lines in E stateRetired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cacheThis event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified stateRetired load uops which data sources were HitM responses from shared LLCThis event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cacheRetired load uops which data sources were hits in LLC without snoops requiredData from local DRAM either Snoop not needed or Snoop Miss (RspI)Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)Retired load uops which data sources were data hits in LLC without snoops requiredThis event counts retired load uops that hit in the last-level (L3) cache without snoops requiredMiss in last-level (L3) cache. Excludes Unknown data-sourceAll retired load uops (Precise event)This event counts the number of load uops retired (Precise event)All retired store uops (Precise event)This event counts the number of store uops retired (Precise event)Retired load uops with locked access (Precise event)Retired load uops that split across a cacheline boundary (Precise event)This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event)Retired store uops that split across a cacheline boundary (Precise event)This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K) (Precise event)Retired load uops that miss the STLB (Precise event)Retired store uops that miss the STLB (Precise event)offcore_requests_outstanding.demand_data_rd_c6Number of AVX-256 Computational FP double precision uops issued this cycleNumber of GSSE-256 Computational FP single precision uops issued this cycleThis event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline.  It excludes cycles when the back-end cannot  accept new micro-ops.  The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-enddsb_fill.all_cancelevent=0xac,period=2000003,umask=0xaCases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limitdsb_fill.other_cancelevent=0xac,period=2000003,umask=0x2Cases of cancelling valid DSB fill not because of exceeding way limitThis event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accessesThis event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more informationUops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled.  In the ideal case 4 uops can be delivered each cycle.  The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them.  This event is used in determining the front-end bound category of the top-down pipeline slots characterizationidq_uops_not_delivered.cycles_ge_1_uop_deliv.coreevent=0x9c,cmask=4,inv=1,period=2000003,umask=0x1Cycles when 1 or more uops were delivered to the by the front endjkt metricsUOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANYUOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.CORE\,cmask\=1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\,cmask\=1@)This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequentlyLoads with latency value being above 4  (Must be precise)Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS) (Must be precise)offcore_response.all_demand_mlc_pref_reads.llc_miss.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC20077This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excludedoffcore_response.all_demand_mlc_pref_reads.llc_miss.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x600400077Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excludedoffcore_response.all_demand_mlc_pref_reads.llc_miss.remote_hitm_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x187FC20077This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excludedhw_pre_req.dl1_missevent=0x4e,period=2000003,umask=0x2Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for insts_written_to_iq.instsevent=0x17,period=2000003,umask=0x1Valid instructions written to IQ per cycleagu_bypass_cancel.countevent=0xb6,period=100003,umask=0x1This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in anevent=0x14,cmask=1,edge=1,period=100003,umask=0x1This event counts the number of the divide operations executedAll (macro) branch instructions retired. (Precise Event - PEBS) (Must be precise)br_misp_exec.all_direct_near_callevent=0x89,period=200003,umask=0xd0Speculative and retired mispredicted direct near callsbr_misp_exec.taken_direct_near_callevent=0x89,period=200003,umask=0x90Taken speculative and retired mispredicted direct near callsbr_misp_retired.near_callevent=0xc5,period=100007,umask=0x2Direct and indirect mispredicted near call instructions retired (Precise event)br_misp_retired.not_takenevent=0xc5,period=400009,umask=0x10Mispredicted not taken branch instructions retired (Precise event)br_misp_retired.takenMispredicted taken branch instructions retired (Precise event)This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other eventsEach cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDINGEach cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0cycle_activity.cycles_no_dispatchEach cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED eventEach cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDINGEach cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlersInstructions retired. (Precise Event - PEBS) (Must be precise)event=0xd,period=2000003,umask=0x40Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)event=0x3,period=100003,umask=0x10Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)event=0x3,period=100003,umask=0x1Loads delayed due to SB blocks, preceding store operations with known addresses but unknown dataThis event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issuedAliasing occurs when a load is issued after a store and their memory addresses are offset by 4K.  This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline.  The enhanced address check typically has a performance penalty of 5 cyclesld_blocks_partial.all_sta_blockevent=0x7,period=100003,umask=0x8This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this typeother_assists.itlb_miss_retiredevent=0xc1,period=100003,umask=0x2Retired instructions experiencing ITLB missespartial_rat_stalls.flags_merge_uopevent=0x59,period=2000003,umask=0x20Increments the number of flags-merge uops in flight each cyclepartial_rat_stalls.flags_merge_uop_cyclesevent=0x59,cmask=1,period=2000003,umask=0x20Performance sensitive flags-merging uops added by Sandy Bridge u-archThis event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manualpartial_rat_stalls.mul_single_uopevent=0x59,period=2000003,umask=0x80Multiply packed/scalar single precision uops allocatedpartial_rat_stalls.slow_lea_windowevent=0x59,period=2000003,umask=0x40Cycles with at least one slow LEA uop being allocatedThis event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructionsresource_stalls.lbevent=0xa2,period=2000003,umask=0x2Counts the cycles of stall due to lack of load buffersresource_stalls.lb_sbevent=0xa2,period=2000003,umask=0xaResource stalls due to load or store buffers all being in useresource_stalls.mem_rsevent=0xa2,period=2000003,umask=0xeResource stalls due to memory buffers or Reservation Station (RS) being fully utilizedresource_stalls.ooo_rsrcevent=0xa2,period=2000003,umask=0xf0Resource stalls due to Rob being full, FCSW, MXCSR and OTHERresource_stalls2.all_fl_emptyevent=0x5b,period=2000003,umask=0xcCycles with either free list is emptyresource_stalls2.all_prf_controlevent=0x5b,period=2000003,umask=0xfResource stalls2 control structures full for physical registersresource_stalls2.bob_fullevent=0x5b,period=2000003,umask=0x40Cycles when Allocator is stalled if BOB is full and new branch needs itresource_stalls2.ooo_rsrcevent=0x5b,period=2000003,umask=0x4fResource stalls out of order resources fullevent=0x5e,cmask=1,edge=1,inv=1,period=2000003,umask=0x1uops_dispatched.coreUops dispatched from any threaduops_dispatched.threadUops dispatched per threadCycles per core when load or STA uops are dispatched to port 2This event counts the number of Uops issued by the front-end of the pipeilne to the back-endThis event counts the number of micro-ops retired (Precise event)This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization (Precise event)unc_c_tor_occupancy.miss_allevent=0x36,umask=0xa,filter_opc=0x182Occupancy counter for all LLC misses; we divide this by UNC_C_CLOCKTICKS to get average Q depth. Unit: uncore_cbox (UNC_C_TOR_OCCUPANCY.MISS_ALL / UNC_C_CLOCKTICKS) * 100.tor_occupancy.miss_all %event=0x36,umask=0x3event=0x1,umask=0xcQPI clock ticks. Used to get percentages of QPI cycles events. Unit: uncore_qpi unc_m_act_countevent=0x1Memory page activates. Unit: uncore_imc event=0x4,umask=0xcMemory controller clock ticks. Used to get percentages of memory controller cycles events. Unit: uncore_imc unc_m_rpq_occupancyevent=0x80Occupancy counter for memory read queue. Unit: uncore_imc Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Unit: uncore_pcu Counts the number of times that the uncore transitioned a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band0=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band0_cycles. Unit: uncore_pcu Counts the number of times that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band1=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band1_cycles. Unit: uncore_pcu Counts the number of cycles that the uncore transitioned to a frequency greater than or equal to the frequency that is configured in the filter.  (filter_band2=XXX with XXX in 100Mhz units). One can also use inversion (filter_inv=1) to track cycles when we were less than the configured frequency. Derived from unc_p_freq_band2_cycles. Unit: uncore_pcu event=0x8,period=100003,umask=0x10This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cyclesevent=0x8,period=100003,umask=0x2Load misses at all DTLB levels that cause completed page walksThis event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB missesCounts the number of MEC requests that were not accepted into the L2Q because of any L2  queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative pathevent=0x86,period=200003,umask=0x4Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache missesThis event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache missesl2_requests.missCounts the number of L2 cache missesl2_requests.referenceCounts the total number of L2 cache referencesl2_requests_reject.allCounts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple timesevent=0x4,period=200003,umask=0x40Counts all the load micro-ops retiredThis event counts the number of load micro-ops retiredevent=0x4,period=200003,umask=0x80Counts all the store micro-ops retiredThis event counts the number of store micro-ops retiredmem_uops_retired.hitmevent=0x4,period=200003,umask=0x20Counts the loads retired that get the data from the other core in the same tile in M state  Supports address when precise (Precise event)mem_uops_retired.l1_miss_loadsevent=0x4,period=200003,umask=0x1Counts the number of load micro-ops retired that miss in L1 D cacheThis event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be countedmem_uops_retired.l2_hit_loadsevent=0x4,period=200003,umask=0x2Counts the number of load micro-ops retired that hit in the L2  Supports address when precise (Precise event)mem_uops_retired.l2_miss_loadsevent=0x4,period=100007,umask=0x4Counts the number of load micro-ops retired that miss in the L2  Supports address when precise (Precise event)mem_uops_retired.utlb_miss_loadsevent=0x4,period=200003,umask=0x10Counts the number of load micro-ops retired that caused micro TLB missCounts the matrix events specified by MSR_OFFCORE_RESPxoffcore_response.any_code_rd.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010044Counts Demand code reads and prefetch code read requests  that accounts for any responseoffcore_response.any_code_rd.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400044Counts Demand code reads and prefetch code read requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_code_rd.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400044Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_code_rd.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400044Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_code_rd.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180044Counts Demand code reads and prefetch code read requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_code_rd.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080044Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.any_code_rd.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080044Counts Demand code reads and prefetch code read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_code_rd.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000044Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_code_rd.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000044Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_code_rd.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000044Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_code_rd.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000044Counts Demand code reads and prefetch code read requests  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.any_code_rd.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000044Counts Demand code reads and prefetch code read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts Demand cacheable data and L1 prefetch data read requests  that accounts for any responseoffcore_response.any_data_rd.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800403091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_data_rd.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800403091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_data_rd.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000403091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_data_rd.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800183091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_data_rd.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800083091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.any_data_rd.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000083091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_data_rd.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_data_rd.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_data_rd.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_data_rd.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses which hit its own tile's L2 with data in S stateCounts Demand cacheable data and L1 prefetch data read requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.any_pf_l2.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010070Counts any Prefetch requests that accounts for any responseoffcore_response.any_pf_l2.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400070Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_pf_l2.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400070Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_pf_l2.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400070Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_pf_l2.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180070Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_pf_l2.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080070Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.any_pf_l2.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080070Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_pf_l2.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000070Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_pf_l2.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000070Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_pf_l2.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000070Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_pf_l2.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000070Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0event=0xb7,period=100007,umask=0x1,offcore_rsp=0x00000132f7Counts any Read request  that accounts for any responseoffcore_response.any_read.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x18004032f7Counts any Read request  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_read.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x08004032f7Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_read.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x10004032f7Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_read.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x18001832f7Counts any Read request  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_read.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x08000832f7Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.any_read.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x10000832f7Counts any Read request  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_read.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x00040032f7Counts any Read request  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_read.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x00100032f7Counts any Read request  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_read.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x00020032f7Counts any Read request  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_read.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x00080032f7Counts any Read request  that accounts for responses which hit its own tile's L2 with data in S stateevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x40000032f7Counts any Read request  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts any request that accounts for any responseoffcore_response.any_request.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800408000Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_request.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800408000Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_request.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000408000Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_request.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800188000Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_request.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800088000Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.any_request.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000088000Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_request.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004008000Counts any request that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_request.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010008000Counts any request that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_request.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002008000Counts any request that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_request.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008008000Counts any request that accounts for responses which hit its own tile's L2 with data in S stateCounts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts Demand cacheable data write requests  that accounts for any responseoffcore_response.any_rfo.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400022Counts Demand cacheable data write requests  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.any_rfo.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400022Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.any_rfo.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400022Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.any_rfo.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180022Counts Demand cacheable data write requests  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.any_rfo.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080022Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.any_rfo.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080022Counts Demand cacheable data write requests  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.any_rfo.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000022Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.any_rfo.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000022Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.any_rfo.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000022Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.any_rfo.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000022Counts Demand cacheable data write requests  that accounts for responses which hit its own tile's L2 with data in S stateCounts Demand cacheable data write requests  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts Bus locks and split lock requests that accounts for any responseoffcore_response.bus_locks.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400400Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.bus_locks.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400400Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.bus_locks.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400400Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.bus_locks.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180400Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.bus_locks.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080400Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.bus_locks.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080400Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.bus_locks.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000400Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.bus_locks.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000400Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.bus_locks.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000400Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.bus_locks.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000400Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S stateCounts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts demand code reads and prefetch code reads that accounts for any responseoffcore_response.demand_code_rd.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400004Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.demand_code_rd.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400004Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.demand_code_rd.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400004Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.demand_code_rd.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180004Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.demand_code_rd.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080004Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.demand_code_rd.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080004Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.demand_code_rd.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000004Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.demand_code_rd.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000004Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.demand_code_rd.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000004Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.demand_code_rd.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000004Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S stateCounts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts demand cacheable data and L1 prefetch data reads that accounts for any responseoffcore_response.demand_data_rd.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.demand_data_rd.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.demand_data_rd.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.demand_data_rd.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.demand_data_rd.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000001Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.demand_data_rd.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000001Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.demand_data_rd.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000001Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.demand_data_rd.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000001Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S stateCounts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts Demand cacheable data writes that accounts for any responseoffcore_response.demand_rfo.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400002Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.demand_rfo.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400002Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.demand_rfo.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400002Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.demand_rfo.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180002Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.demand_rfo.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080002Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.demand_rfo.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080002Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.demand_rfo.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000002Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.demand_rfo.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000002Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.demand_rfo.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000002Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.demand_rfo.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000002Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S stateCounts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any responseoffcore_response.partial_reads.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for any responseoffcore_response.partial_reads.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.partial_reads.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.partial_reads.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.partial_reads.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.partial_reads.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.partial_reads.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.partial_reads.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.partial_reads.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.partial_reads.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.partial_reads.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.partial_reads.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0offcore_response.partial_streaming_stores.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000014000Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any responseoffcore_response.partial_writes.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any responseoffcore_response.partial_writes.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.partial_writes.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.partial_writes.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.partial_writes.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.partial_writes.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.partial_writes.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.partial_writes.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.partial_writes.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.partial_writes.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.partial_writes.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S stateCounts L1 data HW prefetches that accounts for any responseoffcore_response.pf_l1_data_rd.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800402000Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.pf_l1_data_rd.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800402000Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_l1_data_rd.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000402000Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.pf_l1_data_rd.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800182000Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.pf_l1_data_rd.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800082000Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.pf_l1_data_rd.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000082000Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004002000Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010002000Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002002000Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.pf_l1_data_rd.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008002000Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S stateCounts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0event=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010040Counts L2 code HW prefetches that accounts for any responseoffcore_response.pf_l2_code_rd.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800400040Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.pf_l2_code_rd.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400040Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_l2_code_rd.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400040Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.pf_l2_code_rd.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180040Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.pf_l2_code_rd.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080040Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.pf_l2_code_rd.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080040Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.pf_l2_code_rd.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000040Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_l2_code_rd.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000040Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_l2_code_rd.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000040Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any responseoffcore_response.pf_l2_rfo.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_l2_rfo.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.pf_l2_rfo.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.pf_l2_rfo.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.pf_l2_rfo.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.pf_l2_rfo.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.pf_l2_rfo.supplier_noneevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000020020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier detailsoffcore_response.pf_software.any_responseCounts Software Prefetches that accounts for any responseoffcore_response.pf_software.l2_hit_far_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800401000Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster modeoffcore_response.pf_software.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800401000Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.pf_software.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000401000Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.pf_software.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800181000Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.pf_software.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800081000Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.pf_software.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000081000Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.pf_software.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004001000Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.pf_software.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010001000Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.pf_software.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002001000Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.pf_software.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008001000Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.pf_software.outstandingCounts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any responseoffcore_response.uc_code_reads.any_responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000010200Counts UC code reads (valid only for Outstanding response type)  that accounts for any responseoffcore_response.uc_code_reads.l2_hit_far_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800400200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster modeoffcore_response.uc_code_reads.l2_hit_far_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000400200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M stateoffcore_response.uc_code_reads.l2_hit_near_tileevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1800180200Counts UC code reads (valid only for Outstanding response type)  that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateoffcore_response.uc_code_reads.l2_hit_near_tile_e_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0800080200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F stateoffcore_response.uc_code_reads.l2_hit_near_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000080200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M stateoffcore_response.uc_code_reads.l2_hit_this_tile_eevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0004000200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in E stateoffcore_response.uc_code_reads.l2_hit_this_tile_fevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0010000200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in F stateoffcore_response.uc_code_reads.l2_hit_this_tile_mevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0002000200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in M stateoffcore_response.uc_code_reads.l2_hit_this_tile_sevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0008000200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses which hit its own tile's L2 with data in S stateoffcore_response.uc_code_reads.outstandingevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x4000000200Counts UC code reads (valid only for Outstanding response type)  that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0Counts the number of floating operations retired that required microcode assistsThis event counts the number of times that the pipeline stalled due to FP operations needing assistsuops_retired.packed_simdevent=0xc2,period=200003,umask=0x40Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multipliesThis event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multipliesuops_retired.scalar_simdevent=0xc2,period=200003,umask=0x20Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrtThis event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrtCounts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front endCounts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front endCounts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front endCounts all instruction fetches, including uncacheable fetchesCounts all instruction fetches that hit the instruction cacheCounts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstandingCounts the number of times the MSROM starts a flow of uopsCounts the number of times the machine clears due to memory ordering hazardsoffcore_response.any_code_rd.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800044Counts Demand code reads and prefetch code read requests  that accounts for responses from DDR (local and far)offcore_response.any_code_rd.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000044Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Faroffcore_response.any_code_rd.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800044Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Localoffcore_response.any_code_rd.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600044Counts Demand code reads and prefetch code read requests  that accounts for responses from MCDRAM (local and far)offcore_response.any_code_rd.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400044Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_code_rd.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200044Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Localoffcore_response.any_data_rd.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181803091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from DDR (local and far)offcore_response.any_data_rd.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101003091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Faroffcore_response.any_data_rd.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080803091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Localoffcore_response.any_data_rd.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180603091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from MCDRAM (local and far)offcore_response.any_data_rd.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100403091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_data_rd.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080203091Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Localoffcore_response.any_pf_l2.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000070Counts any Prefetch requests that accounts for data responses from DRAM Faroffcore_response.any_pf_l2.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800070Counts any Prefetch requests that accounts for data responses from DRAM Localoffcore_response.any_pf_l2.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600070Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)offcore_response.any_pf_l2.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400070Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_pf_l2.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200070Counts any Prefetch requests that accounts for data responses from MCDRAM Localoffcore_response.any_read.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x01818032f7Counts any Read request  that accounts for responses from DDR (local and far)offcore_response.any_read.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x01010032f7Counts any Read request  that accounts for data responses from DRAM Faroffcore_response.any_read.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x00808032f7Counts any Read request  that accounts for data responses from DRAM Localoffcore_response.any_read.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x01806032f7Counts any Read request  that accounts for responses from MCDRAM (local and far)offcore_response.any_read.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x01004032f7Counts any Read request  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_read.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x00802032f7Counts any Read request  that accounts for data responses from MCDRAM Localoffcore_response.any_request.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181808000Counts any request that accounts for responses from DDR (local and far)offcore_response.any_request.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101008000Counts any request that accounts for data responses from DRAM Faroffcore_response.any_request.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080808000Counts any request that accounts for data responses from DRAM Localoffcore_response.any_request.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180608000Counts any request that accounts for responses from MCDRAM (local and far)offcore_response.any_request.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100408000Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_request.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080208000Counts any request that accounts for data responses from MCDRAM Localoffcore_response.any_rfo.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800022Counts Demand cacheable data write requests  that accounts for responses from DDR (local and far)offcore_response.any_rfo.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000022Counts Demand cacheable data write requests  that accounts for data responses from DRAM Faroffcore_response.any_rfo.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800022Counts Demand cacheable data write requests  that accounts for data responses from DRAM Localoffcore_response.any_rfo.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600022Counts Demand cacheable data write requests  that accounts for responses from MCDRAM (local and far)offcore_response.any_rfo.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400022Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.any_rfo.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200022Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Localoffcore_response.bus_locks.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800400Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)offcore_response.bus_locks.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000400Counts Bus locks and split lock requests that accounts for data responses from DRAM Faroffcore_response.bus_locks.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800400Counts Bus locks and split lock requests that accounts for data responses from DRAM Localoffcore_response.bus_locks.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600400Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)offcore_response.bus_locks.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400400Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.bus_locks.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200400Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Localoffcore_response.demand_code_rd.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800004Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)offcore_response.demand_code_rd.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000004Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Faroffcore_response.demand_code_rd.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800004Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Localoffcore_response.demand_code_rd.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600004Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)offcore_response.demand_code_rd.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400004Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.demand_code_rd.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200004Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Localoffcore_response.demand_data_rd.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)offcore_response.demand_data_rd.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000001Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Faroffcore_response.demand_data_rd.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800001Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Localoffcore_response.demand_data_rd.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600001Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)offcore_response.demand_data_rd.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400001Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.demand_data_rd.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200001Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Localoffcore_response.demand_rfo.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800002Counts Demand cacheable data writes that accounts for responses from DDR (local and far)offcore_response.demand_rfo.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000002Counts Demand cacheable data writes that accounts for data responses from DRAM Faroffcore_response.demand_rfo.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800002Counts Demand cacheable data writes that accounts for data responses from DRAM Localoffcore_response.demand_rfo.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600002Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)offcore_response.demand_rfo.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400002Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.demand_rfo.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200002Counts Demand cacheable data writes that accounts for data responses from MCDRAM Localoffcore_response.partial_reads.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from DDR (local and far)offcore_response.partial_reads.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Faroffcore_response.partial_reads.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Localoffcore_response.partial_reads.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from MCDRAM (local and far)offcore_response.partial_reads.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.partial_reads.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Localoffcore_response.partial_reads.non_dramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x2000020080Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from any NON_DRAM system address. This includes MMIO transactionsoffcore_response.partial_writes.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Faroffcore_response.partial_writes.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Localoffcore_response.partial_writes.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)offcore_response.partial_writes.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.partial_writes.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200100Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Localoffcore_response.pf_l1_data_rd.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181802000Counts L1 data HW prefetches that accounts for responses from DDR (local and far)offcore_response.pf_l1_data_rd.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101002000Counts L1 data HW prefetches that accounts for data responses from DRAM Faroffcore_response.pf_l1_data_rd.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080802000Counts L1 data HW prefetches that accounts for data responses from DRAM Localoffcore_response.pf_l1_data_rd.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100402000Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_l1_data_rd.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080202000Counts L1 data HW prefetches that accounts for data responses from MCDRAM Localoffcore_response.pf_l2_code_rd.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800040Counts L2 code HW prefetches that accounts for responses from DDR (local and far)offcore_response.pf_l2_code_rd.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000040Counts L2 code HW prefetches that accounts for data responses from DRAM Faroffcore_response.pf_l2_code_rd.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800040Counts L2 code HW prefetches that accounts for data responses from DRAM Localoffcore_response.pf_l2_code_rd.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400040Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_l2_code_rd.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200040Counts L2 code HW prefetches that accounts for data responses from MCDRAM Localoffcore_response.pf_l2_rfo.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)offcore_response.pf_l2_rfo.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Faroffcore_response.pf_l2_rfo.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Localoffcore_response.pf_l2_rfo.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)offcore_response.pf_l2_rfo.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_l2_rfo.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Localoffcore_response.pf_l2_rfo.non_dramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x2000020020Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactionsoffcore_response.pf_software.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181801000Counts Software Prefetches that accounts for responses from DDR (local and far)offcore_response.pf_software.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101001000Counts Software Prefetches that accounts for data responses from DRAM Faroffcore_response.pf_software.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080801000Counts Software Prefetches that accounts for data responses from DRAM Localoffcore_response.pf_software.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180601000Counts Software Prefetches that accounts for responses from MCDRAM (local and far)offcore_response.pf_software.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100401000Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.pf_software.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080201000Counts Software Prefetches that accounts for data responses from MCDRAM Localoffcore_response.uc_code_reads.ddrevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0181800200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from DDR (local and far)offcore_response.uc_code_reads.ddr_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0101000200Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Faroffcore_response.uc_code_reads.ddr_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080800200Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Localoffcore_response.uc_code_reads.mcdramevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0180600200Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from MCDRAM (local and far)offcore_response.uc_code_reads.mcdram_farevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0100400200Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Far or Other tile L2 hit faroffcore_response.uc_code_reads.mcdram_nearevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080200200Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM LocalCounts the number of branch instructions retired (Precise event)Counts the number of near CALL branch instructions retired (Precise event)Counts the number of far branch instructions retired (Precise event)Counts the number of near indirect CALL branch instructions retired (Precise event)Counts the number of branch instructions retired that were conditional jumps (Precise event)Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP (Precise event)Counts the number of near relative CALL branch instructions retired (Precise event)Counts the number of near RET branch instructions retired (Precise event)Counts the number of branch instructions retired that were conditional jumps and predicted taken (Precise event)Counts the number of mispredicted branch instructions retired (Precise event)br_misp_retired.callevent=0xc5,period=200003,umask=0xf9Counts the number of mispredicted near CALL branch instructions retired (Precise event)br_misp_retired.far_branchevent=0xc5,period=200003,umask=0xbfCounts the number of mispredicted far branch instructions retired (Precise event)Counts the number of mispredicted near indirect CALL branch instructions retired (Precise event)Counts the number of mispredicted branch instructions retired that were conditional jumps (Precise event)Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP (Precise event)br_misp_retired.rel_callevent=0xc5,period=200003,umask=0xfdCounts the number of mispredicted near relative CALL branch instructions retired (Precise event)Counts the number of mispredicted near RET branch instructions retired (Precise event)Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken (Precise event)Counts the number of unhalted reference clock cyclesFixed Counter: Counts the number of unhalted reference clock cyclesFixed Counter: Counts the number of unhalted core clock cyclesThis event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counterCounts the number of unhalted core clock cyclesevent=0xcd,period=2000003,umask=0x1Cycles the number of core cycles when divider is busy.  Does not imply a stall waiting for the dividerThis event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector dividesFixed Counter: Counts the number of instructions retiredThis event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or trapsCounts the total number of instructions retiredCounts all nukesCounts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code pageno_alloc_cycles.allevent=0xca,period=200003,umask=0x7fCounts the total number of core cycles when no micro-ops are allocated for any reasonno_alloc_cycles.mispredictsevent=0xca,period=200003,umask=0x4Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retireThis event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retireno_alloc_cycles.not_deliveredevent=0xca,period=200003,umask=0x90Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocationThis event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetchedno_alloc_cycles.rat_stallevent=0xca,period=200003,umask=0x20Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is assertedno_alloc_cycles.rob_fullCounts the number of core cycles when no micro-ops are allocated and the ROB is fullrecycleq.any_ldevent=0x3,period=200003,umask=0x40Counts any retired load that was pushed into the recycle queue for any reasonrecycleq.any_stevent=0x3,period=200003,umask=0x80Counts any retired store that was pushed into the recycle queue for any reasonrecycleq.ld_block_std_notreadyCounts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not readyrecycleq.ld_block_st_forwardCounts the number of occurences a retired load gets blocked because its address partially overlaps with a store  Supports address when precise (Precise event)recycleq.ld_splitsCounts the number of occurences a retired load that is a cache line split. Each split should be counted only once  Supports address when precise (Precise event)recycleq.lockCounts all the retired locked loads. It does not include stores because we would double count if we count storesrecycleq.sta_fullevent=0x3,period=200003,umask=0x20Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is fullrecycleq.st_splitsCounts the number of occurences a retired store that is a cache line split. Each split should be counted only onceThis event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only oncers_full_stall.allevent=0xcb,period=200003,umask=0x1fCounts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is fullrs_full_stall.mecevent=0xcb,period=200003,umask=0x1Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entryCounts the number of micro-ops retiredThis event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assistsCounts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS)This event counts the number of micro-ops retired that were supplied from MSROMunc_m_cas_count.rdevent=0x3,umask=0x01ddr bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_imc 6.4e-05MiBunc_m_cas_count.wrevent=0x3,umask=0x02ddr bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_imc unc_e_rpq_insertsevent=0x1,umask=0x01mcdram bandwidth read (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk uncore_edc_eclkunc_e_wpq_insertsevent=0x2,umask=0x01mcdram bandwidth write (CPU traffic only) (MB/sec). Unit: uncore_edc_eclk event=0x4,period=200003,umask=0x8Counts the number of load micro-ops retired that cause a DTLB miss  Supports address when precise (Precise event)Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be includedThis event counts every cycle when a data (D) page walk or instruction (I) page walk is in progressCounts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be includedevent=0x5,edge=1,period=100003,umask=0x1Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be countedCounts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be includedThis event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progressevent=0x5,edge=1,period=100003,umask=0x2Counts the total I-side page walks that are completedevent=0x5,edge=1,period=100003,umask=0x3Counts the total page walks that are completed (I-side and D-side)cache_lock_cycles.l1devent=0x63,period=2000000,umask=0x2Cycles L1D lockedcache_lock_cycles.l1d_l2event=0x63,period=2000000,umask=0x1Cycles L1D and L2 lockedl1d.m_evictevent=0x51,period=2000000,umask=0x4L1D cache lines replaced in M statel1d.m_replevent=0x51,period=2000000,umask=0x2L1D cache lines allocated in the M statel1d.m_snoop_evictevent=0x51,period=2000000,umask=0x8L1D snoop eviction of cache lines in M statel1d.replevent=0x51,period=2000000,umask=0x1L1 data cache lines allocatedl1d_all_ref.anyevent=0x43,period=2000000,umask=0x1All references to the L1 data cachel1d_all_ref.cacheableevent=0x43,period=2000000,umask=0x2L1 data cacheable reads and writesl1d_cache_ld.e_stateevent=0x40,period=2000000,umask=0x4L1 data cache read in E statel1d_cache_ld.i_stateevent=0x40,period=2000000,umask=0x1L1 data cache read in I state (misses)l1d_cache_ld.mesievent=0x40,period=2000000,umask=0xfL1 data cache readsl1d_cache_ld.m_stateevent=0x40,period=2000000,umask=0x8L1 data cache read in M statel1d_cache_ld.s_stateevent=0x40,period=2000000,umask=0x2L1 data cache read in S statel1d_cache_lock.e_stateevent=0x42,period=2000000,umask=0x4L1 data cache load locks in E statel1d_cache_lock.hitevent=0x42,period=2000000,umask=0x1L1 data cache load lock hitsl1d_cache_lock.m_stateevent=0x42,period=2000000,umask=0x8L1 data cache load locks in M statel1d_cache_lock.s_stateevent=0x42,period=2000000,umask=0x2L1 data cache load locks in S statel1d_cache_lock_fb_hitevent=0x53,period=2000000,umask=0x1L1D load lock accepted in fill bufferl1d_cache_prefetch_lock_fb_hitevent=0x52,period=2000000,umask=0x1L1D prefetch load lock accepted in fill bufferl1d_cache_st.e_stateevent=0x41,period=2000000,umask=0x4L1 data cache stores in E statel1d_cache_st.m_stateevent=0x41,period=2000000,umask=0x8L1 data cache stores in M statel1d_cache_st.s_stateevent=0x41,period=2000000,umask=0x2L1 data cache stores in S statel1d_prefetch.missevent=0x4e,period=200000,umask=0x2L1D hardware prefetch missesl1d_prefetch.requestsevent=0x4e,period=200000,umask=0x1L1D hardware prefetch requestsl1d_prefetch.triggersevent=0x4e,period=200000,umask=0x4L1D hardware prefetch requests triggeredl1d_wb_l2.e_stateevent=0x28,period=100000,umask=0x4L1 writebacks to L2 in E statel1d_wb_l2.i_stateevent=0x28,period=100000,umask=0x1L1 writebacks to L2 in I state (misses)l1d_wb_l2.mesievent=0x28,period=100000,umask=0xfAll L1 writebacks to L2l1d_wb_l2.m_stateevent=0x28,period=100000,umask=0x8L1 writebacks to L2 in M statel1d_wb_l2.s_stateevent=0x28,period=100000,umask=0x2L1 writebacks to L2 in S statel2_data_rqsts.anyevent=0x26,period=200000,umask=0xffAll L2 data requestsl2_data_rqsts.demand.e_stateevent=0x26,period=200000,umask=0x4L2 data demand loads in E statel2_data_rqsts.demand.i_stateevent=0x26,period=200000,umask=0x1L2 data demand loads in I state (misses)l2_data_rqsts.demand.mesievent=0x26,period=200000,umask=0xfL2 data demand requestsl2_data_rqsts.demand.m_stateevent=0x26,period=200000,umask=0x8L2 data demand loads in M statel2_data_rqsts.demand.s_stateevent=0x26,period=200000,umask=0x2L2 data demand loads in S statel2_data_rqsts.prefetch.e_stateL2 data prefetches in E statel2_data_rqsts.prefetch.i_stateevent=0x26,period=200000,umask=0x10L2 data prefetches in the I state (misses)l2_data_rqsts.prefetch.mesievent=0x26,period=200000,umask=0xf0All L2 data prefetchesl2_data_rqsts.prefetch.m_stateevent=0x26,period=200000,umask=0x80L2 data prefetches in M statel2_data_rqsts.prefetch.s_stateevent=0x26,period=200000,umask=0x20L2 data prefetches in the S statel2_lines_in.anyevent=0xf1,period=100000,umask=0x7L2 lines alloacatedl2_lines_in.e_stateevent=0xf1,period=100000,umask=0x4L2 lines allocated in the E statel2_lines_in.s_stateevent=0xf1,period=100000,umask=0x2L2 lines allocated in the S statel2_lines_out.anyevent=0xf2,period=100000,umask=0xfL2 lines evictedevent=0xf2,period=100000,umask=0x1L2 lines evicted by a demand requestevent=0xf2,period=100000,umask=0x2L2 modified lines evicted by a demand requestl2_lines_out.prefetch_cleanevent=0xf2,period=100000,umask=0x4L2 lines evicted by a prefetch requestl2_lines_out.prefetch_dirtyevent=0xf2,period=100000,umask=0x8L2 modified lines evicted by a prefetch requestl2_rqsts.ifetchesevent=0x24,period=200000,umask=0x30L2 instruction fetchesl2_rqsts.ifetch_hitevent=0x24,period=200000,umask=0x10L2 instruction fetch hitsl2_rqsts.ifetch_missevent=0x24,period=200000,umask=0x20L2 instruction fetch missesl2_rqsts.ld_hitevent=0x24,period=200000,umask=0x1L2 load hitsl2_rqsts.ld_missevent=0x24,period=200000,umask=0x2L2 load missesl2_rqsts.loadsevent=0x24,period=200000,umask=0x3L2 requestsevent=0x24,period=200000,umask=0xaaAll L2 missesl2_rqsts.prefetchesevent=0x24,period=200000,umask=0xc0All L2 prefetchesl2_rqsts.prefetch_hitL2 prefetch hitsl2_rqsts.prefetch_missevent=0x24,period=200000,umask=0x80L2 prefetch missesevent=0x24,period=200000,umask=0xffl2_rqsts.rfosevent=0x24,period=200000,umask=0xcL2 RFO requestsevent=0x24,period=200000,umask=0x4L2 RFO hitsevent=0x24,period=200000,umask=0x8L2 RFO missesl2_transactions.anyevent=0xf0,period=200000,umask=0x80All L2 transactionsl2_transactions.fillevent=0xf0,period=200000,umask=0x20L2 fill transactionsl2_transactions.ifetchevent=0xf0,period=200000,umask=0x4L2 instruction fetch transactionsl2_transactions.l1d_wbevent=0xf0,period=200000,umask=0x10L1D writeback to L2 transactionsl2_transactions.loadevent=0xf0,period=200000,umask=0x1L2 Load transactionsl2_transactions.prefetchevent=0xf0,period=200000,umask=0x8L2 prefetch transactionsl2_transactions.rfoevent=0xf0,period=200000,umask=0x2L2 RFO transactionsl2_transactions.wbevent=0xf0,period=200000,umask=0x40L2 writeback to LLC transactionsl2_write.lock.e_stateevent=0x27,period=100000,umask=0x40L2 demand lock RFOs in E statel2_write.lock.hitevent=0x27,period=100000,umask=0xe0All demand L2 lock RFOs that hit the cachel2_write.lock.i_stateevent=0x27,period=100000,umask=0x10L2 demand lock RFOs in I state (misses)l2_write.lock.mesievent=0x27,period=100000,umask=0xf0All demand L2 lock RFOsl2_write.lock.m_stateevent=0x27,period=100000,umask=0x80L2 demand lock RFOs in M statel2_write.lock.s_stateevent=0x27,period=100000,umask=0x20L2 demand lock RFOs in S statel2_write.rfo.hitevent=0x27,period=100000,umask=0xeAll L2 demand store RFOs that hit the cachel2_write.rfo.i_stateevent=0x27,period=100000,umask=0x1L2 demand store RFOs in I state (misses)l2_write.rfo.mesievent=0x27,period=100000,umask=0xfAll L2 demand store RFOsl2_write.rfo.m_stateevent=0x27,period=100000,umask=0x8L2 demand store RFOs in M statel2_write.rfo.s_stateevent=0x27,period=100000,umask=0x2L2 demand store RFOs in S stateevent=0x2e,period=100000,umask=0x41Longest latency cache missLongest latency cache referencemem_inst_retired.latency_above_threshold_0event=0xb,period=2000000,umask=0x10,ldlat=0x0Memory instructions retired above 0 clocks (Precise Event)mem_inst_retired.latency_above_threshold_1024event=0xb,period=100,umask=0x10,ldlat=0x400Memory instructions retired above 1024 clocks (Precise Event)mem_inst_retired.latency_above_threshold_128event=0xb,period=1000,umask=0x10,ldlat=0x80Memory instructions retired above 128 clocks (Precise Event)mem_inst_retired.latency_above_threshold_16event=0xb,period=10000,umask=0x10,ldlat=0x10Memory instructions retired above 16 clocks (Precise Event)mem_inst_retired.latency_above_threshold_16384event=0xb,period=5,umask=0x10,ldlat=0x4000Memory instructions retired above 16384 clocks (Precise Event)mem_inst_retired.latency_above_threshold_2048event=0xb,period=50,umask=0x10,ldlat=0x800Memory instructions retired above 2048 clocks (Precise Event)mem_inst_retired.latency_above_threshold_256event=0xb,period=500,umask=0x10,ldlat=0x100Memory instructions retired above 256 clocks (Precise Event)mem_inst_retired.latency_above_threshold_32event=0xb,period=5000,umask=0x10,ldlat=0x20Memory instructions retired above 32 clocks (Precise Event)mem_inst_retired.latency_above_threshold_32768event=0xb,period=3,umask=0x10,ldlat=0x8000Memory instructions retired above 32768 clocks (Precise Event)mem_inst_retired.latency_above_threshold_4event=0xb,period=50000,umask=0x10,ldlat=0x4Memory instructions retired above 4 clocks (Precise Event)mem_inst_retired.latency_above_threshold_4096event=0xb,period=20,umask=0x10,ldlat=0x1000Memory instructions retired above 4096 clocks (Precise Event)mem_inst_retired.latency_above_threshold_512event=0xb,period=200,umask=0x10,ldlat=0x200Memory instructions retired above 512 clocks (Precise Event)mem_inst_retired.latency_above_threshold_64event=0xb,period=2000,umask=0x10,ldlat=0x40Memory instructions retired above 64 clocks (Precise Event)mem_inst_retired.latency_above_threshold_8event=0xb,period=20000,umask=0x10,ldlat=0x8Memory instructions retired above 8 clocks (Precise Event)mem_inst_retired.latency_above_threshold_8192event=0xb,period=10,umask=0x10,ldlat=0x2000Memory instructions retired above 8192 clocks (Precise Event)mem_inst_retired.loadsevent=0xb,period=2000000,umask=0x1Instructions retired which contains a load (Precise Event)mem_inst_retired.storesevent=0xb,period=2000000,umask=0x2Instructions retired which contains a store (Precise Event)mem_load_retired.hit_lfbevent=0xcb,period=200000,umask=0x40Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)mem_load_retired.l1d_hitevent=0xcb,period=2000000,umask=0x1Retired loads that hit the L1 data cache (Precise Event)event=0xcb,period=200000,umask=0x2Retired loads that hit the L2 cache (Precise Event)mem_load_retired.llc_missevent=0xcb,period=10000,umask=0x10Retired loads that miss the LLC cache (Precise Event)mem_load_retired.llc_unshared_hitevent=0xcb,period=40000,umask=0x4Retired loads that hit valid versions in the LLC cache (Precise Event)mem_load_retired.other_core_l2_hit_hitmevent=0xcb,period=40000,umask=0x8Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)mem_uncore_retired.local_dramevent=0xf,period=10000,umask=0x20Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)mem_uncore_retired.other_core_l2_hitmevent=0xf,period=40000,umask=0x2Load instructions retired that HIT modified data in sibling core (Precise Event)mem_uncore_retired.remote_cache_local_home_hitevent=0xf,period=20000,umask=0x8Load instructions retired remote cache HIT data source (Precise Event)mem_uncore_retired.remote_dramevent=0xf,period=10000,umask=0x10Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)mem_uncore_retired.uncacheableevent=0xf,period=4000,umask=0x80Load instructions retired IO (Precise Event)offcore_requests.l1d_writebackevent=0xb0,period=100000,umask=0x40Offcore L1 data cache writebacksoffcore_requests_sq_fullevent=0xb2,period=100000,umask=0x1Offcore requests blocked due to Super Queue fulloffcore_response.any_data.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F11Offcore data reads satisfied by any cache or DRAMoffcore_response.any_data.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF11All offcore data readsoffcore_response.any_data.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8011Offcore data reads satisfied by the IO, CSR, MMIO unitoffcore_response.any_data.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x111Offcore data reads satisfied by the LLC and not found in a sibling coreoffcore_response.any_data.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x211Offcore data reads satisfied by the LLC and HIT in a sibling coreoffcore_response.any_data.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x411Offcore data reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_data.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x711Offcore data reads satisfied by the LLCoffcore_response.any_data.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4711Offcore data reads satisfied by the LLC or local DRAMoffcore_response.any_data.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1811Offcore data reads satisfied by a remote cacheoffcore_response.any_data.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3811Offcore data reads satisfied by a remote cache or remote DRAMoffcore_response.any_data.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1011Offcore data reads that HIT in a remote cacheoffcore_response.any_data.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x811Offcore data reads that HITM in a remote cacheoffcore_response.any_ifetch.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F44Offcore code reads satisfied by any cache or DRAMoffcore_response.any_ifetch.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF44All offcore code readsoffcore_response.any_ifetch.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8044Offcore code reads satisfied by the IO, CSR, MMIO unitoffcore_response.any_ifetch.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x144Offcore code reads satisfied by the LLC and not found in a sibling coreoffcore_response.any_ifetch.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x244Offcore code reads satisfied by the LLC and HIT in a sibling coreoffcore_response.any_ifetch.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x444Offcore code reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_ifetch.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x744Offcore code reads satisfied by the LLCoffcore_response.any_ifetch.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4744Offcore code reads satisfied by the LLC or local DRAMoffcore_response.any_ifetch.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1844Offcore code reads satisfied by a remote cacheoffcore_response.any_ifetch.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3844Offcore code reads satisfied by a remote cache or remote DRAMoffcore_response.any_ifetch.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1044Offcore code reads that HIT in a remote cacheoffcore_response.any_ifetch.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x844Offcore code reads that HITM in a remote cacheoffcore_response.any_request.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7FFFOffcore requests satisfied by any cache or DRAMoffcore_response.any_request.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFFFFAll offcore requestsoffcore_response.any_request.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x80FFOffcore requests satisfied by the IO, CSR, MMIO unitoffcore_response.any_request.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1FFOffcore requests satisfied by the LLC and not found in a sibling coreoffcore_response.any_request.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2FFOffcore requests satisfied by the LLC and HIT in a sibling coreoffcore_response.any_request.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4FFOffcore requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_request.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7FFOffcore requests satisfied by the LLCoffcore_response.any_request.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x47FFOffcore requests satisfied by the LLC or local DRAMoffcore_response.any_request.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x18FFOffcore requests satisfied by a remote cacheoffcore_response.any_request.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x38FFOffcore requests satisfied by a remote cache or remote DRAMoffcore_response.any_request.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x10FFOffcore requests that HIT in a remote cacheoffcore_response.any_request.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8FFOffcore requests that HITM in a remote cacheoffcore_response.any_rfo.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F22Offcore RFO requests satisfied by any cache or DRAMoffcore_response.any_rfo.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF22All offcore RFO requestsoffcore_response.any_rfo.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8022Offcore RFO requests satisfied by the IO, CSR, MMIO unitoffcore_response.any_rfo.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x122Offcore RFO requests satisfied by the LLC and not found in a sibling coreoffcore_response.any_rfo.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x222Offcore RFO requests satisfied by the LLC and HIT in a sibling coreoffcore_response.any_rfo.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x422Offcore RFO requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.any_rfo.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x722Offcore RFO requests satisfied by the LLCoffcore_response.any_rfo.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4722Offcore RFO requests satisfied by the LLC or local DRAMoffcore_response.any_rfo.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1822Offcore RFO requests satisfied by a remote cacheoffcore_response.any_rfo.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3822Offcore RFO requests satisfied by a remote cache or remote DRAMoffcore_response.any_rfo.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1022Offcore RFO requests that HIT in a remote cacheoffcore_response.any_rfo.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x822Offcore RFO requests that HITM in a remote cacheoffcore_response.corewb.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F08Offcore writebacks to any cache or DRAMoffcore_response.corewb.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF08All offcore writebacksoffcore_response.corewb.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8008Offcore writebacks to the IO, CSR, MMIO unitoffcore_response.corewb.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x108Offcore writebacks to the LLC and not found in a sibling coreoffcore_response.corewb.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x408Offcore writebacks to the LLC  and HITM in a sibling coreoffcore_response.corewb.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x708Offcore writebacks to the LLCoffcore_response.corewb.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4708Offcore writebacks to the LLC or local DRAMoffcore_response.corewb.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1808Offcore writebacks to a remote cacheoffcore_response.corewb.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3808Offcore writebacks to a remote cache or remote DRAMoffcore_response.corewb.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1008Offcore writebacks that HIT in a remote cacheoffcore_response.corewb.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x808Offcore writebacks that HITM in a remote cacheoffcore_response.data_ifetch.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F77Offcore code or data read requests satisfied by any cache or DRAMoffcore_response.data_ifetch.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF77All offcore code or data read requestsoffcore_response.data_ifetch.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8077Offcore code or data read requests satisfied by the IO, CSR, MMIO unitoffcore_response.data_ifetch.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x177Offcore code or data read requests satisfied by the LLC and not found in a sibling coreoffcore_response.data_ifetch.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x277Offcore code or data read requests satisfied by the LLC and HIT in a sibling coreoffcore_response.data_ifetch.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x477Offcore code or data read requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.data_ifetch.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x777Offcore code or data read requests satisfied by the LLCoffcore_response.data_ifetch.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4777Offcore code or data read requests satisfied by the LLC or local DRAMoffcore_response.data_ifetch.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1877Offcore code or data read requests satisfied by a remote cacheoffcore_response.data_ifetch.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3877Offcore code or data read requests satisfied by a remote cache or remote DRAMoffcore_response.data_ifetch.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1077Offcore code or data read requests that HIT in a remote cacheoffcore_response.data_ifetch.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x877Offcore code or data read requests that HITM in a remote cacheoffcore_response.data_in.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F33Offcore request = all data, response = any cache_dramoffcore_response.data_in.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF33Offcore request = all data, response = any locationoffcore_response.data_in.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8033Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unitoffcore_response.data_in.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x133Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling coreoffcore_response.data_in.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x233Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling coreoffcore_response.data_in.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x433Offcore data reads, RFO's and prefetches satisfied by the LLC  and HITM in a sibling coreoffcore_response.data_in.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x733Offcore request = all data, response = local cacheoffcore_response.data_in.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4733Offcore request = all data, response = local cache or dramoffcore_response.data_in.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1833Offcore request = all data, response = remote cacheoffcore_response.data_in.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3833Offcore request = all data, response = remote cache or dramoffcore_response.data_in.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1033Offcore data reads, RFO's and prefetches that HIT in a remote cacheoffcore_response.data_in.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x833Offcore data reads, RFO's and prefetches that HITM in a remote cacheoffcore_response.demand_data.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F03Offcore demand data requests satisfied by any cache or DRAMoffcore_response.demand_data.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF03All offcore demand data requestsoffcore_response.demand_data.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8003Offcore demand data requests satisfied by the IO, CSR, MMIO unitoffcore_response.demand_data.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x103Offcore demand data requests satisfied by the LLC and not found in a sibling coreoffcore_response.demand_data.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x203Offcore demand data requests satisfied by the LLC and HIT in a sibling coreoffcore_response.demand_data.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x403Offcore demand data requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.demand_data.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x703Offcore demand data requests satisfied by the LLCoffcore_response.demand_data.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4703Offcore demand data requests satisfied by the LLC or local DRAMoffcore_response.demand_data.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1803Offcore demand data requests satisfied by a remote cacheoffcore_response.demand_data.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3803Offcore demand data requests satisfied by a remote cache or remote DRAMoffcore_response.demand_data.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1003Offcore demand data requests that HIT in a remote cacheoffcore_response.demand_data.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x803Offcore demand data requests that HITM in a remote cacheoffcore_response.demand_data_rd.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F01Offcore demand data reads satisfied by any cache or DRAMoffcore_response.demand_data_rd.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF01All offcore demand data readsoffcore_response.demand_data_rd.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8001Offcore demand data reads satisfied by the IO, CSR, MMIO unitoffcore_response.demand_data_rd.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x101Offcore demand data reads satisfied by the LLC and not found in a sibling coreoffcore_response.demand_data_rd.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x201Offcore demand data reads satisfied by the LLC and HIT in a sibling coreoffcore_response.demand_data_rd.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x401Offcore demand data reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.demand_data_rd.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x701Offcore demand data reads satisfied by the LLCoffcore_response.demand_data_rd.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4701Offcore demand data reads satisfied by the LLC or local DRAMoffcore_response.demand_data_rd.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1801Offcore demand data reads satisfied by a remote cacheoffcore_response.demand_data_rd.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3801Offcore demand data reads satisfied by a remote cache or remote DRAMoffcore_response.demand_data_rd.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1001Offcore demand data reads that HIT in a remote cacheoffcore_response.demand_data_rd.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x801Offcore demand data reads that HITM in a remote cacheoffcore_response.demand_ifetch.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F04Offcore demand code reads satisfied by any cache or DRAMoffcore_response.demand_ifetch.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF04All offcore demand code readsoffcore_response.demand_ifetch.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8004Offcore demand code reads satisfied by the IO, CSR, MMIO unitoffcore_response.demand_ifetch.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x104Offcore demand code reads satisfied by the LLC and not found in a sibling coreoffcore_response.demand_ifetch.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x204Offcore demand code reads satisfied by the LLC and HIT in a sibling coreoffcore_response.demand_ifetch.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x404Offcore demand code reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.demand_ifetch.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x704Offcore demand code reads satisfied by the LLCoffcore_response.demand_ifetch.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4704Offcore demand code reads satisfied by the LLC or local DRAMoffcore_response.demand_ifetch.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1804Offcore demand code reads satisfied by a remote cacheoffcore_response.demand_ifetch.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3804Offcore demand code reads satisfied by a remote cache or remote DRAMoffcore_response.demand_ifetch.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1004Offcore demand code reads that HIT in a remote cacheoffcore_response.demand_ifetch.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x804Offcore demand code reads that HITM in a remote cacheoffcore_response.demand_rfo.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F02Offcore demand RFO requests satisfied by any cache or DRAMoffcore_response.demand_rfo.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF02All offcore demand RFO requestsoffcore_response.demand_rfo.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8002Offcore demand RFO requests satisfied by the IO, CSR, MMIO unitoffcore_response.demand_rfo.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x102Offcore demand RFO requests satisfied by the LLC and not found in a sibling coreoffcore_response.demand_rfo.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x202Offcore demand RFO requests satisfied by the LLC and HIT in a sibling coreoffcore_response.demand_rfo.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x402Offcore demand RFO requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.demand_rfo.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x702Offcore demand RFO requests satisfied by the LLCoffcore_response.demand_rfo.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4702Offcore demand RFO requests satisfied by the LLC or local DRAMoffcore_response.demand_rfo.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1802Offcore demand RFO requests satisfied by a remote cacheoffcore_response.demand_rfo.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3802Offcore demand RFO requests satisfied by a remote cache or remote DRAMoffcore_response.demand_rfo.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1002Offcore demand RFO requests that HIT in a remote cacheoffcore_response.demand_rfo.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x802Offcore demand RFO requests that HITM in a remote cacheoffcore_response.other.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F80Offcore other requests satisfied by any cache or DRAMoffcore_response.other.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF80All offcore other requestsoffcore_response.other.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8080Offcore other requests satisfied by the IO, CSR, MMIO unitoffcore_response.other.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x180Offcore other requests satisfied by the LLC and not found in a sibling coreoffcore_response.other.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x280Offcore other requests satisfied by the LLC and HIT in a sibling coreoffcore_response.other.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x480Offcore other requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.other.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x780Offcore other requests satisfied by the LLCoffcore_response.other.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4780Offcore other requests satisfied by the LLC or local DRAMoffcore_response.other.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1880Offcore other requests satisfied by a remote cacheoffcore_response.other.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3880Offcore other requests satisfied by a remote cache or remote DRAMoffcore_response.other.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1080Offcore other requests that HIT in a remote cacheoffcore_response.other.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x880Offcore other requests that HITM in a remote cacheoffcore_response.pf_data.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F30Offcore prefetch data requests satisfied by any cache or DRAMoffcore_response.pf_data.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF30All offcore prefetch data requestsoffcore_response.pf_data.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8030Offcore prefetch data requests satisfied by the IO, CSR, MMIO unitoffcore_response.pf_data.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x130Offcore prefetch data requests satisfied by the LLC and not found in a sibling coreoffcore_response.pf_data.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x230Offcore prefetch data requests satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_data.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x430Offcore prefetch data requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_data.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x730Offcore prefetch data requests satisfied by the LLCoffcore_response.pf_data.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4730Offcore prefetch data requests satisfied by the LLC or local DRAMoffcore_response.pf_data.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1830Offcore prefetch data requests satisfied by a remote cacheoffcore_response.pf_data.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3830Offcore prefetch data requests satisfied by a remote cache or remote DRAMoffcore_response.pf_data.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1030Offcore prefetch data requests that HIT in a remote cacheoffcore_response.pf_data.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x830Offcore prefetch data requests that HITM in a remote cacheoffcore_response.pf_data_rd.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F10Offcore prefetch data reads satisfied by any cache or DRAMoffcore_response.pf_data_rd.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF10All offcore prefetch data readsoffcore_response.pf_data_rd.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8010Offcore prefetch data reads satisfied by the IO, CSR, MMIO unitoffcore_response.pf_data_rd.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x110Offcore prefetch data reads satisfied by the LLC and not found in a sibling coreoffcore_response.pf_data_rd.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x210Offcore prefetch data reads satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_data_rd.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x410Offcore prefetch data reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_data_rd.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x710Offcore prefetch data reads satisfied by the LLCoffcore_response.pf_data_rd.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4710Offcore prefetch data reads satisfied by the LLC or local DRAMoffcore_response.pf_data_rd.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1810Offcore prefetch data reads satisfied by a remote cacheoffcore_response.pf_data_rd.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3810Offcore prefetch data reads satisfied by a remote cache or remote DRAMoffcore_response.pf_data_rd.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1010Offcore prefetch data reads that HIT in a remote cacheoffcore_response.pf_data_rd.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x810Offcore prefetch data reads that HITM in a remote cacheoffcore_response.pf_ifetch.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F40Offcore prefetch code reads satisfied by any cache or DRAMoffcore_response.pf_ifetch.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF40All offcore prefetch code readsoffcore_response.pf_ifetch.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8040Offcore prefetch code reads satisfied by the IO, CSR, MMIO unitoffcore_response.pf_ifetch.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x140Offcore prefetch code reads satisfied by the LLC and not found in a sibling coreoffcore_response.pf_ifetch.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x240Offcore prefetch code reads satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_ifetch.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x440Offcore prefetch code reads satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_ifetch.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x740Offcore prefetch code reads satisfied by the LLCoffcore_response.pf_ifetch.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4740Offcore prefetch code reads satisfied by the LLC or local DRAMoffcore_response.pf_ifetch.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1840Offcore prefetch code reads satisfied by a remote cacheoffcore_response.pf_ifetch.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3840Offcore prefetch code reads satisfied by a remote cache or remote DRAMoffcore_response.pf_ifetch.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1040Offcore prefetch code reads that HIT in a remote cacheoffcore_response.pf_ifetch.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x840Offcore prefetch code reads that HITM in a remote cacheoffcore_response.pf_rfo.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F20Offcore prefetch RFO requests satisfied by any cache or DRAMoffcore_response.pf_rfo.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF20All offcore prefetch RFO requestsoffcore_response.pf_rfo.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8020Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unitoffcore_response.pf_rfo.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x120Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling coreoffcore_response.pf_rfo.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x220Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling coreoffcore_response.pf_rfo.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x420Offcore prefetch RFO requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.pf_rfo.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x720Offcore prefetch RFO requests satisfied by the LLCoffcore_response.pf_rfo.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4720Offcore prefetch RFO requests satisfied by the LLC or local DRAMoffcore_response.pf_rfo.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1820Offcore prefetch RFO requests satisfied by a remote cacheoffcore_response.pf_rfo.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3820Offcore prefetch RFO requests satisfied by a remote cache or remote DRAMoffcore_response.pf_rfo.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1020Offcore prefetch RFO requests that HIT in a remote cacheoffcore_response.pf_rfo.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x820Offcore prefetch RFO requests that HITM in a remote cacheoffcore_response.prefetch.any_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F70Offcore prefetch requests satisfied by any cache or DRAMoffcore_response.prefetch.any_locationevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF70All offcore prefetch requestsoffcore_response.prefetch.io_csr_mmioevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8070Offcore prefetch requests satisfied by the IO, CSR, MMIO unitoffcore_response.prefetch.llc_hit_no_other_coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x170Offcore prefetch requests satisfied by the LLC and not found in a sibling coreoffcore_response.prefetch.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x270Offcore prefetch requests satisfied by the LLC and HIT in a sibling coreoffcore_response.prefetch.llc_hit_other_core_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x470Offcore prefetch requests satisfied by the LLC  and HITM in a sibling coreoffcore_response.prefetch.local_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x770Offcore prefetch requests satisfied by the LLCoffcore_response.prefetch.local_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4770Offcore prefetch requests satisfied by the LLC or local DRAMoffcore_response.prefetch.remote_cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1870Offcore prefetch requests satisfied by a remote cacheoffcore_response.prefetch.remote_cache_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3870Offcore prefetch requests satisfied by a remote cache or remote DRAMoffcore_response.prefetch.remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1070Offcore prefetch requests that HIT in a remote cacheoffcore_response.prefetch.remote_cache_hitmevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x870Offcore prefetch requests that HITM in a remote cacheevent=0xf4,period=2000000,umask=0x10Super Queue lock splits across a cache linestore_blocks.at_retevent=0x6,period=200000,umask=0x4Loads delayed with at-Retirement block codestore_blocks.l1d_blockevent=0x6,period=200000,umask=0x8Cacheable loads delayed with L1D block codefp_assist.allevent=0xf7,period=20000,umask=0x1X87 Floating point assists (Precise Event)fp_assist.inputevent=0xf7,period=20000,umask=0x4X87 Floating poiint assists for invalid input value (Precise Event)fp_assist.outputevent=0xf7,period=20000,umask=0x2X87 Floating point assists for invalid output value (Precise Event)fp_comp_ops_exe.mmxMMX Uopsfp_comp_ops_exe.sse2_integerevent=0x10,period=2000000,umask=0x8SSE2 integer Uopsfp_comp_ops_exe.sse_double_precisionevent=0x10,period=2000000,umask=0x80SSE* FP double precision Uopsfp_comp_ops_exe.sse_fpevent=0x10,period=2000000,umask=0x4SSE and SSE2 FP Uopsfp_comp_ops_exe.sse_fp_packedevent=0x10,period=2000000,umask=0x10SSE FP packed Uopsfp_comp_ops_exe.sse_fp_scalarevent=0x10,period=2000000,umask=0x20SSE FP scalar Uopsfp_comp_ops_exe.sse_single_precisionevent=0x10,period=2000000,umask=0x40SSE* FP single precision UopsComputational floating-point operations executedfp_mmx_trans.anyevent=0xcc,period=2000000,umask=0x3All Floating Point to and from MMX transitionsfp_mmx_trans.to_fpevent=0xcc,period=2000000,umask=0x1Transitions from MMX to Floating Point instructionsfp_mmx_trans.to_mmxevent=0xcc,period=2000000,umask=0x2Transitions from Floating Point to MMX instructionssimd_int_128.packevent=0x12,period=200000,umask=0x4128 bit SIMD integer pack operationssimd_int_128.packed_arithevent=0x12,period=200000,umask=0x20128 bit SIMD integer arithmetic operationssimd_int_128.packed_logicalevent=0x12,period=200000,umask=0x10128 bit SIMD integer logical operationssimd_int_128.packed_mpyevent=0x12,period=200000,umask=0x1128 bit SIMD integer multiply operationssimd_int_128.packed_shiftevent=0x12,period=200000,umask=0x2128 bit SIMD integer shift operationssimd_int_128.shuffle_moveevent=0x12,period=200000,umask=0x40128 bit SIMD integer shuffle/move operationssimd_int_128.unpackevent=0x12,period=200000,umask=0x8128 bit SIMD integer unpack operationssimd_int_64.packevent=0xfd,period=200000,umask=0x4SIMD integer 64 bit pack operationssimd_int_64.packed_arithevent=0xfd,period=200000,umask=0x20SIMD integer 64 bit arithmetic operationssimd_int_64.packed_logicalevent=0xfd,period=200000,umask=0x10SIMD integer 64 bit logical operationssimd_int_64.packed_mpyevent=0xfd,period=200000,umask=0x1SIMD integer 64 bit packed multiply operationssimd_int_64.packed_shiftevent=0xfd,period=200000,umask=0x2SIMD integer 64 bit shift operationssimd_int_64.shuffle_moveevent=0xfd,period=200000,umask=0x40SIMD integer 64 bit shuffle/move operationssimd_int_64.unpackevent=0xfd,period=200000,umask=0x8SIMD integer 64 bit unpack operationsmacro_insts.decodedevent=0xd0,period=2000000,umask=0x1Instructions decodedmacro_insts.fusions_decodedevent=0xa6,period=2000000,umask=0x1Macro-fused instructions decodedtwo_uop_insts_decodedevent=0x19,period=2000000,umask=0x1Two Uop instructions decodedoffcore_response.any_data.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6011Offcore data reads satisfied by any DRAMoffcore_response.any_data.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF811Offcore data reads that missed the LLCoffcore_response.any_data.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4011Offcore data reads satisfied by the local DRAMoffcore_response.any_data.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2011Offcore data reads satisfied by a remote DRAMoffcore_response.any_ifetch.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6044Offcore code reads satisfied by any DRAMoffcore_response.any_ifetch.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF844Offcore code reads that missed the LLCoffcore_response.any_ifetch.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4044Offcore code reads satisfied by the local DRAMoffcore_response.any_ifetch.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2044Offcore code reads satisfied by a remote DRAMoffcore_response.any_request.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x60FFOffcore requests satisfied by any DRAMoffcore_response.any_request.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF8FFOffcore requests that missed the LLCoffcore_response.any_request.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x40FFOffcore requests satisfied by the local DRAMoffcore_response.any_request.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x20FFOffcore requests satisfied by a remote DRAMoffcore_response.any_rfo.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6022Offcore RFO requests satisfied by any DRAMoffcore_response.any_rfo.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF822Offcore RFO requests that missed the LLCoffcore_response.any_rfo.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4022Offcore RFO requests satisfied by the local DRAMoffcore_response.any_rfo.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2022Offcore RFO requests satisfied by a remote DRAMoffcore_response.corewb.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6008Offcore writebacks to any DRAMoffcore_response.corewb.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF808Offcore writebacks that missed the LLCoffcore_response.corewb.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4008Offcore writebacks to the local DRAMoffcore_response.corewb.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2008Offcore writebacks to a remote DRAMoffcore_response.data_ifetch.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6077Offcore code or data read requests satisfied by any DRAMoffcore_response.data_ifetch.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF877Offcore code or data read requests that missed the LLCoffcore_response.data_ifetch.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4077Offcore code or data read requests satisfied by the local DRAMoffcore_response.data_ifetch.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2077Offcore code or data read requests satisfied by a remote DRAMoffcore_response.data_in.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6033Offcore request = all data, response = any DRAMoffcore_response.data_in.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF833Offcore request = all data, response = any LLC missoffcore_response.data_in.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4033Offcore data reads, RFO's and prefetches statisfied by the local DRAMoffcore_response.data_in.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2033Offcore data reads, RFO's and prefetches statisfied by the remote DRAMoffcore_response.demand_data.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6003Offcore demand data requests satisfied by any DRAMoffcore_response.demand_data.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF803Offcore demand data requests that missed the LLCoffcore_response.demand_data.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4003Offcore demand data requests satisfied by the local DRAMoffcore_response.demand_data.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2003Offcore demand data requests satisfied by a remote DRAMoffcore_response.demand_data_rd.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6001Offcore demand data reads satisfied by any DRAMoffcore_response.demand_data_rd.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF801Offcore demand data reads that missed the LLCoffcore_response.demand_data_rd.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4001Offcore demand data reads satisfied by the local DRAMoffcore_response.demand_data_rd.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2001Offcore demand data reads satisfied by a remote DRAMoffcore_response.demand_ifetch.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6004Offcore demand code reads satisfied by any DRAMoffcore_response.demand_ifetch.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF804Offcore demand code reads that missed the LLCoffcore_response.demand_ifetch.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4004Offcore demand code reads satisfied by the local DRAMoffcore_response.demand_ifetch.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2004Offcore demand code reads satisfied by a remote DRAMoffcore_response.demand_rfo.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6002Offcore demand RFO requests satisfied by any DRAMoffcore_response.demand_rfo.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF802Offcore demand RFO requests that missed the LLCoffcore_response.demand_rfo.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4002Offcore demand RFO requests satisfied by the local DRAMoffcore_response.demand_rfo.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2002Offcore demand RFO requests satisfied by a remote DRAMoffcore_response.other.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6080Offcore other requests satisfied by any DRAMoffcore_response.other.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF880Offcore other requests that missed the LLCoffcore_response.other.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2080Offcore other requests satisfied by a remote DRAMoffcore_response.pf_data.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6030Offcore prefetch data requests satisfied by any DRAMoffcore_response.pf_data.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF830Offcore prefetch data requests that missed the LLCoffcore_response.pf_data.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4030Offcore prefetch data requests satisfied by the local DRAMoffcore_response.pf_data.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2030Offcore prefetch data requests satisfied by a remote DRAMoffcore_response.pf_data_rd.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6010Offcore prefetch data reads satisfied by any DRAMoffcore_response.pf_data_rd.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF810Offcore prefetch data reads that missed the LLCoffcore_response.pf_data_rd.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4010Offcore prefetch data reads satisfied by the local DRAMoffcore_response.pf_data_rd.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2010Offcore prefetch data reads satisfied by a remote DRAMoffcore_response.pf_ifetch.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6040Offcore prefetch code reads satisfied by any DRAMoffcore_response.pf_ifetch.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF840Offcore prefetch code reads that missed the LLCoffcore_response.pf_ifetch.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4040Offcore prefetch code reads satisfied by the local DRAMoffcore_response.pf_ifetch.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2040Offcore prefetch code reads satisfied by a remote DRAMoffcore_response.pf_rfo.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6020Offcore prefetch RFO requests satisfied by any DRAMoffcore_response.pf_rfo.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF820Offcore prefetch RFO requests that missed the LLCoffcore_response.pf_rfo.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4020Offcore prefetch RFO requests satisfied by the local DRAMoffcore_response.pf_rfo.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2020Offcore prefetch RFO requests satisfied by a remote DRAMoffcore_response.prefetch.any_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6070Offcore prefetch requests satisfied by any DRAMoffcore_response.prefetch.any_llc_missevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xF870Offcore prefetch requests that missed the LLCoffcore_response.prefetch.local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4070Offcore prefetch requests satisfied by the local DRAMoffcore_response.prefetch.remote_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2070Offcore prefetch requests satisfied by a remote DRAMes_reg_renamesevent=0xd5,period=2000000,umask=0x1ES segment renamesio_transactionsevent=0x6c,period=2000000,umask=0x1I/O transactionsl1i.cycles_stalledevent=0x80,period=2000000,umask=0x4L1I instruction fetch stall cyclesl1i.hitsevent=0x80,period=2000000,umask=0x1L1I instruction fetch hitsl1i.missesevent=0x80,period=2000000,umask=0x2L1I instruction fetch missesl1i.readsevent=0x80,period=2000000,umask=0x3L1I Instruction fetcheslarge_itlb.hitLarge ITLB hitload_dispatch.anyevent=0x13,period=2000000,umask=0x7All loads dispatchedload_dispatch.mobevent=0x13,period=2000000,umask=0x4Loads dispatched from the MOBload_dispatch.rsLoads dispatched that bypass the MOBload_dispatch.rs_delayedevent=0x13,period=2000000,umask=0x2Loads dispatched from stage 305partial_address_aliasevent=0x7,period=200000,umask=0x1False dependencies due to partial address aliasingsb_drain.anyevent=0x4,period=200000,umask=0x7All Store buffer stall cyclesseg_rename_stallsevent=0xd4,period=2000000,umask=0x1Segment rename stall cyclessnoop_response.hitevent=0xb8,period=100000,umask=0x1Thread responded HIT to snoopsnoop_response.hiteevent=0xb8,period=100000,umask=0x2Thread responded HITE to snoopsnoop_response.hitmevent=0xb8,period=100000,umask=0x4Thread responded HITM to snoopsq_full_stall_cyclesevent=0xf6,period=2000000,umask=0x1Super Queue full stall cyclesarith.cycles_div_busyarith.divevent=0x14,cmask=1,edge=1,inv=1,period=2000000,umask=0x1Divide Operations executedarith.mulevent=0x14,period=2000000,umask=0x2baclear.bad_targetevent=0xe6,period=2000000,umask=0x2BACLEAR asserted with bad target addressbaclear.clearBACLEAR asserted, regardless of causebaclear_force_iqevent=0xa7,period=2000000,umask=0x1Instruction queue forced BACLEARbpu_clears.earlyevent=0xe8,period=2000000,umask=0x1Early Branch Prediciton Unit clearsbpu_clears.lateevent=0xe8,period=2000000,umask=0x2Late Branch Prediction Unit clearsbpu_missed_call_retevent=0xe5,period=2000000,umask=0x1Branch prediction unit missed call or returnbr_inst_exec.anyevent=0x88,period=200000,umask=0x7fBranch instructions executedbr_inst_exec.condevent=0x88,period=200000,umask=0x1Conditional branch instructions executedbr_inst_exec.directevent=0x88,period=200000,umask=0x2Unconditional branches executedbr_inst_exec.direct_near_callevent=0x88,period=20000,umask=0x10Unconditional call branches executedbr_inst_exec.indirect_near_callevent=0x88,period=20000,umask=0x20Indirect call branches executedbr_inst_exec.indirect_non_callevent=0x88,period=20000,umask=0x4Indirect non call branches executedbr_inst_exec.near_callsevent=0x88,period=20000,umask=0x30Call branches executedbr_inst_exec.non_callsevent=0x88,period=200000,umask=0x7All non call branches executedbr_inst_exec.return_nearevent=0x88,period=20000,umask=0x8Indirect return branches executedbr_inst_exec.takenevent=0x88,period=200000,umask=0x40Taken branches executedevent=0xc4,period=200000,umask=0x4Retired branch instructions (Precise Event)event=0xc4,period=200000,umask=0x1Retired conditional branch instructions (Precise Event)event=0xc4,period=20000,umask=0x2Retired near call instructions (Precise Event)br_misp_exec.anyevent=0x89,period=20000,umask=0x7fMispredicted branches executedbr_misp_exec.condevent=0x89,period=20000,umask=0x1Mispredicted conditional branches executedbr_misp_exec.directevent=0x89,period=20000,umask=0x2Mispredicted unconditional branches executedbr_misp_exec.direct_near_callevent=0x89,period=2000,umask=0x10Mispredicted non call branches executedbr_misp_exec.indirect_near_callevent=0x89,period=2000,umask=0x20Mispredicted indirect call branches executedbr_misp_exec.indirect_non_callevent=0x89,period=2000,umask=0x4Mispredicted indirect non call branches executedbr_misp_exec.near_callsevent=0x89,period=2000,umask=0x30Mispredicted call branches executedbr_misp_exec.non_callsevent=0x89,period=20000,umask=0x7br_misp_exec.return_nearevent=0x89,period=2000,umask=0x8Mispredicted return branches executedbr_misp_exec.takenevent=0x89,period=20000,umask=0x40Mispredicted taken branches executedevent=0xc5,period=2000,umask=0x2Mispredicted near retired calls (Precise Event)event=0,period=2000000,umask=0x0Reference cycles when thread is not halted (fixed counter)cpu_clk_unhalted.ref_pevent=0x3c,period=100000,umask=0x1Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)Cycles when thread is not halted (fixed counter)Cycles when thread is not halted (programmable counter)cpu_clk_unhalted.total_cyclesevent=0x3c,cmask=2,inv=1,period=2000000,umask=0x0Total CPU cyclesild_stall.anyevent=0x87,period=2000000,umask=0xfAny Instruction Length Decoder stall cyclesevent=0x87,period=2000000,umask=0x4Instruction Queue full stall cyclesLength Change Prefix stall cyclesild_stall.mruStall cycles due to BPU MRU bypassild_stall.regenevent=0x87,period=2000000,umask=0x8Regen stall cyclesinst_decoded.dec0event=0x18,period=2000000,umask=0x1Instructions that must be decoded by decoder 0inst_queue_writesevent=0x17,period=2000000,umask=0x1Instructions written to instruction queueinst_queue_write_cyclesevent=0x1e,period=2000000,umask=0x1Cycles instructions are written to the instruction queueInstructions retired (fixed counter)event=0xc0,period=2000000,umask=0x1Instructions retired (Programmable counter and Precise Event) (Precise event)inst_retired.mmxevent=0xc0,period=2000000,umask=0x4Retired MMX instructions (Precise Event)inst_retired.total_cyclesevent=0xc0,cmask=16,inv=1,period=2000000,umask=0x1Total cycles (Precise Event)inst_retired.total_cycles_psevent=0xc0,period=2000000,umask=0x2Retired floating-point operations (Precise Event)load_hit_preevent=0x4c,period=200000,umask=0x1Load operations conflicting with software prefetcheslsd.activeevent=0xa8,cmask=1,period=2000000,umask=0x1Cycles when uops were delivered by the LSDlsd.inactiveevent=0xa8,cmask=1,inv=1,period=2000000,umask=0x1Cycles no uops were delivered by the LSDlsd_overflowevent=0x20,period=2000000,umask=0x1Loops that can't stream from the instruction queueevent=0xc3,period=20000,umask=0x1Cycles machine clear assertedmachine_clears.mem_orderevent=0xc3,period=20000,umask=0x2Execution pipeline restart due to Memory ordering conflictsevent=0xc3,period=20000,umask=0x4rat_stalls.anyevent=0xd2,period=2000000,umask=0xfAll RAT stall cyclesrat_stalls.flagsevent=0xd2,period=2000000,umask=0x1Flag stall cyclesrat_stalls.registersevent=0xd2,period=2000000,umask=0x2Partial register stall cyclesrat_stalls.rob_read_portevent=0xd2,period=2000000,umask=0x4ROB read port stalls cyclesrat_stalls.scoreboardevent=0xd2,period=2000000,umask=0x8Scoreboard stall cyclesevent=0xa2,period=2000000,umask=0x1Resource related stall cyclesresource_stalls.fpcwevent=0xa2,period=2000000,umask=0x20FPU control word write stall cyclesresource_stalls.loadevent=0xa2,period=2000000,umask=0x2Load buffer stall cyclesresource_stalls.mxcsrevent=0xa2,period=2000000,umask=0x40MXCSR rename stall cyclesresource_stalls.otherevent=0xa2,period=2000000,umask=0x80Other Resource related stall cyclesresource_stalls.rob_fullevent=0xa2,period=2000000,umask=0x10ROB full stall cyclesresource_stalls.rs_fullevent=0xa2,period=2000000,umask=0x4Reservation Station full stall cyclesresource_stalls.storeevent=0xa2,period=2000000,umask=0x8Store buffer stall cyclesssex_uops_retired.packed_doubleevent=0xc7,period=200000,umask=0x4SIMD Packed-Double Uops retired (Precise Event)ssex_uops_retired.packed_singleevent=0xc7,period=200000,umask=0x1SIMD Packed-Single Uops retired (Precise Event)ssex_uops_retired.scalar_doubleevent=0xc7,period=200000,umask=0x8SIMD Scalar-Double Uops retired (Precise Event)ssex_uops_retired.scalar_singleevent=0xc7,period=200000,umask=0x2SIMD Scalar-Single Uops retired (Precise Event)ssex_uops_retired.vector_integerevent=0xc7,period=200000,umask=0x10SIMD Vector Integer Uops retired (Precise Event)uops_decoded.esp_foldingevent=0xd1,period=2000000,umask=0x4Stack pointer instructions decodeduops_decoded.esp_syncevent=0xd1,period=2000000,umask=0x8Stack pointer sync operationsuops_decoded.ms_cycles_activeevent=0xd1,cmask=1,period=2000000,umask=0x2Uops decoded by Microcode Sequenceruops_decoded.stall_cyclesevent=0xd1,cmask=1,inv=1,period=2000000,umask=0x1Cycles no Uops are decodeduops_executed.core_active_cyclesevent=0xb1,any=1,cmask=1,period=2000000,umask=0x3fCycles Uops executed on any port (core count)uops_executed.core_active_cycles_no_port5event=0xb1,any=1,cmask=1,period=2000000,umask=0x1fCycles Uops executed on ports 0-4 (core count)uops_executed.core_stall_countevent=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3fUops executed on any port (core count)uops_executed.core_stall_count_no_port5event=0xb1,any=1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1fUops executed on ports 0-4 (core count)uops_executed.core_stall_cyclesevent=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x3fCycles no Uops issued on any port (core count)uops_executed.core_stall_cycles_no_port5event=0xb1,any=1,cmask=1,inv=1,period=2000000,umask=0x1fCycles no Uops issued on ports 0-4 (core count)uops_executed.port0event=0xb1,period=2000000,umask=0x1Uops executed on port 0uops_executed.port015event=0xb1,period=2000000,umask=0x40Uops issued on ports 0, 1 or 5uops_executed.port015_stall_cyclesevent=0xb1,cmask=1,inv=1,period=2000000,umask=0x40Cycles no Uops issued on ports 0, 1 or 5uops_executed.port1event=0xb1,period=2000000,umask=0x2Uops executed on port 1uops_executed.port234_coreevent=0xb1,any=1,period=2000000,umask=0x80Uops issued on ports 2, 3 or 4uops_executed.port2_coreevent=0xb1,any=1,period=2000000,umask=0x4Uops executed on port 2 (core count)uops_executed.port3_coreevent=0xb1,any=1,period=2000000,umask=0x8Uops executed on port 3 (core count)uops_executed.port4_coreevent=0xb1,any=1,period=2000000,umask=0x10Uops executed on port 4 (core count)uops_executed.port5event=0xb1,period=2000000,umask=0x20Uops executed on port 5event=0xe,period=2000000,umask=0x1Uops issuedevent=0xe,any=1,cmask=1,inv=1,period=2000000,umask=0x1Cycles no Uops were issued on any threaduops_issued.cycles_all_threadsevent=0xe,any=1,cmask=1,period=2000000,umask=0x1Cycles Uops were issued on either threaduops_issued.fusedevent=0xe,period=2000000,umask=0x2Fused Uops issuedevent=0xe,cmask=1,inv=1,period=2000000,umask=0x1Cycles no Uops were issueduops_retired.active_cyclesevent=0xc2,cmask=1,period=2000000,umask=0x1Cycles Uops are being retired (Precise event)event=0xc2,period=2000000,umask=0x1Uops retired (Precise Event)uops_retired.macro_fusedevent=0xc2,period=2000000,umask=0x4Macro-fused Uops retired (Precise Event)event=0xc2,period=2000000,umask=0x2Retirement slots used (Precise Event)event=0xc2,cmask=1,inv=1,period=2000000,umask=0x1Cycles Uops are not retiring (Precise Event)event=0xc2,cmask=16,inv=1,period=2000000,umask=0x1Total cycles using precise uop retired event (Precise Event)uop_unfusionevent=0xdb,period=2000000,umask=0x1Uop unfusions due to FP exceptionsdtlb_load_misses.anyevent=0x8,period=200000,umask=0x1DTLB load missesdtlb_load_misses.pde_missevent=0x8,period=200000,umask=0x20DTLB load miss caused by low part of addressevent=0x8,period=2000000,umask=0x10DTLB second level hitevent=0x8,period=200000,umask=0x2DTLB load miss page walks completedtlb_misses.anyevent=0x49,period=200000,umask=0x1DTLB missesdtlb_misses.stlb_hitevent=0x49,period=200000,umask=0x10DTLB first level misses but second level hitdtlb_misses.walk_completedevent=0x49,period=200000,umask=0x2DTLB miss page walksitlb_flushevent=0xae,period=2000000,umask=0x1itlb_misses.anyevent=0x85,period=200000,umask=0x1ITLB missevent=0x85,period=200000,umask=0x2ITLB miss page walksitlb_miss_retiredevent=0xc8,period=200000,umask=0x20Retired instructions that missed the ITLB (Precise Event)event=0xcb,period=200000,umask=0x80Retired loads that miss the DTLB (Precise Event)mem_store_retired.dtlb_missRetired stores that miss the DTLB (Precise Event)Offcore data reads, RFO's and prefetches that HIT in a remote cache BACLEAR asserted, regardless of cause Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replaceNumber of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetchNumber of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructionsL1D miss outstandings duration in cyclesCounts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request typeCounts duration of L1D miss outstanding in cyclesevent=0xf1,period=100003,umask=0x1fCounts the number of L2 cache lines filling the L2. Counting does not cover rejectsl2_lines_out.non_silentevent=0xf2,period=200003,umask=0x2Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3l2_lines_out.silentevent=0xf2,period=200003,umask=0x1Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded eventl2_lines_out.useless_hwpfevent=0xf2,period=200003,umask=0x4Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cachel2_lines_out.useless_prefThis event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPFCounts the total number of L2 code requestsCounts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are countedRequests from the L1/L2/L3 hardware prefetchers or Load software prefetchesCounts the total number of requests from the L2 hardware prefetchersCounts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetchesCounts L2 cache hits when fetching instructions, code readsCounts L2 cache misses when fetching instructionsCounts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are countedevent=0x24,period=200003,umask=0xd8Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cacheCounts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cacheevent=0x24,period=200003,umask=0x38Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cacheCounts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cacheCounts the RFO (Read-for-Ownership) requests that hit L2 cacheCounts the RFO (Read-for-Ownership) requests that miss L2 cacheCounts L2 writebacks that access L2 cacheCore-originated cacheable demand requests missed L3  Spec update: SKL057Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3  Spec update: SKL057Core-originated cacheable demand requests that refer to L3  Spec update: SKL057Counts core-originated cacheable requests to the  L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2.  It does not include all accesses to the L3  Spec update: SKL057mem_inst_retired.all_loadsAll retired load instructions  Supports address when precise (Precise event)mem_inst_retired.all_storesAll retired store instructions  Supports address when precise (Precise event)mem_inst_retired.anyevent=0xd0,period=2000003,umask=0x83All retired memory instructions  Supports address when precise (Precise event)Counts all retired memory instructions - loads and stores  Supports address when precise (Precise event)mem_inst_retired.lock_loadsRetired load instructions with locked access  Supports address when precise (Precise event)mem_inst_retired.split_loadsRetired load instructions that split across a cacheline boundary  Supports address when precise (Precise event)Counts retired load instructions that split across a cacheline boundary  Supports address when precise (Precise event)mem_inst_retired.split_storesRetired store instructions that split across a cacheline boundary  Supports address when precise (Precise event)Counts retired store instructions that split across a cacheline boundary  Supports address when precise (Precise event)mem_inst_retired.stlb_miss_loadsRetired load instructions that miss the STLB  Supports address when precise (Precise event)Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB)  Supports address when precise (Precise event)mem_inst_retired.stlb_miss_storesRetired store instructions that miss the STLB  Supports address when precise (Precise event)Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB)  Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_hitRetired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_hitmRetired load instructions which data sources were HitM responses from shared L3  Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_missRetired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_noneRetired load instructions which data sources were hits in L3 without snoops required  Supports address when precise (Precise event)mem_load_misc_retired.ucevent=0xd4,period=100007,umask=0x4Retired instructions with at least 1 uncacheable load or lock  Supports address when precise (Precise event)mem_load_retired.fb_hitevent=0xd1,period=100007,umask=0x40Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event)Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready  Supports address when precise (Precise event)mem_load_retired.l1_hitRetired load instructions with L1 cache hits as data sources  Supports address when precise (Precise event)Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source  Supports address when precise (Precise event)mem_load_retired.l1_missRetired load instructions missed L1 cache as data sources  Supports address when precise (Precise event)Counts retired load instructions with at least one uop that missed in the L1 cache  Supports address when precise (Precise event)Retired load instructions with L2 cache hits as data sources  Supports address when precise (Precise event)Retired load instructions missed L2 cache as data sources  Supports address when precise (Precise event)mem_load_retired.l3_hitRetired load instructions with L3 cache hits as data sources  Supports address when precise (Precise event)Counts retired load instructions with at least one uop that hit in the L3 cache  Supports address when precise (Precise event)mem_load_retired.l3_missRetired load instructions missed L3 cache as data sources  Supports address when precise (Precise event)Counts retired load instructions with at least one uop that missed in the L3 cache  Supports address when precise (Precise event)Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request typeCounts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc.Counts both cacheable and non-cacheable code read requestsCounts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncoreCounts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoMCounts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entriesCounts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTSCounts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTSCycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncoreCounts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTSCounts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation)Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncoreCounts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTSOffcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycleCounts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion pointCounts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTSevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10004Counts all demand code readshave any response typeevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C0004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C0004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C0004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C0004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C0004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C0004offcore_response.demand_code_rd.l3_hit.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C0004offcore_response.demand_code_rd.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0080004offcore_response.demand_code_rd.l3_hit_e.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080004offcore_response.demand_code_rd.l3_hit_e.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080004offcore_response.demand_code_rd.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080004offcore_response.demand_code_rd.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080004offcore_response.demand_code_rd.l3_hit_e.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080004offcore_response.demand_code_rd.l3_hit_e.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40080004offcore_response.demand_code_rd.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0040004offcore_response.demand_code_rd.l3_hit_m.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040004offcore_response.demand_code_rd.l3_hit_m.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040004offcore_response.demand_code_rd.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040004offcore_response.demand_code_rd.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040004offcore_response.demand_code_rd.l3_hit_m.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040004offcore_response.demand_code_rd.l3_hit_m.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40040004offcore_response.demand_code_rd.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0100004offcore_response.demand_code_rd.l3_hit_s.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100004offcore_response.demand_code_rd.l3_hit_s.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100004offcore_response.demand_code_rd.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100004offcore_response.demand_code_rd.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100004offcore_response.demand_code_rd.l3_hit_s.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100004offcore_response.demand_code_rd.l3_hit_s.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40100004offcore_response.demand_code_rd.l4_hit_local_l4.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0400004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000400004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400400004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200400004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400004offcore_response.demand_code_rd.l4_hit_local_l4.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40400004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0020004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020004offcore_response.demand_code_rd.supplier_none.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40020004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001Counts demand data readshave any response typeevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C0001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C0001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C0001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C0001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C0001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C0001offcore_response.demand_data_rd.l3_hit.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C0001offcore_response.demand_data_rd.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0080001offcore_response.demand_data_rd.l3_hit_e.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080001offcore_response.demand_data_rd.l3_hit_e.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080001offcore_response.demand_data_rd.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080001offcore_response.demand_data_rd.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080001offcore_response.demand_data_rd.l3_hit_e.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080001offcore_response.demand_data_rd.l3_hit_e.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40080001offcore_response.demand_data_rd.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0040001offcore_response.demand_data_rd.l3_hit_m.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040001offcore_response.demand_data_rd.l3_hit_m.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040001offcore_response.demand_data_rd.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040001offcore_response.demand_data_rd.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040001offcore_response.demand_data_rd.l3_hit_m.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040001offcore_response.demand_data_rd.l3_hit_m.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40040001offcore_response.demand_data_rd.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0100001offcore_response.demand_data_rd.l3_hit_s.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100001offcore_response.demand_data_rd.l3_hit_s.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100001offcore_response.demand_data_rd.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100001offcore_response.demand_data_rd.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100001offcore_response.demand_data_rd.l3_hit_s.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100001offcore_response.demand_data_rd.l3_hit_s.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40100001offcore_response.demand_data_rd.l4_hit_local_l4.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0400001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000400001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400400001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200400001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400001offcore_response.demand_data_rd.l4_hit_local_l4.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40400001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0020001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020001offcore_response.demand_data_rd.supplier_none.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40020001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002Counts all demand data writes (RFOs)have any response typeevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C0002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C0002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C0002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C0002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C0002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C0002offcore_response.demand_rfo.l3_hit.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C0002offcore_response.demand_rfo.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0080002offcore_response.demand_rfo.l3_hit_e.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080002offcore_response.demand_rfo.l3_hit_e.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080002offcore_response.demand_rfo.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080002offcore_response.demand_rfo.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080002offcore_response.demand_rfo.l3_hit_e.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080002offcore_response.demand_rfo.l3_hit_e.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40080002offcore_response.demand_rfo.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0040002offcore_response.demand_rfo.l3_hit_m.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040002offcore_response.demand_rfo.l3_hit_m.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040002offcore_response.demand_rfo.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040002offcore_response.demand_rfo.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040002offcore_response.demand_rfo.l3_hit_m.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040002offcore_response.demand_rfo.l3_hit_m.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40040002offcore_response.demand_rfo.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0100002offcore_response.demand_rfo.l3_hit_s.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100002offcore_response.demand_rfo.l3_hit_s.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100002offcore_response.demand_rfo.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100002offcore_response.demand_rfo.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100002offcore_response.demand_rfo.l3_hit_s.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100002offcore_response.demand_rfo.l3_hit_s.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40100002offcore_response.demand_rfo.l4_hit_local_l4.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0400002offcore_response.demand_rfo.l4_hit_local_l4.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000400002offcore_response.demand_rfo.l4_hit_local_l4.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400400002offcore_response.demand_rfo.l4_hit_local_l4.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200400002offcore_response.demand_rfo.l4_hit_local_l4.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400002offcore_response.demand_rfo.l4_hit_local_l4.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400002offcore_response.demand_rfo.l4_hit_local_l4.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40400002offcore_response.demand_rfo.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0020002offcore_response.demand_rfo.supplier_none.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020002offcore_response.demand_rfo.supplier_none.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020002offcore_response.demand_rfo.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020002offcore_response.demand_rfo.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020002offcore_response.demand_rfo.supplier_none.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020002offcore_response.demand_rfo.supplier_none.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40020002Counts any other requestshave any response typeevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC01C8000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001C8000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001C8000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001C8000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x801C8000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001C8000offcore_response.other.l3_hit.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x401C8000offcore_response.other.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0088000offcore_response.other.l3_hit_e.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000088000offcore_response.other.l3_hit_e.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400088000offcore_response.other.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200088000offcore_response.other.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80088000offcore_response.other.l3_hit_e.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100088000offcore_response.other.l3_hit_e.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40088000offcore_response.other.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0048000offcore_response.other.l3_hit_m.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000048000offcore_response.other.l3_hit_m.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400048000offcore_response.other.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200048000offcore_response.other.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80048000offcore_response.other.l3_hit_m.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100048000offcore_response.other.l3_hit_m.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40048000offcore_response.other.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0108000offcore_response.other.l3_hit_s.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000108000offcore_response.other.l3_hit_s.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400108000offcore_response.other.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200108000offcore_response.other.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80108000offcore_response.other.l3_hit_s.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100108000offcore_response.other.l3_hit_s.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40108000offcore_response.other.l4_hit_local_l4.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0408000offcore_response.other.l4_hit_local_l4.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000408000offcore_response.other.l4_hit_local_l4.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400408000offcore_response.other.l4_hit_local_l4.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200408000offcore_response.other.l4_hit_local_l4.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80408000offcore_response.other.l4_hit_local_l4.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100408000offcore_response.other.l4_hit_local_l4.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40408000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC0028000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x400028000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x200028000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x80028000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x100028000offcore_response.other.supplier_none.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x40028000Number of cache line split locks sent to uncoreCounts the number of cache line split locks sent to the uncoresw_prefetch_access.ntaevent=0x32,period=2000003,umask=0x1Number of PREFETCHNTA instructions executedsw_prefetch_access.prefetchwevent=0x32,period=2000003,umask=0x8Number of PREFETCHW instructions executedsw_prefetch_access.t0event=0x32,period=2000003,umask=0x2Number of PREFETCHT0 instructions executedsw_prefetch_access.t1_t2event=0x32,period=2000003,umask=0x4Number of PREFETCHT1 or PREFETCHT2 instructions executedCounts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retiredCounts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsCounts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retiredCounts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsCounts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retiredCounts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsCounts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retiredCounts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsCounts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retiredCounts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsCounts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retiredCounts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsCounts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1event=0xe6,period=100003,umask=0x1Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymoreThis event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.
Note: Invoking MITE requires two or three cycles delayCounts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cyclesfrontend_retired.any_dsb_missevent=0xc6,period=100007,umask=0x1,frontend=0x1Retired Instructions who experienced DSB miss (Precise event)Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss (Precise event)frontend_retired.dsb_missevent=0xc6,period=100007,umask=0x1,frontend=0x11Retired Instructions who experienced a critical DSB miss (Precise event)Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss (Precise event)frontend_retired.itlb_missevent=0xc6,period=100007,umask=0x1,frontend=0x14Retired Instructions who experienced iTLB true miss (Precise event)Counts retired Instructions that experienced iTLB (Instruction TLB) true miss (Precise event)frontend_retired.l1i_missevent=0xc6,period=100007,umask=0x1,frontend=0x12Retired Instructions who experienced Instruction L1 Cache true miss (Precise event)frontend_retired.l2_missevent=0xc6,period=100007,umask=0x1,frontend=0x13Retired Instructions who experienced Instruction L2 Cache true miss (Precise event)frontend_retired.latency_ge_1event=0xc6,period=100007,umask=0x1,frontend=0x400106Retired instructions after front-end starvation of at least 1 cycle (Must be precise)Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Must be precise)frontend_retired.latency_ge_128event=0xc6,period=100007,umask=0x1,frontend=0x408006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_16event=0xc6,period=100007,umask=0x1,frontend=0x401006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event)Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops (Precise event)frontend_retired.latency_ge_2event=0xc6,period=100007,umask=0x1,frontend=0x400206Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_256event=0xc6,period=100007,umask=0x1,frontend=0x410006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_2_bubbles_ge_1event=0xc6,period=100007,umask=0x1,frontend=0x100206Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall (Precise event)frontend_retired.latency_ge_2_bubbles_ge_2event=0xc6,period=100007,umask=0x1,frontend=0x200206Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_2_bubbles_ge_3event=0xc6,period=100007,umask=0x1,frontend=0x300206Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_32event=0xc6,period=100007,umask=0x1,frontend=0x402006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event)Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops (Precise event)frontend_retired.latency_ge_4event=0xc6,period=100007,umask=0x1,frontend=0x400406Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_512event=0xc6,period=100007,umask=0x1,frontend=0x420006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_64event=0xc6,period=100007,umask=0x1,frontend=0x404006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_8event=0xc6,period=100007,umask=0x1,frontend=0x400806Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event)Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops (Precise event)frontend_retired.stlb_missevent=0xc6,period=100007,umask=0x1,frontend=0x15Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event)Counts retired Instructions that experienced STLB (2nd level TLB) true miss (Precise event)icache_16b.ifdata_stallCycles where a code fetch is stalled due to L1 instruction cache missCycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularityicache_64b.iftag_hitevent=0x83,period=200003,umask=0x1Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularityicache_64b.iftag_missevent=0x83,period=200003,umask=0x2Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularityicache_64b.iftag_stallevent=0x83,period=200003,umask=0x4Cycles where a code fetch is stalled due to L1 instruction cache tag missCounts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQCounts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQCounts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQCounts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQCounts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQCounts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITECounts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQCounts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQCounts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MSCounts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions).  c. Instruction Decode Queue (IDQ) delivers four uopsCounts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3Cycles with less than 2 uops delivered by the front-endCycles with less than 3 uops delivered by the front-endcycle_activity.cycles_l3_missCycles while L3 cache miss demand load is outstandingcycle_activity.stalls_l3_missExecution stalls while L3 cache miss demand load is outstandinghle_retired.aborted_eventsNumber of times an HLE execution aborted due to unfriendly events (such as interrupts)hle_retired.aborted_memhle_retired.aborted_memtypehle_retired.aborted_timerNumber of times an HLE execution aborted due to hardware timer expirationhle_retired.aborted_unfriendlyNumber of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.)Number of times we entered an HLE region. Does not count nested transactionsCounts the number of machine clears due to memory order conflicts  Spec update: SKL089Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer  Spec update: SKL089Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles  Supports address when precise (Must be precise)Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency  Supports address when precise (Must be precise)offcore_requests.l3_miss_demand_data_rdevent=0xb0,period=100003,umask=0x10Demand Data Read requests who miss L3 cacheoffcore_requests_outstanding.cycles_with_l3_miss_demand_data_rdevent=0x60,cmask=1,period=2000003,umask=0x10Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQoffcore_requests_outstanding.l3_miss_demand_data_rdevent=0x60,period=2000003,umask=0x10Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycleoffcore_requests_outstanding.l3_miss_demand_data_rd_ge_6event=0x60,cmask=6,period=2000003,umask=0x10Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C0004offcore_response.demand_code_rd.l3_hit_e.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000080004offcore_response.demand_code_rd.l3_hit_m.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000040004offcore_response.demand_code_rd.l3_hit_s.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000100004offcore_response.demand_code_rd.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC400004offcore_response.demand_code_rd.l3_miss.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C400004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C400004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C400004event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC400004offcore_response.demand_code_rd.l3_miss.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C400004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C400004offcore_response.demand_code_rd.l3_miss.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C400004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4000004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000004offcore_response.demand_code_rd.l3_miss_local_dram.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x44000004offcore_response.demand_code_rd.l4_hit_local_l4.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000400004event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C0001offcore_response.demand_data_rd.l3_hit_e.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000080001offcore_response.demand_data_rd.l3_hit_m.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000040001offcore_response.demand_data_rd.l3_hit_s.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000100001offcore_response.demand_data_rd.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC400001offcore_response.demand_data_rd.l3_miss.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C400001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C400001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C400001event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC400001offcore_response.demand_data_rd.l3_miss.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C400001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C400001offcore_response.demand_data_rd.l3_miss.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C400001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4000001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000001offcore_response.demand_data_rd.l3_miss_local_dram.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x44000001offcore_response.demand_data_rd.l4_hit_local_l4.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000400001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C0002offcore_response.demand_rfo.l3_hit_e.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000080002offcore_response.demand_rfo.l3_hit_m.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000040002offcore_response.demand_rfo.l3_hit_s.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000100002offcore_response.demand_rfo.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC400002offcore_response.demand_rfo.l3_miss.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C400002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C400002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C400002event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC400002offcore_response.demand_rfo.l3_miss.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C400002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C400002offcore_response.demand_rfo.l3_miss.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C400002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2004000002offcore_response.demand_rfo.l3_miss_local_dram.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000002offcore_response.demand_rfo.l3_miss_local_dram.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x44000002offcore_response.demand_rfo.l4_hit_local_l4.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000400002offcore_response.demand_rfo.supplier_none.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000020002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x20001C8000offcore_response.other.l3_hit_e.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000088000offcore_response.other.l3_hit_m.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000048000offcore_response.other.l3_hit_s.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000108000offcore_response.other.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFC408000offcore_response.other.l3_miss.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C408000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C408000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C408000event=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC408000offcore_response.other.l3_miss.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x203C408000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C408000offcore_response.other.l3_miss.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x7C408000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC4008000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x404008000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x204008000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x84008000event=0xb7,period=100003,umask=0x1,offcore_rsp=0x104008000offcore_response.other.l3_miss_local_dram.spl_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x44008000offcore_response.other.l4_hit_local_l4.snoop_non_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000408000rtm_retired.aborted_eventsrtm_retired.aborted_memrtm_retired.aborted_memtypertm_retired.aborted_timerNumber of times an RTM execution aborted due to uncommon conditionsrtm_retired.aborted_unfriendlyNumber of times we entered an RTM region. Does not count nested transactionsUnfriendly TSX abort triggered by a vzeroupper instructiontx_mem.abort_capacityNumber of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writesNumber of hardware interrupts received by the processorCounts the number of hardware interruptions received by the processormemory_disambiguation.history_resetevent=0x9,period=2000003,umask=0x1arith.divider_activeevent=0x14,cmask=1,period=2000003,umask=0x1Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operationsAll (macro) branch instructions retired  Spec update: SKL091Counts all (macro) branch instructions retired  Spec update: SKL091All (macro) branch instructions retired  Spec update: SKL091 (Must be precise)This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired  Spec update: SKL091 (Must be precise)Conditional branch instructions retired  Spec update: SKL091 (Precise event)This event counts conditional branch instructions retired  Spec update: SKL091 (Precise event)br_inst_retired.cond_ntakenNot taken branch instructions retired  Spec update: SKL091This event counts not taken branch instructions retired  Spec update: SKL091Far branch instructions retired  Spec update: SKL091 (Precise event)This event counts far branch instructions retired  Spec update: SKL091 (Precise event)Direct and indirect near call instructions retired  Spec update: SKL091 (Precise event)This event counts both direct and indirect near call instructions retired  Spec update: SKL091 (Precise event)Return instructions retired  Spec update: SKL091 (Precise event)This event counts return instructions retired  Spec update: SKL091 (Precise event)Taken branch instructions retired  Spec update: SKL091 (Precise event)This event counts taken branch instructions retired  Spec update: SKL091 (Precise event)Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct pathevent=0xc5,period=400009,umask=0x2Mispredicted direct and indirect near call instructions retired (Precise event)Counts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect (Precise event)event=0x3c,period=25003,umask=0x2Core crystal clock cycles when this thread is unhalted and the other thread is haltedevent=0x3c,period=25003,umask=0x1Core crystal clock cycles when the thread is unhaltedevent=0x3c,any=1,period=25003,umask=0x1Core crystal clock cycles when at least one thread on the physical core is unhaltedCounts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this casecpu_clk_unhalted.ring0_transevent=0x3c,cmask=1,edge=1,period=100007Counts when there is a transition from ring 1, 2 or 3 to ring 0Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel)Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other eventsevent=0xa3,cmask=16,period=2000003,umask=0x10event=0xa3,cmask=20,period=2000003,umask=0x14exe_activity.1_ports_utilevent=0xa6,period=2000003,umask=0x2Cycles total of 1 uop is executed on all ports and Reservation Station was not emptyCounts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not emptyexe_activity.2_ports_utilevent=0xa6,period=2000003,umask=0x4Cycles total of 2 uops are executed on all ports and Reservation Station was not emptyCounts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not emptyexe_activity.3_ports_utilevent=0xa6,period=2000003,umask=0x8Cycles total of 3 uops are executed on all ports and Reservation Station was not emptyCycles total of 3 uops are executed on all ports and Reservation Station (RS) was not emptyexe_activity.4_ports_utilevent=0xa6,period=2000003,umask=0x10Cycles total of 4 uops are executed on all ports and Reservation Station was not emptyCycles total of 4 uops are executed on all ports and Reservation Station (RS) was not emptyexe_activity.bound_on_storesevent=0xa6,period=2000003,umask=0x40Cycles where the Store Buffer was full and no outstanding loadexe_activity.exe_bound_0_portsevent=0xa6,period=2000003,umask=0x1Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding loadCounts cycles during which no uops were executed on all ports and Reservation Station (RS) was not emptyCounts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunkinst_decoded.decodersevent=0x55,period=2000003,umask=0x1Instruction decoders utilized in a cycleNumber of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructionsCounts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructionsNumber of instructions retired. General Counter - architectural event  Spec update: SKL091, SKL044Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two)  Spec update: SKL091, SKL044inst_retired.nopNumber of all retired NOP instructions  Spec update: SKL091, SKL044 (Precise event)Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution  Spec update: SKL091, SKL044 (Must be precise)A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled  Spec update: SKL091, SKL044 (Must be precise)event=0xc0,cmask=10,inv=1,period=2000003,umask=0x1Number of cycles using always true condition applied to  PEBS instructions retired event  Spec update: SKL091, SKL044 (Must be precise)Number of cycles using an always true condition applied to  PEBS instructions retired event. (inst_ret< 16)  Spec update: SKL091, SKL044 (Must be precise)int_misc.clear_resteer_cyclesevent=0xd,period=2000003,umask=0x80Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear eventsevent=0xd,period=2000003,umask=0x1Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear eventevent=0xd,any=1,period=2000003,umask=0x1Loads blocked due to overlapping with a preceding store that cannot be forwardedCounts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization GuideCounts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliasedDemand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchCounts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructionsCounts the cycles when 4 uops are delivered by the LSD (Loop-stream detector)Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector)Number of uops delivered to the back-end by the LSD(Loop Stream Detector)Counts self-modifying code (SMC) detected, which causes a machine clearother_assists.anyevent=0xc1,period=100003,umask=0x3fNumber of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assistspartial_rat_stalls.scoreboardevent=0x59,period=2000003,umask=0x1Cycles where the pipeline is stalled due to serializing operationsThis event counts cycles during which the microcode scoreboard stalls happenCounts resource-related stall cyclesCounts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-endIncrements whenever there is an update to the LBR arrayIncrements when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECTrob_misc_events.pause_instevent=0xcc,period=2000003,umask=0x40Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL productsCounts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issuesCounts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issuesCounts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7event=0xb1,cmask=1,inv=1,period=2000003,umask=0x2Counts cycles during which no uops were dispatched from the Reservation Station (RS) per threaduops_executed.x87event=0xb1,period=2000003,umask=0x10Counts the number of x87 uops dispatchedCounts the number of x87 uops executedCounts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS)Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current threaduops_issued.vector_width_mismatchevent=0xe,period=2000003,umask=0x2Uops inserted at issue-stage in order to preserve upper bits of vector registersCounts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guideevent=0xc2,period=2000003,umask=0x4Number of macro-fused uops retired. (non precise)Counts the number of macro-fused uops retired. (non precise)Retirement slots usedCounts the retirement slots usedevent=0xc2,cmask=1,inv=1,period=2000003,umask=0x2event=0xc2,cmask=16,inv=1,period=2000003,umask=0x2skl metrics1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))Total pipeline cost of Branch Misprediction related bottlenecks100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) )Mispredictions100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )Mispredictions_SMTBad;BadSpec;BrMispredicts_SMTTotal pipeline cost of (external) Memory Bandwidth related bottlenecks100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (OFFCORE_REQUESTS_BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) Memory_BandwidthMem;MemoryBW;Offcore100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) Memory_Bandwidth_SMTMem;MemoryBW;Offcore_SMTTotal pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (10 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) )Memory_LatencyMem;MemoryLat;Offcore100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (10 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) )Memory_Latency_SMTMem;MemoryLat;Offcore_SMTTotal pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) Memory_Data_TLBs100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\,cmask\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\,cmask\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) Memory_Data_TLBs_SMTMem;MemoryTLB;_SMTTotal pipeline cost of branch related instructions (used for program control-flow including function calls)100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * CPU_CLK_UNHALTED.THREAD))Branching_OverheadRet100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))Branching_Overhead_SMTRet_SMTTotal pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))Big_CodeBigFoot;Fed;Frontend;IcMiss;MemoryTLB100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))Big_Code_SMTBigFoot;Fed;Frontend;IcMiss;MemoryTLB_SMTTotal pipeline cost of instruction fetch bandwidth related bottlenecks100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))Instruction_Fetch_BWFed;FetchBW;Frontend100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\,cmask\=1\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))Instruction_Fetch_BW_SMTFed;FetchBW;Frontend_SMTUOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1) ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREADINST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADSINST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORESAverage number of Uops issued by front-end when it issued somethingUOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\,cmask\=1@Fetch_UpCFed;FetchBWIDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)Total penalty related to DSB (uop cache) misses - subset/see of/the Instruction_Fetch_BW Bottleneck(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))DSB_Misses_CostDSBmiss;Fed(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))DSB_Misses_Cost_SMTDSBmiss;Fed_SMTNumber of Instructions per non-speculative DSB missINST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISSIpDSB_Miss_RetFraction of branches that are non-taken conditionalsBR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHESCond_NTBad;Branches;CodeGen;PGOFraction of branches that are taken conditionals( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN )  / BR_INST_RETIRED.ALL_BRANCHESCond_TKFraction of branches that are CALL or RET( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHESCallRetBad;BranchesFraction of branches that are unconditional (direct or indirect) jumps(BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHESJumpL1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )Average per-core data access bandwidth to the L3 cache [GB / sec]64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_timeL3_Cache_Access_BW1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANYL1 cache true misses per kilo instruction for all demand loads (including speculative)1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANYL1MPKI_Load1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANYFill Buffer (FB) true hits per kilo instructions for retired demand loads1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANYFB_HPKI( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.THREAD )( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )arb@event\=0x80\,umask\=0x2@ / arb@event\=0x80\,umask\=0x2\,cmask\=1@Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic. Unit: uncore_arb Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent trafficCounts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completedLoads that miss the DTLB and hit the STLBCounts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB)dtlb_load_misses.walk_activeevent=0x8,cmask=1,period=100003,umask=0x10Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in SkylakeCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a loadLoad miss in all TLB levels causes a page walk that completes. (All page sizes)Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a faultPage walk completed due to a demand data load to a 1G pageCounts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultPage walk completed due to a demand data load to a 2M/4M pageCounts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultPage walk completed due to a demand data load to a 4K pageCounts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultCounts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in SkylakeCounts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitectureCounts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completedStores that miss the DTLB and hit the STLBStores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)dtlb_store_misses.walk_activeevent=0x49,cmask=1,period=100003,umask=0x10Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in SkylakeCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a storeStore misses in all TLB levels causes a page walk that completes. (All page sizes)Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a faultPage walk completed due to a demand data store to a 1G pageCounts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultPage walk completed due to a demand data store to a 2M/4M pageCounts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultCounts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faultevent=0x49,period=2000003,umask=0x10Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in SkylakeCounts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitectureCounts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request typeCounts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request typeCounts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific)Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completedInstruction fetch requests that miss the ITLB and hit the STLBitlb_misses.walk_activeevent=0x85,cmask=1,period=100003,umask=0x10Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in SkylakeCycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitectureCode miss in all TLB levels causes a page walk that completes. (All page sizes)Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a faultCode miss in all TLB levels causes a page walk that completes. (1G)Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a faultCounts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a faultCounts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a faultCounts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in SkylakeCounts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitectureCounts the number of DTLB flush attempts of the thread-specific entriesCounts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.)Counts the number of request that were not accepted into the L2Q because the L2Q is FULLCounts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.)Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.
Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other eventsCounts the number of request from the L2 that were not accepted into the XQThis event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims)This event counts the total number of L2 cache references and the number of L2 cache misses respectivelyL2 cache requests from this coreThis event counts requests originating from the core that references a cache line in the L2 cacheAll LoadsThis event counts the number of load ops retiredAll StoresThis event counts the number of store ops retiredCross core or cross module hitm (Precise event)This event counts the number of load ops retired that got data from the other core or from the other module (Precise event)Loads missed L1This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be countedLoads hit L2 (Precise event)This event counts the number of load ops retired that hit in the L2 (Precise event)Loads missed L2 (Precise event)This event counts the number of load ops retired that miss in the L2 (Precise event)mem_uops_retired.utlb_missLoads missed UTLBThis event counts the number of load ops retired that had UTLB missCounts any code reads (demand & prefetch) that have any response typeoffcore_response.any_code_rd.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000044Counts any code reads (demand & prefetch) that miss L2offcore_response.any_code_rd.l2_miss.hitm_other_coreevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000000044Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cacheoffcore_response.any_code_rd.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000044Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.any_code_rd.l2_miss.snoop_missevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000044Counts any code reads (demand & prefetch) that miss L2 with a snoop miss responseCounts any data read (demand & prefetch) that have any response typeevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680003091Counts any data read (demand & prefetch) that miss L2Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cacheCounts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.any_data_rd.l2_miss.snoop_missCounts any data read (demand & prefetch) that miss L2 with a snoop miss responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0000018008Counts any request that have any response typeevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1000008008Counts any request that hit in the other module where modified copies were found in other core's L1 cacheevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400008008Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.any_request.l2_miss.snoop_missevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200008008Counts any request that miss L2 with a snoop miss responseCounts any rfo reads (demand & prefetch) that have any response typeevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000022Counts any rfo reads (demand & prefetch) that miss L2Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cacheCounts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.any_rfo.l2_miss.snoop_missCounts any rfo reads (demand & prefetch) that miss L2 with a snoop miss responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000008Counts writeback (modified to exclusive) that miss L2offcore_response.corewb.l2_miss.no_snoop_neededevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0080000008Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related informationCounts demand and DCU prefetch instruction cacheline that have any response typeevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000004Counts demand and DCU prefetch instruction cacheline that miss L2Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_code_rd.l2_miss.snoop_missCounts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss responseCounts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is receivedCounts demand and DCU prefetch data read that have any response typeevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000001Counts demand and DCU prefetch data read that miss L2Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cacheCounts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_data_rd.l2_miss.snoop_missCounts demand and DCU prefetch data read that miss L2 with a snoop miss responseCounts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is receivedevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000002Counts demand and DCU prefetch RFOs that miss L2Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cacheCounts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_rfo.l2_miss.snoop_missCounts demand and DCU prefetch RFOs that miss L2 with a snoop miss responseCounts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is receivedevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000080Counts demand reads of partial cache lines (including UC and WC) that miss L2event=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000100Countsof demand RFO requests to write to partial cache lines that miss L2Counts DCU hardware prefetcher data read that have any response typeevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680002000Counts DCU hardware prefetcher data read that miss L2Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cacheCounts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l1_data_rd.l2_miss.snoop_missCounts DCU hardware prefetcher data read that miss L2 with a snoop miss responseoffcore_response.pf_l2_code_rd.l2_miss.anyevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000040Counts code reads generated by L2 prefetchers that miss L2offcore_response.pf_l2_code_rd.l2_miss.hit_other_core_no_fwdevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0400000040Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_code_rd.l2_miss.snoop_missevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x0200000040Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000010Counts data cacheline reads generated by L2 prefetchers that miss L2Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cacheCounts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_data_rd.l2_miss.snoop_missCounts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680000020Counts RFO requests generated by L2 prefetchers that miss L2Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cacheCounts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_rfo.l2_miss.snoop_missCounts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss responseevent=0xb7,period=100007,umask=0x1,offcore_rsp=0x1680004800Counts streaming store that miss L2rehabq.any_ldAny reissued load uopsThis event counts the number of load uops reissued from Rehabqrehabq.any_stAny reissued store uopsThis event counts the number of store uops reissued from Rehabqrehabq.ld_block_std_notreadyLoads blocked due to store data not readyThis event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right timerehabq.ld_block_st_forwardLoads blocked due to store forward restriction (Precise event)This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise event)rehabq.ld_splitsLoad uops that split cache line boundary (Precise event)This event counts the number of retire loads that experienced cache line boundary splits (Precise event)rehabq.lockUops with lock semanticsThis event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0)rehabq.sta_fullStore address buffer fullThis event counts the number of retired stores that are delayed because there is not a store address buffer availablerehabq.st_splitsStore uops that split cache line boundaryThis event counts the number of retire stores that experienced cache line boundary splitsStalls due to FP assistsThis event counts the number of times that pipeline stalled due to FP operations needing assistsCounts the number of baclearsThe BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.ANY event counts the number of baclears for any type of branchCounts the number of JCC baclearsThe BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclearsCounts the number of RETURN baclearsThe BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end.  The BACLEARS.RETURN event counts the number of RETURN baclearsCounts the number of times a decode restriction reduced the decode throughput due to wrong instruction length predictionThis event counts all instruction fetches, not including most uncacheable
fetchesInstruction fetches from IcacheThis event counts all instruction fetches from the instruction cacheThis event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstandingCounts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative countCounts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort.  The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear.  Background: UOPS are produced by two mechanisms.  Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction.  MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition.  This event is an excellent mechanism for detecting instructions that require the use of MSROM instructionsStalls due to Memory orderingThis event counts the number of times that pipeline was cleared due to memory ordering issuesevent=0x86,period=200003,umask=0x3fCounts the number of branch instructions retired.. (Precise event)ALL_BRANCHES counts the number of any branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Must be precise)CALL counts the number of near CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)FAR counts the number of far branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)IND_CALL counts the number of near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)Counts the number of JCC branch instructions retired (Precise event)JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)Counts the number of near indirect JMP and near indirect CALL branch instructions retired (Precise event)NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)REL_CALL counts the number of near relative CALL branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)RETURN counts the number of near RET branch instructions retired.  Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)Counts the number of taken JCC branch instructions retired (Precise event)TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns (Precise event)ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)Counts the number of mispredicted JCC branch instructions retired (Precise event)JCC counts the number of mispredicted conditional branches (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired (Precise event)NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)RETURN counts the number of mispredicted near RET branch instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)Counts the number of mispredicted taken JCC branch instructions retired (Precise event)TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired.  This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa.  When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REFThis event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to timeThis event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the timeCounts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios.  The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  Divide this event count by core frequency to determine the elapsed time while the core was not in halt state.  This event is architecturally defined and is a designated fixed counter.  CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time.  CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REFCycles the divider is busy.  Does not imply a stall waiting for the dividerCycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty.  The divide instruction is one of the longest latency instructions in the machine.  Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructionsThis event counts the number of instructions that retire.  For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires.  The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.  Background: Modern microprocessors employ extensive pipelining and speculative techniques.  Since sometimes an instruction is started but never completed, the notion of "retirement" is introduced.  A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires.  This counter measures the number of completed instructions.  The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_PThis event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlersCounts all machine clearsMachine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path.  All instructions "older" than this one will be allowed to finish.  This instruction and all "younger" instructions must be cleared, since they must not be allowed to complete.  Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine.  This means all older instructions are retired, and all pending stores (from older instructions) are completed.  Then the new path of instructions from the front end are allowed to start into the machine.  There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault).  All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST).  However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANYThis event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processorsevent=0xca,period=200003,umask=0x3fCounts the number of cycles when no uops are allocated for any reasonThe NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycleCounts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire.  After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredictedevent=0xca,period=200003,umask=0x50Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocationThe NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance.  Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources.  When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidthCounts the number of cycles when no uops are allocated and a RATstall is assertedCounts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event countsCounts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry.  The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to MThis event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-opsMSROM micro-ops retiredLoads missed DTLB (Precise event)This event counts the number of load ops retired that had DTLB miss (Precise event)Total cycles for all the page walks. (I-side and D-side)This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this eventDuration of D-side page-walks in core cyclesThis event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walksD-side page-walksThis event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalksDuration of I-side page-walks in core cyclesThis event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walksI-side page-walksThis event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalksTotal page walks that are completed (I-side and D-side)This event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalksRetired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS) (Precise event)This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS) (Precise event)This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package).  Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line.  In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS) (Precise event)mem_load_uops_misc_retired.llc_missevent=0xd4,period=100007,umask=0x2Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS) (Precise event)This event counts retired demand loads that missed the  last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS) (Precise event)Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS) (Precise event)Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS) (Precise event)Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS) (Precise event)This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS) (Precise event)All retired load uops. (Precise Event - PEBS) (Precise event)This event counts the number of load uops retired (Precise Event) (Precise event)All retired store uops. (Precise Event - PEBS) (Precise event)This event counts the number of store uops retired. (Precise Event - PEBS) (Precise event)Retired load uops with locked access. (Precise Event - PEBS) (Precise event)Retired load uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event)This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event)Retired store uops that split across a cacheline boundary. (Precise Event - PEBS) (Precise event)This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS) (Precise event)Retired load uops that miss the STLB. (Precise Event - PEBS) (Precise event)Retired store uops that miss the STLB. (Precise Event - PEBS) (Precise event)offcore_response.all_code_rd.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0244Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_code_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0244Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.all_pf_code_rd.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0240Counts all prefetch code reads that hit in the LLCoffcore_response.all_pf_code_rd.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0240Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_pf_code_rd.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0240Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_pf_code_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0240Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_pf_code_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0240Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all prefetch data reads that hit in the LLCCounts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.all_pf_rfo.llc_hit.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0120Counts all prefetch RFOs that hit in the LLCoffcore_response.all_pf_rfo.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0120Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_pf_rfo.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0120Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_pf_rfo.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0120Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_pf_rfo.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0120Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all data/code/rfo references (demand & prefetch) Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedCounts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedCounts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresCounts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all demand & prefetch prefetch RFOs event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0122Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0122Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.all_rfo.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0122Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseCOREWB & ANY_RESPONSEoffcore_response.data_in.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10433REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSEevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0004Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0004Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_code_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0004Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all demand data reads Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all demand rfo's event=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0002Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.demand_rfo.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0002Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.demand_rfo.llc_hit_m.hitmREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITMevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2380408000offcore_response.pf_ifetch.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10040REQUEST = PF_RFO and RESPONSE = ANY_RESPONSEoffcore_response.pf_l2_code_rd.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0040Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l2_code_rd.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0040Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_code_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0040Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l2_code_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0040Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all prefetch (that bring data to L2) data reads that hit in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0020Counts all prefetch (that bring data to L2) RFOs that hit in the LLCoffcore_response.pf_l2_rfo.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0020Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l2_rfo.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0020Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_l2_rfo.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0020Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l2_rfo.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0020Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.pf_llc_code_rd.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0200Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_llc_code_rd.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0200Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_llc_code_rd.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0200Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_llc_code_rd.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0200Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean responseCounts all prefetch (that bring data to LLC only) data reads that hit in the LLCevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3f803c0100Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLCoffcore_response.pf_llc_rfo.llc_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003c0100Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_llc_rfo.llc_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003c0100Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwardedoffcore_response.pf_llc_rfo.llc_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003c0100Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_llc_rfo.llc_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003c0100Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean responseoffcore_response.pf_l_data_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10080REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSEoffcore_response.pf_l_ifetch.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10200REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSEThis event counts cycles during which the microcode sequencer assisted the front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.  See the Intel 64 and IA-32 Architectures Optimization Reference Manual for more informationoffcore_response.all_pf_code_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400240Counts all prefetch code reads that miss the LLC  and the data returned from dramoffcore_response.all_pf_data_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400090Counts all prefetch data reads that miss the LLC  and the data returned from dramoffcore_response.all_pf_rfo.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400120Counts all prefetch RFOs that miss the LLC  and the data returned from dramoffcore_response.all_rfo.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400122Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dramoffcore_response.any_request.llc_miss_local.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80408fffREQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMThis event counts any requests that miss the LLC where the data was returned from local DRAMThis event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC  where the data is returned from local DRAMoffcore_response.data_in_socket.llc_miss_local.any_llc_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x17004001b3REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIToffcore_response.demand_ifetch.llc_miss_local.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400004REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.demand_rfo.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400002Counts demand data writes (RFOs) that miss the LLC and the data returned from dramoffcore_response.pf_data_rd.llc_miss_local.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400010REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.pf_ifetch.llc_miss_local.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400040REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.pf_l2_code_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400040Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dramoffcore_response.pf_l2_data_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400010Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dramoffcore_response.pf_l2_rfo.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400020Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dramoffcore_response.pf_llc_code_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400200Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dramoffcore_response.pf_llc_data_rd.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400080Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dramoffcore_response.pf_llc_rfo.llc_miss.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x300400100Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dramoffcore_response.pf_l_data_rd.llc_miss_local.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400080REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMoffcore_response.pf_l_ifetch.llc_miss_local.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1f80400200REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAMNumber of any page walk that had a miss in LLC. Does not necessary cause a SUSPENDDirect and indirect mispredicted near call instructions retired. (Precise Event - PEBS) (Precise event)Mispredicted not taken branch instructions retired.(Precise Event - PEBS) (Precise event)Mispredicted taken branch instructions retired. (Precise Event - PEBS) (Precise event)This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issuedThis event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel 64 and IA-32 Architectures Optimization Reference ManualThis event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructionsActually retired uops. (Precise Event - PEBS) (Precise event)This event counts the number of micro-ops retired. (Precise Event) (Precise event)This event counts the number of retirement slots used each cycle.  There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle.  This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS) (Precise event)snb metricsoffcore_requests.anyevent=0xb0,period=100000,umask=0x80offcore_requests.any.readevent=0xb0,period=100000,umask=0x8Offcore read requestsoffcore_requests.any.rfoevent=0xb0,period=100000,umask=0x10Offcore RFO requestsoffcore_requests.demand.read_codeevent=0xb0,period=100000,umask=0x2Offcore demand code read requestsoffcore_requests.demand.read_dataevent=0xb0,period=100000,umask=0x1Offcore demand data read requestsoffcore_requests.demand.rfoevent=0xb0,period=100000,umask=0x4Offcore demand RFO requestsoffcore_requests_outstanding.any.readevent=0x60,period=2000000,umask=0x8Outstanding offcore readsoffcore_requests_outstanding.any.read_not_emptyevent=0x60,cmask=1,period=2000000,umask=0x8Cycles offcore reads busyoffcore_requests_outstanding.demand.read_codeevent=0x60,period=2000000,umask=0x2Outstanding offcore demand code readsoffcore_requests_outstanding.demand.read_code_not_emptyevent=0x60,cmask=1,period=2000000,umask=0x2Cycles offcore demand code read busyoffcore_requests_outstanding.demand.read_dataevent=0x60,period=2000000,umask=0x1Outstanding offcore demand data readsoffcore_requests_outstanding.demand.read_data_not_emptyevent=0x60,cmask=1,period=2000000,umask=0x1Cycles offcore demand data read busyoffcore_requests_outstanding.demand.rfoevent=0x60,period=2000000,umask=0x4Outstanding offcore demand RFOsoffcore_requests_outstanding.demand.rfo_not_emptyevent=0x60,cmask=1,period=2000000,umask=0x4Cycles offcore demand RFOs busyoffcore_response.any_data.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5011REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f11REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff11REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATIONREQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIOREQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHEoffcore_response.any_data.local_dram_and_remote_cache_hitREQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITMoffcore_response.any_ifetch.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5044REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f44REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff44REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATIONREQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHEoffcore_response.any_ifetch.local_dram_and_remote_cache_hitREQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITMoffcore_response.any_request.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x50ffREQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7fffREQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xffffREQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATIONevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x80ffREQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIOevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1ffREQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_COREevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2ffREQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4ffREQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7ffREQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHEoffcore_response.any_request.local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x10ffREQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8ffREQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITMoffcore_response.any_rfo.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5022REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f22REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff22REQUEST = ANY RFO and RESPONSE = ANY_LOCATIONREQUEST = ANY RFO and RESPONSE = IO_CSR_MMIOREQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = ANY RFO and RESPONSE = LOCAL_CACHEoffcore_response.any_rfo.local_dram_and_remote_cache_hitREQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITMoffcore_response.corewb.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5008REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f08REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff08REQUEST = CORE_WB and RESPONSE = ANY_LOCATIONREQUEST = CORE_WB and RESPONSE = IO_CSR_MMIOREQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_COREoffcore_response.corewb.llc_hit_other_core_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x208REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = CORE_WB and RESPONSE = LOCAL_CACHEoffcore_response.corewb.local_dram_and_remote_cache_hitREQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITMoffcore_response.data_ifetch.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5077REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f77REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff77REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATIONREQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHEoffcore_response.data_ifetch.local_dram_and_remote_cache_hitREQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITMoffcore_response.data_in.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5033REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f33REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff33REQUEST = DATA_IN and RESPONSE = ANY_LOCATIONREQUEST = DATA_IN and RESPONSE = IO_CSR_MMIOREQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DATA_IN and RESPONSE = LOCAL_CACHEoffcore_response.data_in.local_dram_and_remote_cache_hitREQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITMoffcore_response.demand_data.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5003REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f03REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff03REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHEoffcore_response.demand_data.local_dram_and_remote_cache_hitREQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITMoffcore_response.demand_data_rd.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5001REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f01REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff01REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHEoffcore_response.demand_data_rd.local_dram_and_remote_cache_hitREQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITMoffcore_response.demand_ifetch.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5004REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f04REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff04REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHEoffcore_response.demand_ifetch.local_dram_and_remote_cache_hitREQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITMoffcore_response.demand_rfo.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5002REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f02REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff02REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATIONREQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIOREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHEoffcore_response.demand_rfo.local_dram_and_remote_cache_hitREQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITMoffcore_response.other.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5080REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f80REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff80REQUEST = OTHER and RESPONSE = ANY_LOCATIONREQUEST = OTHER and RESPONSE = IO_CSR_MMIOREQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = OTHER and RESPONSE = LOCAL_CACHEoffcore_response.other.local_dram_and_remote_cache_hitREQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITMoffcore_response.pf_data.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5050REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f50REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff50REQUEST = PF_DATA and RESPONSE = ANY_LOCATIONevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x8050REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIOevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x150REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_COREevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x250REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x450REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x750REQUEST = PF_DATA and RESPONSE = LOCAL_CACHEoffcore_response.pf_data.local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x1050REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x850REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITMoffcore_response.pf_data_rd.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5010REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f10REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff10REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATIONREQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIOREQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHEoffcore_response.pf_data_rd.local_dram_and_remote_cache_hitREQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITMoffcore_response.pf_ifetch.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5040REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f40REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff40REQUEST = PF_RFO and RESPONSE = ANY_LOCATIONREQUEST = PF_RFO and RESPONSE = IO_CSR_MMIOREQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PF_RFO and RESPONSE = LOCAL_CACHEoffcore_response.pf_ifetch.local_dram_and_remote_cache_hitREQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITMoffcore_response.pf_rfo.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5020REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f20REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff20REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATIONREQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIOREQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHEoffcore_response.pf_rfo.local_dram_and_remote_cache_hitREQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITMoffcore_response.prefetch.all_local_dram_and_remote_cache_hitevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x5070REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HITevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x7f70REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xff70REQUEST = PREFETCH and RESPONSE = ANY_LOCATIONREQUEST = PREFETCH and RESPONSE = IO_CSR_MMIOREQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_COREREQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITREQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITMREQUEST = PREFETCH and RESPONSE = LOCAL_CACHEoffcore_response.prefetch.local_dram_and_remote_cache_hitREQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HITREQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITMsq_misc.lru_hintsevent=0xf4,period=2000000,umask=0x4Super Queue LRU hints sent to LLCmisalign_mem_ref.storeevent=0x5,period=200000,umask=0x2Misaligned store referencesoffcore_response.any_data.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3011REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf811REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISSoffcore_response.any_data.other_local_dramREQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAMREQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAMoffcore_response.any_ifetch.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3044REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf844REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.any_ifetch.other_local_dramREQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAMoffcore_response.any_request.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x30ffREQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf8ffREQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISSoffcore_response.any_request.other_local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x40ffREQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x20ffREQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAMoffcore_response.any_rfo.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3022REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf822REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISSoffcore_response.any_rfo.other_local_dramREQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAMREQUEST = ANY RFO and RESPONSE = REMOTE_DRAMoffcore_response.corewb.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3008REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf808REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISSoffcore_response.corewb.other_local_dramREQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAMREQUEST = CORE_WB and RESPONSE = REMOTE_DRAMoffcore_response.data_ifetch.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3077REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf877REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.data_ifetch.other_local_dramREQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAMoffcore_response.data_in.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3033REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf833REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISSoffcore_response.data_in.other_local_dramREQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DATA_IN and RESPONSE = REMOTE_DRAMoffcore_response.demand_data.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3003REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf803REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISSoffcore_response.demand_data.other_local_dramREQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAMoffcore_response.demand_data_rd.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3001REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf801REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISSoffcore_response.demand_data_rd.other_local_dramREQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAMoffcore_response.demand_ifetch.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3004REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf804REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.demand_ifetch.other_local_dramREQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAMoffcore_response.demand_rfo.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3002REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf802REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISSoffcore_response.demand_rfo.other_local_dramREQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAMREQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAMoffcore_response.other.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3080REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf880REQUEST = OTHER and RESPONSE = ANY_LLC_MISSoffcore_response.other.other_local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4080REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAMREQUEST = OTHER and RESPONSE = REMOTE_DRAMoffcore_response.pf_data.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3050REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf850REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISSoffcore_response.pf_data.other_local_dramevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x4050REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2050REQUEST = PF_DATA and RESPONSE = REMOTE_DRAMoffcore_response.pf_data_rd.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3010REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf810REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISSoffcore_response.pf_data_rd.other_local_dramREQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAMoffcore_response.pf_ifetch.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3040REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf840REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISSoffcore_response.pf_ifetch.other_local_dramREQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PF_RFO and RESPONSE = REMOTE_DRAMoffcore_response.pf_rfo.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3020REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf820REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.pf_rfo.other_local_dramREQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAMoffcore_response.prefetch.any_dram_and_remote_fwdevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x3070REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWDevent=0xb7,period=100000,umask=0x1,offcore_rsp=0xf870REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISSoffcore_response.prefetch.other_local_dramREQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAMREQUEST = PREFETCH and RESPONSE = REMOTE_DRAMload_block.overlap_storeevent=0x3,period=200000,umask=0x2Loads that partially overlap an earlier storesnoopq_requests.codeevent=0xb4,period=100000,umask=0x4Snoop code requestssnoopq_requests.dataevent=0xb4,period=100000,umask=0x1Snoop data requestssnoopq_requests.invalidateevent=0xb4,period=100000,umask=0x2Snoop invalidate requestssnoopq_requests_outstanding.codeOutstanding snoop code requestssnoopq_requests_outstanding.code_not_emptyevent=0xb3,cmask=1,period=2000000,umask=0x4Cycles snoop code requests queuedsnoopq_requests_outstanding.dataOutstanding snoop data requestssnoopq_requests_outstanding.data_not_emptyevent=0xb3,cmask=1,period=2000000,umask=0x1Cycles snoop data requests queuedsnoopq_requests_outstanding.invalidateOutstanding snoop invalidate requestssnoopq_requests_outstanding.invalidate_not_emptyevent=0xb3,cmask=1,period=2000000,umask=0x2Cycles snoop invalidate requests queuedevent=0xc5,period=20000,umask=0x4Mispredicted retired branch instructions (Precise Event)event=0xc5,period=20000,umask=0x1Mispredicted conditional retired branches (Precise Event)dtlb_load_misses.large_walk_completedevent=0x8,period=200000,umask=0x80DTLB load miss large page walksdtlb_load_misses.walk_cyclesevent=0x8,period=200000,umask=0x4DTLB load miss page walk cyclesdtlb_misses.large_walk_completedevent=0x49,period=200000,umask=0x80DTLB miss large page walksdtlb_misses.pde_missevent=0x49,period=200000,umask=0x20DTLB misses casued by low part of addressdtlb_misses.walk_cyclesevent=0x49,period=2000000,umask=0x4DTLB miss page walk cyclesevent=0x4f,period=2000000,umask=0x10Extended Page Table walk cyclesitlb_misses.large_walk_completedevent=0x85,period=200000,umask=0x80ITLB miss large page walksitlb_misses.walk_cyclesevent=0x85,period=2000000,umask=0x4ITLB miss page walk cyclesoffcore_requests.uncached_memevent=0xb0,period=100000,umask=0x20Offcore uncached memory accessesevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2711event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5811event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2744event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5844event=0xb7,period=100000,umask=0x1,offcore_rsp=0x27FFevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x58FFevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2722event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5822event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2708event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5808event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2777event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5877Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unitOffcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling coreOffcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling coreOffcore data reads, RFOs, and prefetches satisfied by the LLC  and HITM in a sibling coreevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2733event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5833Offcore data reads, RFOs, and prefetches that HIT in a remote cacheOffcore data reads, RFOs, and prefetches that HITM in a remote cacheevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x2703event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5803event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2701event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5801event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2704event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5804event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2702event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5802event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2780event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5880event=0xb7,period=100000,umask=0x1,offcore_rsp=0x7F50event=0xb7,period=100000,umask=0x1,offcore_rsp=0xFF50event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2750event=0xb7,period=100000,umask=0x1,offcore_rsp=0x1850event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5850event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2710event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5810event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2740event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5840event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2720event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5820event=0xb7,period=100000,umask=0x1,offcore_rsp=0x2770event=0xb7,period=100000,umask=0x1,offcore_rsp=0x5870Offcore data reads, RFOs, and prefetches satisfied by the local DRAMOffcore data reads, RFOs, and prefetches satisfied by the remote DRAMevent=0xb7,period=100000,umask=0x1,offcore_rsp=0x6050event=0xb7,period=100000,umask=0x1,offcore_rsp=0xF850mem_uncore_retired.local_dram_and_remote_cache_hitLoad instructions retired local dram and remote cache HIT data sources (Precise Event)mem_uncore_retired.local_hitmmem_uncore_retired.remote_hitmevent=0xf,period=40000,umask=0x4Retired loads that hit remote socket in modified state (Precise Event)event=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x3fevent=0xb1,cmask=1,edge=1,inv=1,period=2000000,umask=0x1fDTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDECounts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or droppedCounts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded eventmem_load_l3_miss_retired.local_dramRetired load instructions which data sources missed L3 but serviced from local dram  Supports address when precise (Precise event)Retired load instructions which data sources missed L3 but serviced from local DRAM  Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_dramevent=0xd3,period=100007,umask=0x2Retired load instructions which data sources missed L3 but serviced from remote dram  Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_fwdevent=0xd3,period=100007,umask=0x8Retired load instructions whose data sources was forwarded from a remote cache  Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_hitmRetired load instructions whose data sources was remote HITM  Supports address when precise (Precise event)event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10491Counts all demand & prefetch data reads that have any response typeevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0491Counts all demand & prefetch data reads that hit in the L3event=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0491Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0491offcore_response.all_data_rd.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0491Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0491OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10490Counts all prefetch data reads that have any response typeevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0490Counts all prefetch data reads that hit in the L3offcore_response.all_pf_data_rd.l3_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0490Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_pf_data_rd.l3_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0490offcore_response.all_pf_data_rd.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0490Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0490OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10120Counts prefetch RFOs that have any response typeCounts prefetch RFOs that hit in the L3offcore_response.all_pf_rfo.l3_hit.hitm_other_coreCounts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.all_pf_rfo.l3_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0120offcore_response.all_pf_rfo.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0120Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0120OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10122Counts all demand & prefetch RFOs that have any response typeCounts all demand & prefetch RFOs that hit in the L3Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0122offcore_response.all_rfo.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0122Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.all_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0122OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWDCounts all demand code reads that have any response typeCounts all demand code reads that hit in the L3Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0004offcore_response.demand_code_rd.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0004Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0004OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWDCounts demand data reads that have any response typeCounts demand data reads that hit in the L3Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0001offcore_response.demand_data_rd.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0001Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0001OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDCounts all demand data writes (RFOs) that have any response typeCounts all demand data writes (RFOs) that hit in the L3Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0002offcore_response.demand_rfo.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0002Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.demand_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0002OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.pf_l1d_and_sw.any_responseCounts L1 data cache hardware prefetch requests and software prefetch requests that have any response typeoffcore_response.pf_l1d_and_sw.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C0400Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3offcore_response.pf_l1d_and_sw.l3_hit.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0400Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0400offcore_response.pf_l1d_and_sw.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0400Counts L1 data cache hardware prefetch requests and software prefetch requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0400OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10010Counts prefetch (that bring data to L2) data reads that have any response typeCounts prefetch (that bring data to L2) data reads that hit in the L3offcore_response.pf_l2_data_rd.l3_hit.hitm_other_coreCounts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l2_data_rd.l3_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0010offcore_response.pf_l2_data_rd.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0010Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0010OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10020Counts all prefetch (that bring data to L2) RFOs that have any response typeCounts all prefetch (that bring data to L2) RFOs that hit in the L3offcore_response.pf_l2_rfo.l3_hit.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l2_rfo.l3_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0020offcore_response.pf_l2_rfo.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0020Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0020OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWDCounts all prefetch (that bring data to LLC only) data reads that have any response typeCounts all prefetch (that bring data to LLC only) data reads that hit in the L3offcore_response.pf_l3_data_rd.l3_hit.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l3_data_rd.l3_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0080offcore_response.pf_l3_data_rd.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0080Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0080OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100Counts all prefetch (that bring data to LLC only) RFOs that have any response typeCounts all prefetch (that bring data to LLC only) RFOs that hit in the L3offcore_response.pf_l3_rfo.l3_hit.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwardedoffcore_response.pf_l3_rfo.l3_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0100offcore_response.pf_l3_rfo.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0100Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple coresoffcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0100OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWDfp_arith_inst_retired.512b_packed_doubleevent=0xc7,period=2000003,umask=0x40Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsfp_arith_inst_retired.512b_packed_singleevent=0xc7,period=2000003,umask=0x80Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsoffcore_response.all_data_rd.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000491Counts all demand & prefetch data reads that miss in the L3offcore_response.all_data_rd.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00491Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cacheoffcore_response.all_data_rd.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00491Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_data_rd.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00491Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dramoffcore_response.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000491Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dramoffcore_response.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800491Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dramoffcore_response.all_pf_data_rd.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000490Counts all prefetch data reads that miss in the L3offcore_response.all_pf_data_rd.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00490Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cacheoffcore_response.all_pf_data_rd.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00490Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_pf_data_rd.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00490Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dramoffcore_response.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000490Counts all prefetch data reads that miss the L3 and the data is returned from local dramoffcore_response.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800490Counts all prefetch data reads that miss the L3 and the data is returned from remote dramoffcore_response.all_pf_rfo.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000120Counts prefetch RFOs that miss in the L3offcore_response.all_pf_rfo.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00120Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cacheoffcore_response.all_pf_rfo.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00120Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_pf_rfo.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00120Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dramoffcore_response.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000120Counts prefetch RFOs that miss the L3 and the data is returned from local dramoffcore_response.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800120Counts prefetch RFOs that miss the L3 and the data is returned from remote dramoffcore_response.all_rfo.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000122Counts all demand & prefetch RFOs that miss in the L3offcore_response.all_rfo.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00122Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cacheoffcore_response.all_rfo.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00122Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.all_rfo.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00122Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dramoffcore_response.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000122Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dramoffcore_response.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800122Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000004Counts all demand code reads that miss in the L3offcore_response.demand_code_rd.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00004Counts all demand code reads that miss the L3 and the modified data is transferred from remote cacheoffcore_response.demand_code_rd.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00004Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.demand_code_rd.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00004Counts all demand code reads that miss the L3 and the data is returned from local or remote dramoffcore_response.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000004Counts all demand code reads that miss the L3 and the data is returned from local dramoffcore_response.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800004Counts all demand code reads that miss the L3 and the data is returned from remote dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000001Counts demand data reads that miss in the L3offcore_response.demand_data_rd.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00001Counts demand data reads that miss the L3 and the modified data is transferred from remote cacheoffcore_response.demand_data_rd.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00001Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.demand_data_rd.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00001Counts demand data reads that miss the L3 and the data is returned from local or remote dramoffcore_response.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000001Counts demand data reads that miss the L3 and the data is returned from local dramoffcore_response.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800001Counts demand data reads that miss the L3 and the data is returned from remote dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000002Counts all demand data writes (RFOs) that miss in the L3offcore_response.demand_rfo.l3_miss.remote_hitmCounts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cacheoffcore_response.demand_rfo.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00002Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.demand_rfo.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00002Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dramoffcore_response.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000002Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dramoffcore_response.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800002Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dramoffcore_response.pf_l1d_and_sw.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000400Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3offcore_response.pf_l1d_and_sw.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00400Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cacheoffcore_response.pf_l1d_and_sw.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00400Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.pf_l1d_and_sw.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00400Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dramoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000400Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dramoffcore_response.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800400Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dramoffcore_response.pf_l2_data_rd.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000010Counts prefetch (that bring data to L2) data reads that miss in the L3offcore_response.pf_l2_data_rd.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00010Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cacheoffcore_response.pf_l2_data_rd.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00010Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.pf_l2_data_rd.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00010Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dramoffcore_response.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000010Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dramoffcore_response.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800010Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dramoffcore_response.pf_l2_rfo.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000020Counts all prefetch (that bring data to L2) RFOs that miss in the L3offcore_response.pf_l2_rfo.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00020Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cacheoffcore_response.pf_l2_rfo.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00020Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.pf_l2_rfo.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00020Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dramoffcore_response.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000020Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dramoffcore_response.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800020Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dramoffcore_response.pf_l3_data_rd.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000080Counts all prefetch (that bring data to LLC only) data reads that miss in the L3offcore_response.pf_l3_data_rd.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00080Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cacheoffcore_response.pf_l3_data_rd.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00080Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.pf_l3_data_rd.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00080Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dramoffcore_response.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000080Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dramoffcore_response.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800080Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dramoffcore_response.pf_l3_rfo.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC000100Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3offcore_response.pf_l3_rfo.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC00100Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cacheoffcore_response.pf_l3_rfo.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC00100Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cacheoffcore_response.pf_l3_rfo.l3_miss.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63FC00100Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dramoffcore_response.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604000100Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dramoffcore_response.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B800100Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dramcore_power.lvl0_turbo_licenseevent=0x28,period=200003,umask=0x7Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo scheduleCore cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codescore_power.lvl1_turbo_licenseevent=0x28,period=200003,umask=0x18Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo scheduleCore cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructionscore_power.lvl2_turbo_licenseevent=0x28,period=200003,umask=0x20Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo scheduleCore cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructionscore_power.throttleevent=0x28,period=200003,umask=0x40Core cycles the core was throttled due to a pending power level requestCore cycles the out-of-order engine was throttled due to a pending power level requestidi_misc.wb_downgradeevent=0xfe,period=100003,umask=0x4Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortlyidi_misc.wb_upgradeevent=0xfe,period=100003,umask=0x2Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortlyskx metrics100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) )100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) )( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) )Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double countingINST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )IpArith_AVX512Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANYL2_Evictions_Silent_PKIL2Evicts;Mem;ServerRate of non silent evictions from the L2 cache per Kilo instruction1000 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANYL2_Evictions_NonSilent_PKI( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_timeFraction of Core cycles where the core was running with power-delivery for baseline license level 0Fraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codesCORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.THREADPower_License0_UtilizationFraction of Core cycles where the core was running with power-delivery for baseline license level 0. SMT version; use when SMT is enabled and measuring per logical CPUFraction of Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes. SMT version; use when SMT is enabled and measuring per logical CPUCORE_POWER.LVL0_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )Power_License0_Utilization_SMTPower_SMTFraction of Core cycles where the core was running with power-delivery for license level 1Fraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructionsCORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.THREADPower_License1_UtilizationFraction of Core cycles where the core was running with power-delivery for license level 1. SMT version; use when SMT is enabled and measuring per logical CPUFraction of Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions. SMT version; use when SMT is enabled and measuring per logical CPUCORE_POWER.LVL1_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )Power_License1_Utilization_SMTFraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructionsCORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.THREADPower_License2_UtilizationFraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). SMT version; use when SMT is enabled and measuring per logical CPUFraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX).  This includes high current AVX 512-bit instructions. SMT version; use when SMT is enabled and measuring per logical CPUCORE_POWER.LVL2_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )Power_License2_Utilization_SMT1000000000 * ( cha@event\=0x36\,umask\=0x21\,config\=0x40433@ / cha@event\=0x35\,umask\=0x21\,config\=0x40433@ ) / ( cha_0@event\=0x0@ / duration_time )cha@event\=0x36\,umask\=0x21\,config\=0x40433@ / cha@event\=0x36\,umask\=0x21\,config\=0x40433\,thresh\=1@Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches1000000000 * ( UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS ) / imc_0@event\=0x0@MEM_DRAM_Read_LatencyMem;MemoryLat;SoC;ServerAverage IO (network or disk) Bandwidth Use for Writes [GB / sec]( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000000 / duration_timeIO_Write_BWIoBW;Mem;SoC;ServerAverage IO (network or disk) Bandwidth Use for Reads [GB / sec]( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 ) * 4 / 1000000000 / duration_timeIO_Read_BWcha_0@event\=0x0@read requests to memory controller. Unit: uncore_imc write requests to memory controller. Unit: uncore_imc unc_m_act_count.wrDRAM Page Activate commands sent due to a write request. Unit: uncore_imc Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller).  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) commandunc_m_cas_count.allevent=0x4,umask=0xFAll DRAM CAS Commands issued. Unit: uncore_imc Counts all CAS (Column Address Select) commands issued to DRAM per memory channel.  CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or notunc_m_cas_count.rd_regevent=0x4,umask=0x1All DRAM Read CAS Commands issued (does not include underfills). Unit: uncore_imc Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read.  This event only counts regular reads and does not includes underfill reads due to partial write requests.  This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write)  is enabled or notunc_m_cas_count.rd_underfillevent=0x4,umask=0x2DRAM Underfill Read CAS Commands issued. Unit: uncore_imc Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis.  CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads.  Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request)unc_m_cas_count.wr_wmmevent=0x4,umask=0x4DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode. Unit: uncore_imc Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Modeunc_m_rpq_insertsRead Pending Queue Allocations. Unit: uncore_imc Counts the number of read requests allocated into the Read Pending Queue (RPQ).  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  The requests deallocate after the read CAS command has been issued to DRAM.  This event counts both Isochronous and non-Isochronous requests which were issued to the RPQRead Pending Queue Occupancy. Unit: uncore_imc Counts the number of entries in the Read Pending Queue (RPQ) at each cycle.  This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memoryunc_m_wpq_insertsevent=0x20Write Pending Queue Allocations. Unit: uncore_imc Counts the number of writes requests allocated into the Write Pending Queue (WPQ).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller).  The write requests deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMCunc_m_wpq_occupancyevent=0x81Write Pending Queue Occupancy. Unit: uncore_imc Counts the number of entries in the Write Pending Queue (WPQ) at each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule writes out to the memory controller and to track the requests.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller).  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???unc_cha_clockticksUncore cache clock ticks. Unit: uncore_cha uncore_chaevent=0x35,umask=0x21,config1=0x40e33LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha unc_cha_tor_inserts.ia_missLLC misses - Uncacheable reads (from cpu) . Unit: uncore_cha event=0x35,umask=0x21,config1=0x40040e33MMIO reads. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha MMIO reads. Unit: uncore_cha event=0x35,umask=0x21,config1=0x40041e33MMIO writes. Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha MMIO writes. Unit: uncore_cha event=0x35,umask=0x21,config1=0x41833Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha Streaming stores (full cache line). Unit: uncore_cha event=0x35,umask=0x21,config1=0x41a33Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss. Unit: uncore_cha Streaming stores (partial cache line). Unit: uncore_cha unc_cha_requests.readsevent=0x50,umask=0x03read requests from home agent. Unit: uncore_cha unc_cha_requests.reads_localevent=0x50,umask=0x01read requests from local home agent. Unit: uncore_cha unc_cha_requests.reads_remoteevent=0x50,umask=0x02read requests from remote home agent. Unit: uncore_cha unc_cha_requests.writesevent=0x50,umask=0x0Cwrite requests from home agent. Unit: uncore_cha unc_cha_requests.writes_localevent=0x50,umask=0x04write requests from local home agent. Unit: uncore_cha upi_data_bandwidth_txevent=0x2,umask=0xfUPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data. Unit: uncore_upi uncore_upi7.11E-06Bytesunc_upi_txl_flits.all_dataUPI interconnect send bandwidth for payload. Unit: uncore_upi unc_iio_data_req_of_cpu.mem_read.part0event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x04PCI Express bandwidth reading at IIO, part 0. Unit: uncore_iio uncore_iio4Bytesunc_iio_data_req_of_cpu.mem_read.part1event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x04PCI Express bandwidth reading at IIO, part 1. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part2event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x04PCI Express bandwidth reading at IIO, part 2. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_read.part3event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x04PCI Express bandwidth reading at IIO, part 3. Unit: uncore_iio event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x04,ch_mask=0x1fPCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0. Unit: uncore_iio UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3LLC_MISSES.PCIE_READPCI Express bandwidth reading at IIO. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part0event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x01PCI Express bandwidth writing at IIO, part 0. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part1event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x01PCI Express bandwidth writing at IIO, part 1. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part2event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x01PCI Express bandwidth writing at IIO, part 2. Unit: uncore_iio unc_iio_data_req_of_cpu.mem_write.part3event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x01PCI Express bandwidth writing at IIO, part 3. Unit: uncore_iio event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x01,ch_mask=0x1fPCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0. Unit: uncore_iio UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3LLC_MISSES.PCIE_WRITEPCI Express bandwidth writing at IIO. Unit: uncore_iio unc_cha_core_snp.core_gtoneevent=0x33,umask=0x42Core Cross Snoops Issued; Multiple Core Requests. Unit: uncore_cha Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s)unc_cha_core_snp.evict_gtoneevent=0x33,umask=0x82Core Cross Snoops Issued; Multiple Eviction. Unit: uncore_cha unc_cha_dir_lookup.no_snpevent=0x53,umask=0x02Multi-socket cacheline Directory state lookups; Snoop Not Needed. Unit: uncore_cha Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not neededunc_cha_dir_lookup.snpevent=0x53,umask=0x01Multi-socket cacheline Directory state lookups; Snoop Needed. Unit: uncore_cha Counts  transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was neededunc_cha_dir_update.haevent=0x54,umask=0x01Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe. Unit: uncore_cha Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelinesunc_cha_dir_update.torevent=0x54,umask=0x02Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe. Unit: uncore_cha Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelinesunc_cha_fast_asserted.horzevent=0xa5,umask=0x02FaST wire asserted; Horizontal. Unit: uncore_cha Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and acrossunc_cha_hitme_hit.ex_rdsevent=0x5f,umask=0x01Read request from a remote socket which hit in the HitMe Cache to a line In the E state. Unit: uncore_cha Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state.  This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)unc_cha_imc_reads_count.normalevent=0x59,umask=0x01Normal priority reads issued to the memory controller from the CHA. Unit: uncore_cha Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHAunc_cha_imc_writes_count.fullevent=0x5b,umask=0x01CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH. Unit: uncore_cha Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channelsunc_cha_llc_victims.total_eevent=0x37,umask=0x02Lines Victimized; Lines in E state. Unit: uncore_cha Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was inunc_cha_llc_victims.total_fevent=0x37,umask=0x08Lines Victimized; Lines in F State. Unit: uncore_cha unc_cha_llc_victims.total_mevent=0x37,umask=0x01Lines Victimized; Lines in M state. Unit: uncore_cha unc_cha_llc_victims.total_sevent=0x37,umask=0x04Lines Victimized; Lines in S State. Unit: uncore_cha unc_cha_misc.rfo_hit_sevent=0x39,umask=0x08Number of times that an RFO hit in S state. Unit: uncore_cha Counts when a RFO (the Read for Ownership issued before a  write) request hit a cacheline in the S (Shared) stateunc_cha_requests.invitoe_localevent=0x50,umask=0x10Local requests for exclusive ownership of a cache line  without receiving data. Unit: uncore_cha Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHAunc_cha_requests.invitoe_remoteevent=0x50,umask=0x20Local requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHAunc_cha_rxc_inserts.irqevent=0x13,umask=0x01Ingress (from CMS) Allocations; IRQ. Unit: uncore_cha Counts number of allocations per cycle into the specified Ingress queueunc_cha_rxc_irq1_reject.pa_matchevent=0x19,umask=0x80Ingress (from CMS) Request Queue Rejects; PhyAddr Match. Unit: uncore_cha Ingress (from CMS) Request Queue Rejects; PhyAddr Matchunc_cha_rxc_occupancy.irqevent=0x11,umask=0x01Ingress (from CMS) Occupancy; IRQ. Unit: uncore_cha Counts number of entries in the specified Ingress queue in each cycleunc_cha_sf_eviction.e_stateevent=0x3d,umask=0x02Snoop filter capacity evictions for E-state entries. Unit: uncore_cha Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cachelineunc_cha_sf_eviction.m_stateevent=0x3d,umask=0x01Snoop filter capacity evictions for M-state entries. Unit: uncore_cha Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cachelineunc_cha_sf_eviction.s_stateevent=0x3d,umask=0x04Snoop filter capacity evictions for S-state entries. Unit: uncore_cha Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cachelineunc_cha_snoop_resp.rspcnflctsevent=0x5c,umask=0x40RspCnflct* Snoop Responses Received. Unit: uncore_cha Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbIunc_cha_snoop_resp.rspievent=0x5c,umask=0x01RspI Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data)unc_cha_snoop_resp.rspifwdevent=0x5c,umask=0x04RspIFwd Snoop Responses Received. Unit: uncore_cha Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states.  This is commonly returned with RFO (the Read for Ownership issued before a write) transactions.  The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward)  statesunc_cha_snoop_resp.rspsfwdevent=0x5c,umask=0x08RspSFwd Snoop Responses Received. Unit: uncore_cha Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy.  This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) stateunc_cha_snoop_resp.rsp_fwd_wbevent=0x5c,umask=0x20Rsp*Fwd*WB Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket.  This snoop response is only used in &gt;= 4 socket systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memoryunc_cha_snoop_resp.rsp_wbwbevent=0x5c,umask=0x10Rsp*WB Snoop Responses Received. Unit: uncore_cha Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home.  This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured.  This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownershipunc_iio_clockticksClockticks of the IIO Traffic Controller. Unit: uncore_iio Counts clockticks of the 1GHz trafiic controller clock in the IIO unitunc_iio_comp_buf_inserts.cmpd.all_partsevent=0xc2,ch_mask=0x0f,fc_mask=0x4,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 0-3. Unit: uncore_iio PCIe Completion Buffer Inserts of completions with data: Part 0-3unc_iio_comp_buf_inserts.cmpd.part0event=0xc2,ch_mask=0x01,fc_mask=0x4,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 0. Unit: uncore_iio PCIe Completion Buffer Inserts of completions with data: Part 0unc_iio_comp_buf_inserts.cmpd.part1event=0xc2,ch_mask=0x02,fc_mask=0x4,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 1. Unit: uncore_iio PCIe Completion Buffer Inserts of completions with data: Part 1unc_iio_comp_buf_inserts.cmpd.part2event=0xc2,ch_mask=0x04,fc_mask=0x4,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 2. Unit: uncore_iio PCIe Completion Buffer Inserts of completions with data: Part 2unc_iio_comp_buf_inserts.cmpd.part3event=0xc2,ch_mask=0x08,fc_mask=0x4,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 3. Unit: uncore_iio PCIe Completion Buffer Inserts of completions with data: Part 3unc_iio_comp_buf_occupancy.cmpd.all_partsevent=0xd5,fc_mask=0x04,umask=0x0fPCIe Completion Buffer occupancy of completions with data: Part 0-3. Unit: uncore_iio PCIe Completion Buffer occupancy of completions with data: Part 0-3unc_iio_comp_buf_occupancy.cmpd.part0event=0xd5,fc_mask=0x04,umask=0x01PCIe Completion Buffer occupancy of completions with data: Part 0. Unit: uncore_iio PCIe Completion Buffer occupancy of completions with data: Part 0unc_iio_comp_buf_occupancy.cmpd.part1event=0xd5,fc_mask=0x04,umask=0x02PCIe Completion Buffer occupancy of completions with data: Part 1. Unit: uncore_iio PCIe Completion Buffer occupancy of completions with data: Part 1unc_iio_comp_buf_occupancy.cmpd.part2event=0xd5,fc_mask=0x04,umask=0x04PCIe Completion Buffer occupancy of completions with data: Part 2. Unit: uncore_iio PCIe Completion Buffer occupancy of completions with data: Part 2unc_iio_comp_buf_occupancy.cmpd.part3event=0xd5,fc_mask=0x04,umask=0x08PCIe Completion Buffer occupancy of completions with data: Part 3. Unit: uncore_iio PCIe Completion Buffer occupancy of completions with data: Part 3unc_iio_data_req_by_cpu.mem_read.part0event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x04Read request for 4 bytes made by the CPU to IIO Part0. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_read.part1event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x04Read request for 4 bytes made by the CPU to IIO Part1. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_read.part2event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x04Read request for 4 bytes made by the CPU to IIO Part2. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_read.part3event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x04Read request for 4 bytes made by the CPU to IIO Part3. Unit: uncore_iio Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part0event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x01Write request of 4 bytes made to IIO Part0 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part1event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x01Write request of 4 bytes made to IIO Part1 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part2event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x01Write request of 4 bytes made to IIO Part2 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.mem_write.part3event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x01Write request of 4 bytes made to IIO Part3 by the CPU. Unit: uncore_iio Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by  a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_read.part0event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x08Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_read.part1event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x08Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_read.part2event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x08Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_read.part3event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x08Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3. Unit: uncore_iio Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_write.part0event=0xc0,ch_mask=0x01,fc_mask=0x07,umask=0x02Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit.  In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_write.part1event=0xc0,ch_mask=0x02,fc_mask=0x07,umask=0x02Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_write.part2event=0xc0,ch_mask=0x04,fc_mask=0x07,umask=0x02Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_by_cpu.peer_write.part3event=0xc0,ch_mask=0x08,fc_mask=0x07,umask=0x02Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_read.part0event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x08Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_read.part1event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x08Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_read.part2event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x08Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_read.part3event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x08Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target. Unit: uncore_iio Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_write.part0event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x02Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_write.part1event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x02Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_write.part2event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x02Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_data_req_of_cpu.peer_write.part3event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x02Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_read.part0event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x04Read request for up to a 64 byte transaction is made by the CPU to IIO Part0. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_read.part1event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x04Read request for up to a 64 byte transaction is made by the CPU to IIO Part1. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_read.part2event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x04Read request for up to a 64 byte transaction is made by the CPU to IIO Part2. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_read.part3event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x04Read request for up to a 64 byte transaction is made by the CPU to IIO Part3. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part0event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x01Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part1event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x01Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part2event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x01Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.mem_write.part3event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x01Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_read.part0event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x08Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_read.part1event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x08Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_read.part2event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x08Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_read.part3event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x08Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3. Unit: uncore_iio Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_write.part0event=0xc1,ch_mask=0x01,fc_mask=0x07,umask=0x02Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_write.part1event=0xc1,ch_mask=0x02,fc_mask=0x07,umask=0x02Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_write.part2event=0xc1,ch_mask=0x04,fc_mask=0x07,umask=0x02Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_by_cpu.peer_write.part3event=0xc1,ch_mask=0x08,fc_mask=0x07,umask=0x02Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_read.part0event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x04Read request for up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_read.part1event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x04Read request for up to a 64 byte transaction is  made by IIO Part1 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_read.part2event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x04Read request for up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_read.part3event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x04Read request for up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_write.part0event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x01Write request of up to a 64 byte transaction is made by IIO Part0 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_write.part1event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x01Write request of up to a 64 byte transaction is made by IIO Part1 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_write.part2event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x01Write request of up to a 64 byte transaction is made by IIO Part2 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.mem_write.part3event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x01Write request of up to a 64 byte transaction is made by IIO Part3 to Memory. Unit: uncore_iio Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_read.part0event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x08Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_read.part1event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x08Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_read.part2event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x08Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_read.part3event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x08Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_write.part0event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x02Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_write.part1event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x02Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_write.part2event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x02Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the busunc_iio_txn_req_of_cpu.peer_write.part3event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x02Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target. Unit: uncore_iio Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to  any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the busunc_i_cache_total_occupancy.memevent=0xf,umask=0x4Total IRP occupancy of inbound read and write requests. Unit: uncore_irp Total IRP occupancy of inbound read and write requests.  This is effectively the sum of read occupancy and write occupancyuncore_irpunc_i_coherent_ops.pcitomevent=0x10,umask=0x10PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline. Unit: uncore_irp PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO.  PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cacheunc_i_coherent_ops.rfoevent=0x10,umask=0x8RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline. Unit: uncore_irp RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory.  RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cacheunc_i_faf_insertsevent=0x18Inbound read requests received by the IRP and inserted into the FAF queue. Unit: uncore_irp Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRPunc_i_faf_occupancyevent=0x19Occupancy of the IRP FAF queue. Unit: uncore_irp Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRPunc_i_transactions.wr_prefevent=0x11,umask=0x8Inbound write (fast path) requests received by the IRP. Unit: uncore_irp Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the meshunc_m2m_bypass_m2m_egress.not_takenevent=0x22,umask=0x2Traffic in which the M2M to iMC Bypass was not taken. Unit: uncore_m2m Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not takenuncore_m2munc_m2m_direct2core_not_taken_dirstateevent=0x24Cycles when direct to core mode (which bypasses the CHA) was disabled. Unit: uncore_m2m Counts cycles when direct to core mode (which bypasses the CHA) was disabledunc_m2m_direct2core_takenevent=0x23Messages sent direct to core (bypassing the CHA). Unit: uncore_m2m Counts when messages were sent direct to core (bypassing the CHA)unc_m2m_direct2core_txn_overrideevent=0x25Number of reads in which direct to core transaction were overridden. Unit: uncore_m2m Counts reads in which direct to core transactions (which would have bypassed the CHA) were overriddenunc_m2m_direct2upi_not_taken_creditsevent=0x28Number of reads in which direct to Intel UPI transactions were overridden. Unit: uncore_m2m Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overriddenunc_m2m_direct2upi_not_taken_dirstateevent=0x27Cycles when direct to Intel UPI was disabled. Unit: uncore_m2m Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabledunc_m2m_direct2upi_takenevent=0x26Messages sent direct to the Intel UPI. Unit: uncore_m2m Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)unc_m2m_direct2upi_txn_overrideevent=0x29Number of reads that a message sent direct2 Intel UPI was overridden. Unit: uncore_m2m Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overriddenunc_m2m_directory_lookup.anyevent=0x2d,umask=0x1Multi-socket cacheline Directory lookups (any state found). Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)unc_m2m_directory_lookup.state_aevent=0x2d,umask=0x8Multi-socket cacheline Directory lookups (cacheline found in A state). Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data.  The data may be stored in any state in the local socketunc_m2m_directory_lookup.state_ievent=0x2d,umask=0x2Multi-socket cacheline Directory lookup (cacheline found in I state). Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socketunc_m2m_directory_lookup.state_sevent=0x2d,umask=0x4Multi-socket cacheline Directory lookup (cacheline found in S state). Unit: uncore_m2m Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data.  The data may be stored in any state in the local socketunc_m2m_directory_update.a2ievent=0x2e,umask=0x20Multi-socket cacheline Directory update from A to I. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to I (Invalid)unc_m2m_directory_update.a2sevent=0x2e,umask=0x40Multi-socket cacheline Directory update from A to S. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from A (SnoopAll) to S (Shared)unc_m2m_directory_update.anyevent=0x2e,umask=0x1Multi-socket cacheline Directory update from/to Any state. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new stateunc_m2m_directory_update.i2aevent=0x2e,umask=0x4Multi-socket cacheline Directory update from I to A. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to A (SnoopAll)unc_m2m_directory_update.i2sevent=0x2e,umask=0x2Multi-socket cacheline Directory update from I to S. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from I (Invalid) to S (Shared)unc_m2m_directory_update.s2aevent=0x2e,umask=0x10Multi-socket cacheline Directory update from S to A. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to A (SnoopAll)unc_m2m_directory_update.s2ievent=0x2e,umask=0x8Multi-socket cacheline Directory update from S to I. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from from S (Shared) to I (Invalid)unc_m2m_imc_reads.allevent=0x37,umask=0x4Reads to iMC issued. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller)unc_m2m_imc_reads.normalReads to iMC issued at Normal Priority (Non-Isochronous). Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).  It only counts  normal priority non-isochronous readsunc_m2m_imc_writes.allevent=0x38,umask=0x10Writes to iMC issued. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller)unc_m2m_imc_writes.nievent=0x38,umask=0x80M2M Writes Issued to iMC; All, regardless of priority. Unit: uncore_m2m M2M Writes Issued to iMC; All, regardless of priorityunc_m2m_imc_writes.partialevent=0x38,umask=0x2Partial Non-Isochronous writes to the iMC. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller).  It only counts normal priority non-isochronous writesunc_m2m_prefcam_demand_promotionsevent=0x56Prefecth requests that got turn into a demand request. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address.  Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory)unc_m2m_prefcam_insertsevent=0x57Inserts into the Memory Controller Prefetch Queue. Unit: uncore_m2m Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue.  Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memoryunc_m2m_rxc_ad_insertsAD Ingress (from CMS) Queue Inserts. Unit: uncore_m2m Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop).  This is generally used for reads, andunc_m2m_rxc_ad_occupancyevent=0x2AD Ingress (from CMS) Occupancy. Unit: uncore_m2m AD Ingress (from CMS) Occupancyunc_m2m_rxc_bl_insertsBL Ingress (from CMS) Allocations. Unit: uncore_m2m BL Ingress (from CMS) Allocationsunc_m2m_rxc_bl_occupancyBL Ingress (from CMS) Occupancy. Unit: uncore_m2m BL Ingress (from CMS) Occupancyunc_m2m_txc_ad_insertsevent=0x9AD Egress (to CMS) Allocations. Unit: uncore_m2m AD Egress (to CMS) Allocationsunc_m2m_txc_ad_occupancyAD Egress (to CMS) Occupancy. Unit: uncore_m2m AD Egress (to CMS) Occupancyunc_m2m_txc_bl_inserts.allevent=0x15,umask=0x03BL Egress (to CMS) Allocations; All. Unit: uncore_m2m BL Egress (to CMS) Allocations; Allunc_m2m_txc_bl_occupancy.allevent=0x16,umask=0x03BL Egress (to CMS) Occupancy; All. Unit: uncore_m2m BL Egress (to CMS) Occupancy; Allunc_m3upi_upi_prefetch_spawnPrefetches generated by the flow control queue of the M3UPI unit. Unit: uncore_m3upi Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)uncore_m3upiunc_upi_clockticksClocks of the Intel Ultra Path Interconnect (UPI). Unit: uncore_upi Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI).  This clock runs at1/8th the 'GT/s' speed of the UPI link.  For example, a  9.6GT/s  link will have a fixed Frequency of 1.2 Ghzunc_upi_direct_attempts.d2cevent=0x12,umask=0x1Data Response packets that go direct to core. Unit: uncore_upi Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHAunc_upi_direct_attempts.d2uevent=0x12,umask=0x2Data Response packets that go direct to Intel UPI. Unit: uncore_upi Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA unc_upi_l1_power_cyclesevent=0x21Cycles Intel UPI is in L1 power mode (shutdown). Unit: uncore_upi Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode.  L1 is a mode that totally shuts down the UPI link.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdownunc_upi_rxl0p_power_cyclesCycles the Rx of the Intel UPI is in L0p power mode. Unit: uncore_upi Counts cycles when the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save powerunc_upi_rxl_bypassed.slot0event=0x31,umask=0x1FLITs received which bypassed the Slot0 Receive Buffer. Unit: uncore_upi Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyunc_upi_rxl_bypassed.slot1event=0x31,umask=0x2Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer  (Receive Queue) and passed directly across the BGF and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyunc_upi_rxl_bypassed.slot2event=0x31,umask=0x4FLITs received which bypassed the Slot0 Recieve Buffer. Unit: uncore_upi Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue)  and passed directly to the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latencyunc_upi_rxl_flits.all_dataevent=0x3,umask=0x0FValid data FLITs received from any slot. Unit: uncore_upi Counts valid data FLITs  (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unitunc_upi_rxl_flits.all_nullevent=0x3,umask=0x27Null FLITs received from any slot. Unit: uncore_upi Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unitunc_upi_rxl_flits.non_dataevent=0x3,umask=0x97Protocol header and credit FLITs received from any slot. Unit: uncore_upi Counts protocol header and credit FLITs  (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unitunc_upi_txl0p_power_cyclesCycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode. Unit: uncore_upi Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save powerunc_upi_txl_bypassedevent=0x41FLITs that bypassed the TxL Buffer. Unit: uncore_upi Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR  mode, increasing latency to transfer out to the linkunc_upi_txl_flits.all_nullevent=0x2,umask=0x27Null FLITs transmitted from any slot. Unit: uncore_upi Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unitunc_upi_txl_flits.dataValid Flits Sent; Data. Unit: uncore_upi Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting.unc_upi_txl_flits.idleevent=0x2,umask=0x47Idle FLITs transmitted. Unit: uncore_upi Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs).  Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITsunc_upi_txl_flits.non_dataevent=0x2,umask=0x97Protocol header and credit FLITs transmitted across any slot. Unit: uncore_upi Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unitRetired load instructions whose data sources was forwarded from a remote cache  Supports address when precisemem_load_l3_miss_retired.remote_pmmRetired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches. Precise event  Supports address when precise (Precise event)Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event  Supports address when precise (Precise event)mem_load_retired.local_pmmevent=0xd1,period=100003,umask=0x80Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches. Precise event  Supports address when precise (Precise event)Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event  Supports address when precise (Precise event)ocr.all_data_rd.l3_hit.any_snoopOCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOPocr.all_data_rd.l3_hit.hitm_other_coreOCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_COREocr.all_data_rd.l3_hit.hit_other_core_fwdOCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit.hit_other_core_no_fwdOCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_hit.no_snoop_neededOCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0491OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDocr.all_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0491OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISSocr.all_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0491OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONEocr.all_data_rd.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080491OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOPocr.all_data_rd.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080491OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_COREocr.all_data_rd.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080491OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080491OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080491OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080491OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISSocr.all_data_rd.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080491OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONEocr.all_data_rd.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200491OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOPocr.all_data_rd.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200491OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_COREocr.all_data_rd.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200491OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200491OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200491OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200491OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISSocr.all_data_rd.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200491OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONEocr.all_data_rd.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040491OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOPocr.all_data_rd.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040491OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_COREocr.all_data_rd.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040491OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040491OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040491OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040491OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISSocr.all_data_rd.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040491OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONEocr.all_data_rd.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100491OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP  OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOPocr.all_data_rd.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100491OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_COREocr.all_data_rd.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100491OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100491OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100491OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDocr.all_data_rd.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100491OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISSocr.all_data_rd.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100491OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONEocr.all_pf_data_rd.l3_hit.any_snoopOCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOPocr.all_pf_data_rd.l3_hit.hitm_other_coreOCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_COREocr.all_pf_data_rd.l3_hit.hit_other_core_fwdOCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_hit.hit_other_core_no_fwdOCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit.no_snoop_neededOCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0490OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDocr.all_pf_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0490OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISSocr.all_pf_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0490OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONEocr.all_pf_data_rd.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080490OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOPocr.all_pf_data_rd.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080490OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_COREocr.all_pf_data_rd.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080490OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080490OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080490OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080490OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISSocr.all_pf_data_rd.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080490OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONEocr.all_pf_data_rd.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200490OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOPocr.all_pf_data_rd.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200490OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_COREocr.all_pf_data_rd.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200490OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200490OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200490OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200490OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISSocr.all_pf_data_rd.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200490OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONEocr.all_pf_data_rd.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040490OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOPocr.all_pf_data_rd.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040490OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_COREocr.all_pf_data_rd.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040490OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040490OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040490OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040490OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISSocr.all_pf_data_rd.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040490OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONEocr.all_pf_data_rd.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100490OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOPocr.all_pf_data_rd.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100490OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_COREocr.all_pf_data_rd.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100490OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100490OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100490OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100490OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISSocr.all_pf_data_rd.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100490OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONEocr.all_pf_rfo.l3_hit.any_snoopOCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOPocr.all_pf_rfo.l3_hit.hitm_other_coreOCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_COREocr.all_pf_rfo.l3_hit.hit_other_core_fwdOCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit.hit_other_core_no_fwdOCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit.no_snoop_neededOCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0120OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWDocr.all_pf_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0120OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISSocr.all_pf_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0120OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONEocr.all_pf_rfo.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080120OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOPocr.all_pf_rfo.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080120OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_COREocr.all_pf_rfo.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080120OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080120OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080120OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080120OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISSocr.all_pf_rfo.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080120OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONEocr.all_pf_rfo.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200120OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOPocr.all_pf_rfo.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200120OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_COREocr.all_pf_rfo.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200120OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200120OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200120OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200120OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISSocr.all_pf_rfo.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200120OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONEocr.all_pf_rfo.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040120OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOPocr.all_pf_rfo.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040120OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_COREocr.all_pf_rfo.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040120OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040120OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040120OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040120OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISSocr.all_pf_rfo.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040120OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONEocr.all_pf_rfo.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100120OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP  OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOPocr.all_pf_rfo.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100120OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_COREocr.all_pf_rfo.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100120OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100120OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100120OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100120OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISSocr.all_pf_rfo.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100120OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONEocr.all_reads.l3_hit.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C07F7OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOPocr.all_reads.l3_hit.hitm_other_coreOCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_COREocr.all_reads.l3_hit.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C07F7OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWDocr.all_reads.l3_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C07F7OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C07F7OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDEDocr.all_reads.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C07F7OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWDocr.all_reads.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C07F7OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISSocr.all_reads.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C07F7OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONEocr.all_reads.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800807F7OCR.ALL_READS.L3_HIT_E.ANY_SNOOP  OCR.ALL_READS.L3_HIT_E.ANY_SNOOPocr.all_reads.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000807F7OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_E.HITM_OTHER_COREocr.all_reads.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000807F7OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWDocr.all_reads.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000807F7OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000807F7OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDEDocr.all_reads.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000807F7OCR.ALL_READS.L3_HIT_E.SNOOP_MISSocr.all_reads.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800807F7OCR.ALL_READS.L3_HIT_E.SNOOP_NONEocr.all_reads.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F802007F7OCR.ALL_READS.L3_HIT_F.ANY_SNOOP  OCR.ALL_READS.L3_HIT_F.ANY_SNOOPocr.all_reads.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10002007F7OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_F.HITM_OTHER_COREocr.all_reads.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8002007F7OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWDocr.all_reads.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4002007F7OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002007F7OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDEDocr.all_reads.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2002007F7OCR.ALL_READS.L3_HIT_F.SNOOP_MISSocr.all_reads.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x802007F7OCR.ALL_READS.L3_HIT_F.SNOOP_NONEocr.all_reads.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800407F7OCR.ALL_READS.L3_HIT_M.ANY_SNOOP  OCR.ALL_READS.L3_HIT_M.ANY_SNOOPocr.all_reads.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000407F7OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_M.HITM_OTHER_COREocr.all_reads.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000407F7OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWDocr.all_reads.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000407F7OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000407F7OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDEDocr.all_reads.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000407F7OCR.ALL_READS.L3_HIT_M.SNOOP_MISSocr.all_reads.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800407F7OCR.ALL_READS.L3_HIT_M.SNOOP_NONEocr.all_reads.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F801007F7OCR.ALL_READS.L3_HIT_S.ANY_SNOOP  OCR.ALL_READS.L3_HIT_S.ANY_SNOOPocr.all_reads.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10001007F7OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_READS.L3_HIT_S.HITM_OTHER_COREocr.all_reads.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8001007F7OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWDocr.all_reads.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4001007F7OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001007F7OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDEDocr.all_reads.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001007F7OCR.ALL_READS.L3_HIT_S.SNOOP_MISSocr.all_reads.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x801007F7OCR.ALL_READS.L3_HIT_S.SNOOP_NONEocr.all_rfo.l3_hit.any_snoopOCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOPocr.all_rfo.l3_hit.hitm_other_coreOCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_COREocr.all_rfo.l3_hit.hit_other_core_fwdOCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit.hit_other_core_no_fwdOCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit.no_snoop_neededOCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDEDocr.all_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0122OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWDocr.all_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0122OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISSocr.all_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0122OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONEocr.all_rfo.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080122OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_E.ANY_SNOOPocr.all_rfo.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080122OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_COREocr.all_rfo.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080122OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080122OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080122OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080122OCR.ALL_RFO.L3_HIT_E.SNOOP_MISSocr.all_rfo.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080122OCR.ALL_RFO.L3_HIT_E.SNOOP_NONEocr.all_rfo.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200122OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_F.ANY_SNOOPocr.all_rfo.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200122OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_COREocr.all_rfo.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200122OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200122OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200122OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200122OCR.ALL_RFO.L3_HIT_F.SNOOP_MISSocr.all_rfo.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200122OCR.ALL_RFO.L3_HIT_F.SNOOP_NONEocr.all_rfo.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040122OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_M.ANY_SNOOPocr.all_rfo.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040122OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_COREocr.all_rfo.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040122OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040122OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040122OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040122OCR.ALL_RFO.L3_HIT_M.SNOOP_MISSocr.all_rfo.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040122OCR.ALL_RFO.L3_HIT_M.SNOOP_NONEocr.all_rfo.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100122OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP  OCR.ALL_RFO.L3_HIT_S.ANY_SNOOPocr.all_rfo.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100122OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE  OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_COREocr.all_rfo.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100122OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDocr.all_rfo.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100122OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100122OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDEDocr.all_rfo.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100122OCR.ALL_RFO.L3_HIT_S.SNOOP_MISSocr.all_rfo.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100122OCR.ALL_RFO.L3_HIT_S.SNOOP_NONEocr.demand_code_rd.l3_hit.any_snoopCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOPocr.demand_code_rd.l3_hit.hitm_other_coreCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_COREocr.demand_code_rd.l3_hit.hit_other_core_fwdCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit.hit_other_core_no_fwdCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit.no_snoop_neededCounts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0004ocr.demand_code_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0004Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISSocr.demand_code_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0004Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONEocr.demand_code_rd.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOPocr.demand_code_rd.l3_hit_e.hitm_other_coreCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_COREocr.demand_code_rd.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_e.hit_other_core_no_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_e.no_snoop_neededCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit_e.snoop_missocr.demand_code_rd.l3_hit_e.snoop_noneocr.demand_code_rd.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOPocr.demand_code_rd.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_COREocr.demand_code_rd.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200004ocr.demand_code_rd.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200004ocr.demand_code_rd.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOPocr.demand_code_rd.l3_hit_m.hitm_other_coreCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_COREocr.demand_code_rd.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_m.hit_other_core_no_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_m.no_snoop_neededCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit_m.snoop_missocr.demand_code_rd.l3_hit_m.snoop_noneocr.demand_code_rd.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOPocr.demand_code_rd.l3_hit_s.hitm_other_coreCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_COREocr.demand_code_rd.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_hit_s.hit_other_core_no_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_hit_s.no_snoop_neededCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_hit_s.snoop_missocr.demand_code_rd.l3_hit_s.snoop_noneocr.demand_data_rd.l3_hit.any_snoopCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOPocr.demand_data_rd.l3_hit.hitm_other_coreCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_COREocr.demand_data_rd.l3_hit.hit_other_core_fwdCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit.hit_other_core_no_fwdCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit.no_snoop_neededCounts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0001ocr.demand_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0001Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISSocr.demand_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0001Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONEocr.demand_data_rd.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOPocr.demand_data_rd.l3_hit_e.hitm_other_coreCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_COREocr.demand_data_rd.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_e.hit_other_core_no_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_e.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_e.snoop_missocr.demand_data_rd.l3_hit_e.snoop_noneocr.demand_data_rd.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOPocr.demand_data_rd.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_COREocr.demand_data_rd.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200001ocr.demand_data_rd.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200001ocr.demand_data_rd.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOPocr.demand_data_rd.l3_hit_m.hitm_other_coreCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_COREocr.demand_data_rd.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_m.hit_other_core_no_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_m.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_m.snoop_missocr.demand_data_rd.l3_hit_m.snoop_noneocr.demand_data_rd.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOPocr.demand_data_rd.l3_hit_s.hitm_other_coreCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_COREocr.demand_data_rd.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_hit_s.hit_other_core_no_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_hit_s.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_hit_s.snoop_missocr.demand_data_rd.l3_hit_s.snoop_noneocr.demand_rfo.l3_hit.any_snoopCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOPocr.demand_rfo.l3_hit.hitm_other_coreCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_COREocr.demand_rfo.l3_hit.hit_other_core_fwdCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit.hit_other_core_no_fwdCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit.no_snoop_neededCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDEDocr.demand_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0002ocr.demand_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0002Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISSocr.demand_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0002Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONEocr.demand_rfo.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOPocr.demand_rfo.l3_hit_e.hitm_other_coreCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_COREocr.demand_rfo.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_e.hit_other_core_no_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit_e.no_snoop_neededCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDEDocr.demand_rfo.l3_hit_e.snoop_missocr.demand_rfo.l3_hit_e.snoop_noneocr.demand_rfo.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOPocr.demand_rfo.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_COREocr.demand_rfo.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDEDocr.demand_rfo.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200002ocr.demand_rfo.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200002ocr.demand_rfo.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOPocr.demand_rfo.l3_hit_m.hitm_other_coreCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_COREocr.demand_rfo.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_m.hit_other_core_no_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit_m.no_snoop_neededCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDEDocr.demand_rfo.l3_hit_m.snoop_missocr.demand_rfo.l3_hit_m.snoop_noneocr.demand_rfo.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOPocr.demand_rfo.l3_hit_s.hitm_other_coreCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_COREocr.demand_rfo.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_hit_s.hit_other_core_no_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_hit_s.no_snoop_neededCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDEDocr.demand_rfo.l3_hit_s.snoop_missocr.demand_rfo.l3_hit_s.snoop_noneocr.other.l3_hit.any_snoopCounts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOPocr.other.l3_hit.hitm_other_coreCounts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_COREocr.other.l3_hit.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C8000Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWDocr.other.l3_hit.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C8000Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.other.l3_hit.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C8000Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDEDocr.other.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C8000ocr.other.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C8000Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISSocr.other.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C8000Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONEocr.other.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80088000Counts any other requests  OCR.OTHER.L3_HIT_E.ANY_SNOOPocr.other.l3_hit_e.hitm_other_coreCounts any other requests  OCR.OTHER.L3_HIT_E.HITM_OTHER_COREocr.other.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800088000Counts any other requests  OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWDocr.other.l3_hit_e.hit_other_core_no_fwdCounts any other requests  OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_e.no_snoop_neededCounts any other requests  OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDEDocr.other.l3_hit_e.snoop_missocr.other.l3_hit_e.snoop_noneocr.other.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80208000Counts any other requests  OCR.OTHER.L3_HIT_F.ANY_SNOOPocr.other.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000208000Counts any other requests  OCR.OTHER.L3_HIT_F.HITM_OTHER_COREocr.other.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800208000Counts any other requests  OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWDocr.other.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400208000Counts any other requests  OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100208000Counts any other requests  OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDEDocr.other.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200208000ocr.other.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80208000ocr.other.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80048000Counts any other requests  OCR.OTHER.L3_HIT_M.ANY_SNOOPocr.other.l3_hit_m.hitm_other_coreCounts any other requests  OCR.OTHER.L3_HIT_M.HITM_OTHER_COREocr.other.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800048000Counts any other requests  OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWDocr.other.l3_hit_m.hit_other_core_no_fwdCounts any other requests  OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_m.no_snoop_neededCounts any other requests  OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDEDocr.other.l3_hit_m.snoop_missocr.other.l3_hit_m.snoop_noneocr.other.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80108000Counts any other requests  OCR.OTHER.L3_HIT_S.ANY_SNOOPocr.other.l3_hit_s.hitm_other_coreCounts any other requests  OCR.OTHER.L3_HIT_S.HITM_OTHER_COREocr.other.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800108000Counts any other requests  OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWDocr.other.l3_hit_s.hit_other_core_no_fwdCounts any other requests  OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.other.l3_hit_s.no_snoop_neededCounts any other requests  OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDEDocr.other.l3_hit_s.snoop_missocr.other.l3_hit_s.snoop_noneocr.pf_l1d_and_sw.l3_hit.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOPocr.pf_l1d_and_sw.l3_hit.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0400Counts L1 data cache hardware prefetch requests and software prefetch requestsocr.pf_l1d_and_sw.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0400Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISSocr.pf_l1d_and_sw.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0400Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONEocr.pf_l1d_and_sw.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080400ocr.pf_l1d_and_sw.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080400ocr.pf_l1d_and_sw.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200400ocr.pf_l1d_and_sw.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200400ocr.pf_l1d_and_sw.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040400ocr.pf_l1d_and_sw.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040400ocr.pf_l1d_and_sw.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOPocr.pf_l1d_and_sw.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100400ocr.pf_l1d_and_sw.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100400ocr.pf_l2_data_rd.l3_hit.any_snoopCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOPocr.pf_l2_data_rd.l3_hit.hitm_other_coreCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit.no_snoop_neededCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0010ocr.pf_l2_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0010Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISSocr.pf_l2_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0010Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONEocr.pf_l2_data_rd.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOPocr.pf_l2_data_rd.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080010ocr.pf_l2_data_rd.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080010ocr.pf_l2_data_rd.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOPocr.pf_l2_data_rd.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200010ocr.pf_l2_data_rd.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200010ocr.pf_l2_data_rd.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOPocr.pf_l2_data_rd.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040010ocr.pf_l2_data_rd.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040010ocr.pf_l2_data_rd.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOPocr.pf_l2_data_rd.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_COREocr.pf_l2_data_rd.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100010ocr.pf_l2_data_rd.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100010ocr.pf_l2_rfo.l3_hit.any_snoopCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOPocr.pf_l2_rfo.l3_hit.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_hit.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0020ocr.pf_l2_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISSocr.pf_l2_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONEocr.pf_l2_rfo.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOPocr.pf_l2_rfo.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080020ocr.pf_l2_rfo.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080020ocr.pf_l2_rfo.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOPocr.pf_l2_rfo.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200020ocr.pf_l2_rfo.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200020ocr.pf_l2_rfo.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOPocr.pf_l2_rfo.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040020ocr.pf_l2_rfo.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040020ocr.pf_l2_rfo.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOPocr.pf_l2_rfo.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_COREocr.pf_l2_rfo.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100020ocr.pf_l2_rfo.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100020ocr.pf_l3_data_rd.l3_hit.any_snoopCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOPocr.pf_l3_data_rd.l3_hit.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_hit.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0080ocr.pf_l3_data_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISSocr.pf_l3_data_rd.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONEocr.pf_l3_data_rd.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOPocr.pf_l3_data_rd.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080080ocr.pf_l3_data_rd.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080080ocr.pf_l3_data_rd.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOPocr.pf_l3_data_rd.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200080ocr.pf_l3_data_rd.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200080ocr.pf_l3_data_rd.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOPocr.pf_l3_data_rd.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040080ocr.pf_l3_data_rd.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040080ocr.pf_l3_data_rd.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOPocr.pf_l3_data_rd.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_COREocr.pf_l3_data_rd.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100080ocr.pf_l3_data_rd.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100080ocr.pf_l3_rfo.l3_hit.any_snoopCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOPocr.pf_l3_rfo.l3_hit.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_COREocr.pf_l3_rfo.l3_hit.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8007C0100ocr.pf_l3_rfo.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0100Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISSocr.pf_l3_rfo.l3_hit.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x803C0100Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONEocr.pf_l3_rfo.l3_hit_e.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80080100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOPocr.pf_l3_rfo.l3_hit_e.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000080100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_e.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800080100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400080100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_e.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100080100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_e.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200080100ocr.pf_l3_rfo.l3_hit_e.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080100ocr.pf_l3_rfo.l3_hit_f.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80200100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOPocr.pf_l3_rfo.l3_hit_f.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000200100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_f.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800200100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400200100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_f.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100200100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_f.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200200100ocr.pf_l3_rfo.l3_hit_f.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80200100ocr.pf_l3_rfo.l3_hit_m.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80040100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOPocr.pf_l3_rfo.l3_hit_m.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000040100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_m.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800040100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400040100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_m.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100040100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_m.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200040100ocr.pf_l3_rfo.l3_hit_m.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80040100ocr.pf_l3_rfo.l3_hit_s.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80100100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOPocr.pf_l3_rfo.l3_hit_s.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000100100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_COREocr.pf_l3_rfo.l3_hit_s.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800100100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400100100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_hit_s.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100100100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_hit_s.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200100100ocr.pf_l3_rfo.l3_hit_s.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80100100This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOPoffcore_response.all_data_rd.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISSoffcore_response.all_data_rd.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.all_data_rd.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.all_data_rd.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.all_data_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISSoffcore_response.all_data_rd.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONEoffcore_response.all_data_rd.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.all_data_rd.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_data_rd.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISSoffcore_response.all_data_rd.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.all_data_rd.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_data_rd.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.all_data_rd.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_data_rd.supplier_none.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_data_rd.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISSevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020491This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONEoffcore_response.all_pf_data_rd.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.all_pf_data_rd.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_pf_data_rd.supplier_none.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_pf_data_rd.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISSevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020490This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONEoffcore_response.all_pf_rfo.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISSoffcore_response.all_pf_rfo.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONEoffcore_response.all_pf_rfo.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.all_pf_rfo.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.all_pf_rfo.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISSoffcore_response.all_pf_rfo.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.all_pf_rfo.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.all_pf_rfo.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISSoffcore_response.all_pf_rfo.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.all_pf_rfo.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.all_pf_rfo.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_pf_rfo.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_pf_rfo.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISSevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020120This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONEevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x107F7This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSEoffcore_response.all_reads.l3_hit.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_COREoffcore_response.all_reads.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_hit.snoop_hit_with_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.all_reads.l3_hit.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISSoffcore_response.all_reads.l3_hit.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONEoffcore_response.all_reads.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOPoffcore_response.all_reads.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_COREoffcore_response.all_reads.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISSoffcore_response.all_reads.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONEoffcore_response.all_reads.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOPoffcore_response.all_reads.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_reads.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISSoffcore_response.all_reads.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONEoffcore_response.all_reads.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOPoffcore_response.all_reads.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_reads.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISSoffcore_response.all_reads.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONEoffcore_response.all_reads.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOPoffcore_response.all_reads.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_reads.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISSoffcore_response.all_reads.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONEoffcore_response.all_reads.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F804007F7This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_reads.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804007F7This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.all_reads.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004007F7This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.all_reads.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F800207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_reads.supplier_none.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_reads.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.all_reads.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.all_reads.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISSoffcore_response.all_reads.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800207F7This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONEoffcore_response.all_rfo.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOPoffcore_response.all_rfo.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISSoffcore_response.all_rfo.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONEoffcore_response.all_rfo.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.all_rfo.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.all_rfo.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.all_rfo.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.all_rfo.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISSoffcore_response.all_rfo.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.all_rfo.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.all_rfo.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_COREoffcore_response.all_rfo.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISSoffcore_response.all_rfo.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.all_rfo.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400122This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.all_rfo.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400122This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.all_rfo.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400122This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.all_rfo.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.all_rfo.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISSevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020122This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOPoffcore_response.demand_code_rd.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONEoffcore_response.demand_code_rd.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOPoffcore_response.demand_code_rd.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISSoffcore_response.demand_code_rd.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOPoffcore_response.demand_code_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOPoffcore_response.demand_code_rd.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONEoffcore_response.demand_code_rd.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.demand_code_rd.pmm_hit_local_pmm.snoop_not_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.demand_code_rd.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.demand_code_rd.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020004This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOPoffcore_response.demand_data_rd.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.demand_data_rd.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.demand_data_rd.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.demand_data_rd.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.demand_data_rd.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.demand_data_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.demand_data_rd.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.demand_data_rd.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.demand_data_rd.pmm_hit_local_pmm.snoop_not_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.demand_data_rd.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.demand_data_rd.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020001This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOPoffcore_response.demand_rfo.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONEoffcore_response.demand_rfo.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.demand_rfo.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.demand_rfo.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.demand_rfo.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.demand_rfo.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.demand_rfo.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_COREoffcore_response.demand_rfo.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.demand_rfo.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400002This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.demand_rfo.pmm_hit_local_pmm.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.demand_rfo.pmm_hit_local_pmm.snoop_not_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.demand_rfo.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.demand_rfo.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020002This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOPoffcore_response.other.l3_hit.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_COREoffcore_response.other.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_hit.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDEDoffcore_response.other.l3_hit.snoop_hit_with_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONEThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOPoffcore_response.other.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_COREoffcore_response.other.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONEoffcore_response.other.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOPoffcore_response.other.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_COREoffcore_response.other.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.other.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISSoffcore_response.other.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONEThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOPoffcore_response.other.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_COREoffcore_response.other.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONEThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOPoffcore_response.other.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_COREoffcore_response.other.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.other.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONEoffcore_response.other.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80408000This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.other.pmm_hit_local_pmm.snoop_noneThis event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.other.pmm_hit_local_pmm.snoop_not_neededThis event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOPoffcore_response.other.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.other.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800028000This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.other.supplier_none.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.other.supplier_none.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWDoffcore_response.pf_l1d_and_sw.l3_hit.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDoffcore_response.pf_l1d_and_sw.supplier_none.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l1d_and_sw.supplier_none.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.supplier_none.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISSoffcore_response.pf_l1d_and_sw.supplier_none.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020400This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONEoffcore_response.pf_l2_data_rd.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l2_data_rd.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l2_data_rd.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONEoffcore_response.pf_l2_data_rd.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l2_data_rd.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l2_data_rd.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISSevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020010This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISSoffcore_response.pf_l2_rfo.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l2_rfo.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l2_rfo.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.pf_l2_rfo.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l2_rfo.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l2_rfo.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400020This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400020This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400020This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l2_rfo.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.pf_l2_rfo.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISSevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020020This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONEoffcore_response.pf_l3_data_rd.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l3_data_rd.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l3_data_rd.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISSevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020080This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOPThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_hit_e.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_e.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_e.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_hit_e.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_hit_e.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_e.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_hit_f.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_f.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_f.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_hit_f.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_hit_f.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_f.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_hit_m.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_m.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_m.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_hit_m.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_hit_m.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_m.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONEoffcore_response.pf_l3_rfo.l3_hit_s.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_hit_s.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_hit_s.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_hit_s.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_hit_s.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_hit_s.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONEoffcore_response.pf_l3_rfo.pmm_hit_local_pmm.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F80400100This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPoffcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80400100This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEoffcore_response.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400100This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOPoffcore_response.pf_l3_rfo.supplier_none.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_COREoffcore_response.pf_l3_rfo.supplier_none.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.supplier_none.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.supplier_none.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISSevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80020100This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONEclx metrics100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (OFFCORE_REQUESTS_BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) 100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) )100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\,cmask\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\,cmask\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) )Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)LSD_CoverageFed;LSDIDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches( 1000000000 * ( imc@event\=0xe0\,umask\=0x1@ / imc@event\=0xe3@ ) / imc_0@event\=0x0@ )MEM_PMM_Read_LatencyAverage 3DXP Memory Bandwidth Use for reads [GB / sec]( ( 64 * imc@event\=0xe3@ / 1000000000 ) / duration_time )PMM_Read_BWMem;MemoryBW;SoC;ServerAverage 3DXP Memory Bandwidth Use for Writes [GB / sec]( ( 64 * imc@event\=0xe7@ / 1000000000 ) / duration_time )PMM_Write_BWNumber of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.  The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsNumber of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsfp_arith_inst_retired2.128bit_packed_bf16event=0xcf,period=2000003,umask=0x20Intel AVX-512 computational 512-bit packed BFloat16 instructions retiredCounts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction.  Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lakefp_arith_inst_retired2.256bit_packed_bf16event=0xcf,period=2000003,umask=0x40Intel AVX-512 computational 128-bit packed BFloat16 instructions retiredCounts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lakefp_arith_inst_retired2.512bit_packed_bf16event=0xcf,period=2000003,umask=0x80Intel AVX-512 computational 256-bit packed BFloat16 instructions retiredCounts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction.  Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lakeocr.all_data_rd.l3_miss.any_snoopOCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOPocr.all_data_rd.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000491OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_COREocr.all_data_rd.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000491OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000491OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000491OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.all_data_rd.l3_miss.remote_hitmOCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITMocr.all_data_rd.l3_miss.remote_hit_forwardOCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDocr.all_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000491OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISSocr.all_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000491OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONEocr.all_data_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000491OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_data_rd.l3_miss_local_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000491OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.all_data_rd.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000491OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000491OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000491OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.all_data_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000491OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdOCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_data_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000491OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.all_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdOCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_data_rd.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_data_rd.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000491OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.all_pf_data_rd.l3_miss.any_snoopOCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOPocr.all_pf_data_rd.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000490OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_COREocr.all_pf_data_rd.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000490OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000490OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000490OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_miss.remote_hitmOCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITMocr.all_pf_data_rd.l3_miss.remote_hit_forwardOCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDocr.all_pf_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000490OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISSocr.all_pf_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000490OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONEocr.all_pf_data_rd.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000490OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_pf_data_rd.l3_miss_local_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000490OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000490OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000490OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000490OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000490OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_pf_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdOCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_pf_data_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000490OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.all_pf_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdOCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000490OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000490OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000490OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000490OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000490OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000490OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000490OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.all_pf_rfo.l3_miss.any_snoopOCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOPocr.all_pf_rfo.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000120OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_COREocr.all_pf_rfo.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000120OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000120OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000120OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_miss.remote_hitmOCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITMocr.all_pf_rfo.l3_miss.remote_hit_forwardOCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.all_pf_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000120OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISSocr.all_pf_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000120OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONEocr.all_pf_rfo.l3_miss_local_dram.any_snoopOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_pf_rfo.l3_miss_local_dram.hitm_other_coreOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000120OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000120OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000120OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000120OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_pf_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdOCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_pf_rfo.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000120OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.all_pf_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdOCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000120OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.all_reads.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC0007F7OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOPocr.all_reads.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C0007F7OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_COREocr.all_reads.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C0007F7OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWDocr.all_reads.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C0007F7OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C0007F7OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDEDocr.all_reads.l3_miss.remote_hitmOCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITMocr.all_reads.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC007F7OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARDocr.all_reads.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C0007F7OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISSocr.all_reads.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC0007F7OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONEocr.all_reads.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F840007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_reads.l3_miss_local_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10040007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.all_reads.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8040007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.all_reads.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4040007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1040007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.all_reads.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2040007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x6040007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_reads.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x840007F7OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B8007F7OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_reads.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F900007F7OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_reads.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10100007F7OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8100007F7OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4100007F7OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_reads.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1100007F7OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_reads.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2100007F7OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_reads.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x900007F7OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.all_rfo.l3_miss.any_snoopOCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOPocr.all_rfo.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000122OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_COREocr.all_rfo.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000122OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.all_rfo.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000122OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000122OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.all_rfo.l3_miss.remote_hitmOCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITMocr.all_rfo.l3_miss.remote_hit_forwardOCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.all_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000122OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISSocr.all_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000122OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONEocr.all_rfo.l3_miss_local_dram.any_snoopOCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.all_rfo.l3_miss_local_dram.hitm_other_coreOCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.all_rfo.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000122OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.all_rfo.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000122OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000122OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.all_rfo.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000122OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSocr.all_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdOCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_rfo.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000122OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEocr.all_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdOCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.all_rfo.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.all_rfo.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.all_rfo.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED  OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.all_rfo.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSocr.all_rfo.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000122OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.demand_code_rd.l3_miss.any_snoopCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOPocr.demand_code_rd.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000004Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_COREocr.demand_code_rd.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000004Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000004Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000004Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_miss.remote_hitmCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITMocr.demand_code_rd.l3_miss.remote_hit_forwardCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARDocr.demand_code_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000004Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISSocr.demand_code_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000004Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONEocr.demand_code_rd.l3_miss_local_dram.any_snoopCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.demand_code_rd.l3_miss_local_dram.hitm_other_coreCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.demand_code_rd.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss_local_dram.no_snoop_neededCounts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_miss_local_dram.snoop_missocr.demand_code_rd.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_code_rd.l3_miss_local_dram.snoop_noneocr.demand_code_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_code_rd.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000004Counts all demand code reads  OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000004ocr.demand_code_rd.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000004ocr.demand_data_rd.l3_miss.any_snoopCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOPocr.demand_data_rd.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000001Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_COREocr.demand_data_rd.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000001Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000001Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000001Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_miss.remote_hitmCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITMocr.demand_data_rd.l3_miss.remote_hit_forwardCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDocr.demand_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000001Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISSocr.demand_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000001Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONEocr.demand_data_rd.l3_miss_local_dram.any_snoopCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.demand_data_rd.l3_miss_local_dram.hitm_other_coreCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.demand_data_rd.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_miss_local_dram.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_miss_local_dram.snoop_missocr.demand_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_data_rd.l3_miss_local_dram.snoop_noneocr.demand_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_data_rd.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000001Counts demand data reads  OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000001ocr.demand_data_rd.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000001ocr.demand_rfo.l3_miss.any_snoopCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOPocr.demand_rfo.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000002Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_COREocr.demand_rfo.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000002Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000002Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000002Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.demand_rfo.l3_miss.remote_hitmCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITMocr.demand_rfo.l3_miss.remote_hit_forwardCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.demand_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000002Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISSocr.demand_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000002Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONEocr.demand_rfo.l3_miss_local_dram.any_snoopCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.demand_rfo.l3_miss_local_dram.hitm_other_coreCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.demand_rfo.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_miss_local_dram.no_snoop_neededCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.demand_rfo.l3_miss_local_dram.snoop_missocr.demand_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_rfo.l3_miss_local_dram.snoop_noneocr.demand_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.demand_rfo.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000002Counts all demand data writes (RFOs)  OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000002ocr.demand_rfo.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000002ocr.other.l3_miss.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBC008000Counts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOPocr.other.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C008000Counts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_COREocr.other.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C008000Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWDocr.other.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C008000Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.other.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C008000Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDEDocr.other.l3_miss.remote_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103FC08000Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HITMocr.other.l3_miss.remote_hit_forwardevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83FC08000Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARDocr.other.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C008000Counts any other requests OCR.OTHER.L3_MISS.SNOOP_MISSocr.other.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC008000Counts any other requests OCR.OTHER.L3_MISS.SNOOP_NONEocr.other.l3_miss_local_dram.any_snoopCounts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.other.l3_miss_local_dram.hitm_other_coreCounts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.other.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804008000Counts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.other.l3_miss_local_dram.hit_other_core_no_fwdCounts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.other.l3_miss_local_dram.no_snoop_neededCounts any other requests  OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.other.l3_miss_local_dram.snoop_missocr.other.l3_miss_local_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x604008000Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.other.l3_miss_local_dram.snoop_noneocr.other.l3_miss_remote_dram.snoop_miss_or_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x63B808000Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.other.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90008000Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.other.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010008000Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.other.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810008000Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410008000Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.other.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110008000Counts any other requests  OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.other.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210008000ocr.other.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90008000ocr.pf_l1d_and_sw.l3_miss.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOPocr.pf_l1d_and_sw.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000400Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000400Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000400Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000400Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_miss.remote_hitmCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITMocr.pf_l1d_and_sw.l3_miss.remote_hit_forwardCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l1d_and_sw.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000400Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISSocr.pf_l1d_and_sw.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000400Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONEocr.pf_l1d_and_sw.l3_miss_local_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000400ocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_miss_or_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l1d_and_sw.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000400ocr.pf_l1d_and_sw.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000400Counts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000400ocr.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000400ocr.pf_l2_data_rd.l3_miss.any_snoopCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOPocr.pf_l2_data_rd.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000010Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_COREocr.pf_l2_data_rd.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000010Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000010Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000010Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_miss.remote_hitmCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITMocr.pf_l2_data_rd.l3_miss.remote_hit_forwardCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l2_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000010Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISSocr.pf_l2_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000010Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONEocr.pf_l2_data_rd.l3_miss_local_dram.any_snoopCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.pf_l2_data_rd.l3_miss_local_dram.hitm_other_coreCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000010ocr.pf_l2_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l2_data_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000010ocr.pf_l2_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000010Counts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000010ocr.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000010ocr.pf_l2_rfo.l3_miss.any_snoopCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOPocr.pf_l2_rfo.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_COREocr.pf_l2_rfo.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss.remote_hitmCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITMocr.pf_l2_rfo.l3_miss.remote_hit_forwardCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l2_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISSocr.pf_l2_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000020Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONEocr.pf_l2_rfo.l3_miss_local_dram.any_snoopCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.pf_l2_rfo.l3_miss_local_dram.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000020ocr.pf_l2_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l2_rfo.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000020ocr.pf_l2_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000020Counts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000020ocr.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000020ocr.pf_l3_data_rd.l3_miss.any_snoopCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOPocr.pf_l3_data_rd.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_COREocr.pf_l3_data_rd.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_miss.remote_hitmCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITMocr.pf_l3_data_rd.l3_miss.remote_hit_forwardCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l3_data_rd.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISSocr.pf_l3_data_rd.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000080Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONEocr.pf_l3_data_rd.l3_miss_local_dram.any_snoopCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.pf_l3_data_rd.l3_miss_local_dram.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000080ocr.pf_l3_data_rd.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l3_data_rd.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000080ocr.pf_l3_data_rd.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000080Counts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000080ocr.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000080ocr.pf_l3_rfo.l3_miss.any_snoopCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOPocr.pf_l3_rfo.l3_miss.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x103C000100Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_COREocr.pf_l3_rfo.l3_miss.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x83C000100Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_miss.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x43C000100Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_miss.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x13C000100Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_miss.remote_hitmCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITMocr.pf_l3_rfo.l3_miss.remote_hit_forwardCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARDocr.pf_l3_rfo.l3_miss.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x23C000100Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISSocr.pf_l3_rfo.l3_miss.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0xBC000100Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONEocr.pf_l3_rfo.l3_miss_local_dram.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPocr.pf_l3_rfo.l3_miss_local_dram.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x804000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x404000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_miss_local_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_miss_local_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x204000100ocr.pf_l3_rfo.l3_miss_local_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l3_rfo.l3_miss_local_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000100ocr.pf_l3_rfo.l3_miss_remote_dram.snoop_miss_or_no_fwdCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoopevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F90000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x810000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x410000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x110000100Counts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x210000100ocr.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_noneevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90000100This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOPoffcore_response.all_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_COREoffcore_response.all_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.all_data_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.all_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.all_pf_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOPoffcore_response.all_pf_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.all_pf_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.all_pf_rfo.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEoffcore_response.all_reads.l3_miss.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOPoffcore_response.all_reads.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_COREoffcore_response.all_reads.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_miss.remote_hitmThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITMoffcore_response.all_reads.l3_miss.remote_hit_forwardThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.all_reads.l3_miss.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISSoffcore_response.all_reads.l3_miss.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONEoffcore_response.all_reads.l3_miss_local_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.all_reads.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.all_reads.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_miss_local_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.all_reads.l3_miss_local_dram.snoop_miss_or_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_reads.l3_miss_local_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.all_reads.l3_miss_remote_dram.snoop_miss_or_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_reads.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.all_reads.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_reads.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_reads.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.all_reads.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOPoffcore_response.all_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.all_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.all_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.all_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.all_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.all_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.all_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.all_rfo.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.all_rfo.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOPoffcore_response.demand_code_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.demand_code_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.demand_code_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOPoffcore_response.demand_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.demand_data_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.demand_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOPoffcore_response.demand_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.demand_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.demand_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.demand_rfo.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOPoffcore_response.other.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_COREoffcore_response.other.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.other.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDEDoffcore_response.other.l3_miss.remote_hitmThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITMoffcore_response.other.l3_miss.remote_hit_forwardThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.other.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.other.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.other.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISSoffcore_response.other.l3_miss_local_dram.snoop_miss_or_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONEoffcore_response.other.l3_miss_remote_dram.snoop_miss_or_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.other.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.other.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.other.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.other.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.other.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.other.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARDoffcore_response.pf_l1d_and_sw.l3_miss.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_miss.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONEoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_local_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l1d_and_sw.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l2_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l2_rfo.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l3_data_rd.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_miss.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_miss.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_miss.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_miss.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITMThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_miss_local_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_miss_local_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_miss_local_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDEDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISSThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWDThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONEThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWDoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.any_snoopThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOPoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hitm_other_coreThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_COREoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWDoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.hit_other_core_no_fwdThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWDoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.no_snoop_neededThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDEDoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_missThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISSoffcore_response.pf_l3_rfo.l3_miss_remote_hop1_dram.snoop_noneThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONEocr.all_data_rd.any_responseOCR.ALL_DATA_RD.ANY_RESPONSE have any response typeocr.all_data_rd.pmm_hit_local_pmm.any_snoopOCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_data_rd.pmm_hit_local_pmm.snoop_noneOCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.all_data_rd.pmm_hit_local_pmm.snoop_not_neededOCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_data_rd.supplier_none.any_snoopOCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOPocr.all_data_rd.supplier_none.hitm_other_coreOCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREocr.all_data_rd.supplier_none.hit_other_core_fwdOCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.all_data_rd.supplier_none.hit_other_core_no_fwdOCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.all_data_rd.supplier_none.no_snoop_neededOCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.all_data_rd.supplier_none.snoop_missOCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISSocr.all_data_rd.supplier_none.snoop_noneOCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONEocr.all_pf_data_rd.any_responseOCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response typeocr.all_pf_data_rd.pmm_hit_local_pmm.any_snoopOCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_noneOCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.all_pf_data_rd.pmm_hit_local_pmm.snoop_not_neededOCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_pf_data_rd.supplier_none.any_snoopOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOPocr.all_pf_data_rd.supplier_none.hitm_other_coreOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREocr.all_pf_data_rd.supplier_none.hit_other_core_fwdOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.all_pf_data_rd.supplier_none.hit_other_core_no_fwdOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.all_pf_data_rd.supplier_none.no_snoop_neededOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.all_pf_data_rd.supplier_none.snoop_missOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISSocr.all_pf_data_rd.supplier_none.snoop_noneOCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONEocr.all_pf_rfo.any_responseOCR.ALL_PF_RFO.ANY_RESPONSE have any response typeocr.all_pf_rfo.pmm_hit_local_pmm.any_snoopOCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_pf_rfo.pmm_hit_local_pmm.snoop_noneOCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.all_pf_rfo.pmm_hit_local_pmm.snoop_not_neededOCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_pf_rfo.supplier_none.any_snoopOCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOPocr.all_pf_rfo.supplier_none.hitm_other_coreOCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_COREocr.all_pf_rfo.supplier_none.hit_other_core_fwdOCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.all_pf_rfo.supplier_none.hit_other_core_no_fwdOCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.all_pf_rfo.supplier_none.no_snoop_neededOCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.all_pf_rfo.supplier_none.snoop_missOCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISSocr.all_pf_rfo.supplier_none.snoop_noneOCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONEocr.all_reads.any_responseOCR.ALL_READS.ANY_RESPONSE have any response typeocr.all_reads.pmm_hit_local_pmm.any_snoopOCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_reads.pmm_hit_local_pmm.snoop_noneOCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.all_reads.pmm_hit_local_pmm.snoop_not_neededOCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_reads.supplier_none.any_snoopOCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOPocr.all_reads.supplier_none.hitm_other_coreOCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_COREocr.all_reads.supplier_none.hit_other_core_fwdOCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.all_reads.supplier_none.hit_other_core_no_fwdOCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.all_reads.supplier_none.no_snoop_neededOCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.all_reads.supplier_none.snoop_missOCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISSocr.all_reads.supplier_none.snoop_noneOCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONEocr.all_rfo.any_responseOCR.ALL_RFO.ANY_RESPONSE have any response typeocr.all_rfo.pmm_hit_local_pmm.any_snoopOCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.all_rfo.pmm_hit_local_pmm.snoop_noneOCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.all_rfo.pmm_hit_local_pmm.snoop_not_neededOCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.all_rfo.supplier_none.any_snoopOCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP  OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOPocr.all_rfo.supplier_none.hitm_other_coreOCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE  OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_COREocr.all_rfo.supplier_none.hit_other_core_fwdOCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD  OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.all_rfo.supplier_none.hit_other_core_no_fwdOCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD  OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.all_rfo.supplier_none.no_snoop_neededOCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED  OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.all_rfo.supplier_none.snoop_missOCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISSocr.all_rfo.supplier_none.snoop_noneOCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONEocr.demand_code_rd.any_responseocr.demand_code_rd.pmm_hit_local_pmm.any_snoopCounts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.demand_code_rd.pmm_hit_local_pmm.snoop_noneCounts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.demand_code_rd.pmm_hit_local_pmm.snoop_not_neededCounts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.demand_code_rd.supplier_none.any_snoopCounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOPocr.demand_code_rd.supplier_none.hitm_other_coreCounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_COREocr.demand_code_rd.supplier_none.hit_other_core_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.demand_code_rd.supplier_none.hit_other_core_no_fwdCounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.demand_code_rd.supplier_none.no_snoop_neededCounts all demand code reads  OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.demand_code_rd.supplier_none.snoop_missocr.demand_code_rd.supplier_none.snoop_noneocr.demand_data_rd.any_responseocr.demand_data_rd.pmm_hit_local_pmm.any_snoopCounts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.demand_data_rd.pmm_hit_local_pmm.snoop_noneCounts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.demand_data_rd.pmm_hit_local_pmm.snoop_not_neededCounts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.demand_data_rd.supplier_none.any_snoopCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOPocr.demand_data_rd.supplier_none.hitm_other_coreCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREocr.demand_data_rd.supplier_none.hit_other_core_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.demand_data_rd.supplier_none.hit_other_core_no_fwdCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.demand_data_rd.supplier_none.no_snoop_neededCounts demand data reads  OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.demand_data_rd.supplier_none.snoop_missocr.demand_data_rd.supplier_none.snoop_noneocr.demand_rfo.any_responseocr.demand_rfo.pmm_hit_local_pmm.any_snoopCounts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.demand_rfo.pmm_hit_local_pmm.snoop_noneCounts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.demand_rfo.pmm_hit_local_pmm.snoop_not_neededCounts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.demand_rfo.supplier_none.any_snoopCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOPocr.demand_rfo.supplier_none.hitm_other_coreCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_COREocr.demand_rfo.supplier_none.hit_other_core_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.demand_rfo.supplier_none.hit_other_core_no_fwdCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.demand_rfo.supplier_none.no_snoop_neededCounts all demand data writes (RFOs)  OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.demand_rfo.supplier_none.snoop_missocr.demand_rfo.supplier_none.snoop_noneocr.other.any_responseocr.other.pmm_hit_local_pmm.any_snoopCounts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.other.pmm_hit_local_pmm.snoop_noneCounts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.other.pmm_hit_local_pmm.snoop_not_neededCounts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.other.supplier_none.any_snoopCounts any other requests  OCR.OTHER.SUPPLIER_NONE.ANY_SNOOPocr.other.supplier_none.hitm_other_coreCounts any other requests  OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_COREocr.other.supplier_none.hit_other_core_fwdCounts any other requests  OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.other.supplier_none.hit_other_core_no_fwdCounts any other requests  OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.other.supplier_none.no_snoop_neededCounts any other requests  OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.other.supplier_none.snoop_missocr.other.supplier_none.snoop_noneocr.pf_l1d_and_sw.any_responseCounts L1 data cache hardware prefetch requests and software prefetch requests have any response typeocr.pf_l1d_and_sw.pmm_hit_local_pmm.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_noneCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.pf_l1d_and_sw.pmm_hit_local_pmm.snoop_not_neededCounts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.pf_l1d_and_sw.supplier_none.any_snoopCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOPocr.pf_l1d_and_sw.supplier_none.hitm_other_coreCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_COREocr.pf_l1d_and_sw.supplier_none.hit_other_core_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.pf_l1d_and_sw.supplier_none.hit_other_core_no_fwdCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.pf_l1d_and_sw.supplier_none.no_snoop_neededCounts L1 data cache hardware prefetch requests and software prefetch requests  OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l1d_and_sw.supplier_none.snoop_missocr.pf_l1d_and_sw.supplier_none.snoop_noneocr.pf_l2_data_rd.any_responseocr.pf_l2_data_rd.pmm_hit_local_pmm.any_snoopCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_noneCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.pf_l2_data_rd.pmm_hit_local_pmm.snoop_not_neededCounts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.pf_l2_data_rd.supplier_none.any_snoopCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOPocr.pf_l2_data_rd.supplier_none.hitm_other_coreCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREocr.pf_l2_data_rd.supplier_none.hit_other_core_fwdCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.pf_l2_data_rd.supplier_none.hit_other_core_no_fwdCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.pf_l2_data_rd.supplier_none.no_snoop_neededCounts prefetch (that bring data to L2) data reads  OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l2_data_rd.supplier_none.snoop_missocr.pf_l2_data_rd.supplier_none.snoop_noneocr.pf_l2_rfo.any_responseocr.pf_l2_rfo.pmm_hit_local_pmm.any_snoopCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_noneCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.pf_l2_rfo.pmm_hit_local_pmm.snoop_not_neededCounts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.pf_l2_rfo.supplier_none.any_snoopCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOPocr.pf_l2_rfo.supplier_none.hitm_other_coreCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_COREocr.pf_l2_rfo.supplier_none.hit_other_core_fwdCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.pf_l2_rfo.supplier_none.hit_other_core_no_fwdCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.pf_l2_rfo.supplier_none.no_snoop_neededCounts all prefetch (that bring data to L2) RFOs  OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l2_rfo.supplier_none.snoop_missocr.pf_l2_rfo.supplier_none.snoop_noneocr.pf_l3_data_rd.any_responseocr.pf_l3_data_rd.pmm_hit_local_pmm.any_snoopCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_noneCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.pf_l3_data_rd.pmm_hit_local_pmm.snoop_not_neededCounts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.pf_l3_data_rd.supplier_none.any_snoopCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOPocr.pf_l3_data_rd.supplier_none.hitm_other_coreCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_COREocr.pf_l3_data_rd.supplier_none.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.pf_l3_data_rd.supplier_none.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.pf_l3_data_rd.supplier_none.no_snoop_neededCounts all prefetch (that bring data to LLC only) data reads  OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l3_data_rd.supplier_none.snoop_missocr.pf_l3_data_rd.supplier_none.snoop_noneocr.pf_l3_rfo.any_responseocr.pf_l3_rfo.pmm_hit_local_pmm.any_snoopCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOPocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_noneCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONEocr.pf_l3_rfo.pmm_hit_local_pmm.snoop_not_neededCounts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDEDocr.pf_l3_rfo.supplier_none.any_snoopCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOPocr.pf_l3_rfo.supplier_none.hitm_other_coreCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_COREocr.pf_l3_rfo.supplier_none.hit_other_core_fwdCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWDocr.pf_l3_rfo.supplier_none.hit_other_core_no_fwdCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWDocr.pf_l3_rfo.supplier_none.no_snoop_neededCounts all prefetch (that bring data to LLC only) RFOs  OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDEDocr.pf_l3_rfo.supplier_none.snoop_missocr.pf_l3_rfo.supplier_none.snoop_noneCycles where DRAM ranks are in power down (CKE) mode+C37. Unit: uncore_imc unc_m_pmm_rpq_insertsevent=0xe3Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_pmm_wpq_insertsevent=0xe7unc_m_pmm_bandwidth.readIntel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc 6.103515625E-5MB/secIntel Optane DC persistent memory bandwidth read (MB/sec). Unit: uncore_imc unc_m_pmm_bandwidth.writeIntel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts. Unit: uncore_imc Intel Optane DC persistent memory bandwidth write (MB/sec). Unit: uncore_imc unc_m_pmm_bandwidth.totalIntel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts. Unit: uncore_imc UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTSUNC_M_PMM_BANDWIDTH.TOTALIntel Optane DC persistent memory bandwidth total (MB/sec). Unit: uncore_imc unc_m_pmm_rpq_occupancy.allevent=0xe0,umask=0x1Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory. Unit: uncore_imc unc_m_pmm_read_latencyIntel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all. Unit: uncore_imc 6000000000nsUNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKSUNC_M_PMM_READ_LATENCYIntel Optane DC persistent memory read latency (ns). Unit: uncore_imc unc_m_pmm_cmd1.allevent=0xea,umask=0x1All commands for Intel Optane DC persistent memory. Unit: uncore_imc All commands for Intel Optane DC persistent memoryunc_m_pmm_cmd1.rdevent=0xea,umask=0x2Regular reads(RPQ) commands for Intel Optane DC persistent memory. Unit: uncore_imc All Reads - RPQ or Ufillunc_m_pmm_cmd1.ufill_rdevent=0xea,umask=0x8Underfill read commands for Intel Optane DC persistent memory. Unit: uncore_imc Underfill readsunc_m_pmm_cmd1.wrevent=0xea,umask=0x4Write commands for Intel Optane DC persistent memory. Unit: uncore_imc Writesunc_m_pmm_wpq_occupancy.allevent=0xe4,umask=0x1Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory. Unit: uncore_imc Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memoryunc_m_tagchk.hitevent=0xd3,umask=0x1All hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Tag Check; Hitunc_m_tagchk.miss_cleanevent=0xd3,umask=0x2All Clean line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Tag Check; Cleanunc_m_tagchk.miss_dirtyevent=0xd3,umask=0x4All dirty line misses to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_imc Tag Check; DirtyUNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket.  This snoop response is only used in >= 4 socket systems.  It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memoryunc_cha_tor_inserts.ia_miss_drdevent=0x35,umask=0x21,config1=0x40433TOR Inserts : DRds issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_occupancy.ia_miss_drdevent=0x36,umask=0x21,config1=0x40433TOR Occupancy : DRds issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsunc_m2m_imc_reads.to_pmmevent=0x37,umask=0x8Read requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m M2M Reads Issued to iMC; All, regardless of priorityunc_m2m_imc_writes.to_pmmevent=0x38,umask=0x20Write requests to Intel Optane DC persistent memory issued to the iMC from M2M. Unit: uncore_m2m unc_m2m_tag_hit.nm_rd_hit_dirtyevent=0x2c,umask=0x02Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Tag Hit; Read Hit from NearMem, Dirty  Lineunc_m2m_tag_hit.nm_ufill_hit_cleanevent=0x2c,umask=0x04Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Tag Hit; Underfill Rd Hit from NearMem, Clean Lineunc_m2m_tag_hit.nm_ufill_hit_dirtyevent=0x2c,umask=0x08Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode. Unit: uncore_m2m Tag Hit; Underfill Rd Hit from NearMem, Dirty  Lineevent=0x51,period=100003,umask=0x1Counts the number of cache lines replaced in L1 data cacheevent=0x48,period=1000003,umask=0x2Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailabilityCounts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accessesl1d_pend_miss.fb_full_periodsevent=0x48,cmask=1,edge=1,period=1000003,umask=0x2Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablabilityCounts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accessesl1d_pend_miss.l2_stallevent=0x48,period=1000003,umask=0x4Number of cycles a demand request has waited due to L1D due to lack of L2 resourcesCounts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accessesevent=0x48,period=1000003,umask=0x1Number of L1D misses that are outstandingCounts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request typeevent=0x48,cmask=1,period=1000003,umask=0x1Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fillNon-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fillCache lines that have been L2 hardware prefetched but not used by demand accessesCounts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cacheCounts demand requests that miss L2 cacheCounts demand requests to L2 cacheCounts the number of demand Data Read requests initiated by load instructions that hit L2 cachel2_rqsts.swpf_hitevent=0x24,period=200003,umask=0xc8SW prefetch requests that hit L2 cacheCounts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not fulll2_rqsts.swpf_missevent=0x24,period=200003,umask=0x28SW prefetch requests that miss L2 cacheCounts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not fullCore-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3event=0xd0,period=1000003,umask=0x81Counts all retired load instructions. This event accounts for SW prefetch instructions for loads  Supports address when precise (Precise event)event=0xd0,period=1000003,umask=0x82Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores  Supports address when precise (Precise event)event=0xd0,period=1000003,umask=0x83Counts retired load instructions with locked access  Supports address when precise (Precise event)Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event)Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event)Retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise (Precise event)Counts retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise (Precise event)Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event)Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event)Retired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise (Precise event)Counts retired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise (Precise event)Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1  Supports address when precise (Precise event)event=0xd1,period=1000003,umask=0x1Counts retired load instructions with L2 cache hits as data sources  Supports address when precise (Precise event)event=0xd1,period=100021,umask=0x10Counts retired load instructions missed L2 cache as data sources  Supports address when precise (Precise event)event=0xd1,period=100021,umask=0x4event=0xd1,period=50021,umask=0x20ocr.demand_code_rd.l3_hit.anyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0004Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or notocr.demand_code_rd.l3_hit.snoop_hitmCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedocr.demand_code_rd.l3_hit.snoop_hit_no_fwdCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.demand_code_rd.l3_hit.snoop_not_neededCounts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestocr.demand_code_rd.l3_hit.snoop_sentevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0004Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sentocr.demand_data_rd.l3_hit.anyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0001Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or notocr.demand_data_rd.l3_hit.snoop_hitmCounts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedocr.demand_data_rd.l3_hit.snoop_hit_no_fwdCounts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredCounts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.demand_data_rd.l3_hit.snoop_not_neededCounts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestocr.demand_data_rd.l3_hit.snoop_sentevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0001Counts demand data reads that hit a cacheline in the L3 where a snoop was sentocr.demand_rfo.l3_hit.anyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or notocr.demand_rfo.l3_hit.snoop_hitmCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedocr.demand_rfo.l3_hit.snoop_hit_no_fwdCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.demand_rfo.l3_hit.snoop_not_neededCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestocr.demand_rfo.l3_hit.snoop_sentevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sentocr.hwpf_l1d_and_swpf.l3_hit.anyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0400Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or notocr.hwpf_l1d_and_swpf.l3_hit.snoop_missCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.hwpf_l1d_and_swpf.l3_hit.snoop_not_neededCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestocr.hwpf_l2_data_rd.l3_hit.anyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0010Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent or notocr.hwpf_l2_data_rd.l3_hit.snoop_hitmCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedocr.hwpf_l2_data_rd.l3_hit.snoop_hit_no_fwdCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredocr.hwpf_l2_data_rd.l3_hit.snoop_missCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.hwpf_l2_data_rd.l3_hit.snoop_not_neededCounts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestocr.hwpf_l2_data_rd.l3_hit.snoop_sentevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0010Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sentocr.hwpf_l2_rfo.l3_hit.anyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0020Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or notocr.hwpf_l2_rfo.l3_hit.snoop_hitmCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modifiedocr.hwpf_l2_rfo.l3_hit.snoop_hit_no_fwdCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredocr.hwpf_l2_rfo.l3_hit.snoop_missCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.hwpf_l2_rfo.l3_hit.snoop_not_neededCounts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestocr.hwpf_l2_rfo.l3_hit.snoop_sentevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C0020Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sentocr.hwpf_l3.l3_hit.anyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C2380Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or notocr.other.l3_hit.snoop_hit_no_fwdCounts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not requiredCounts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the dataocr.other.l3_hit.snoop_not_neededCounts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the requestocr.other.l3_hit.snoop_sentevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1E003C8000Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sentocr.streaming_wr.l3_hit.anyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FC03C0800Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or notCounts memory transactions sent to the uncoreCounts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responsesevent=0x60,period=1000003,umask=0x8For every cycle, increments by the number of outstanding data read requests pendingFor every cycle, increments by the number of outstanding data read requests pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestorevent=0x60,cmask=1,period=1000003,umask=0x8Cycles where at least 1 outstanding data read request is pendingCycles where at least 1 outstanding data read request is pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestorevent=0x60,cmask=1,period=1000003,umask=0x4Cycles where at least 1 outstanding Demand RFO request is pendingCycles where at least 1 outstanding Demand RFO request is pending.   RFOs are initiated by a core as part of a data store operation.  Demand RFO requests include RFOs, locks, and ItoM transactions.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestorevent=0x60,period=1000003,umask=0x1For every cycle, increments by the number of outstanding demand data read requests pendingFor every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestorevent=0x60,period=1000003,umask=0x4Store Read transactions pending for off-core. Highly correlatedCounts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completionsq_misc.sq_fullevent=0xf4,period=100003,umask=0x4Cycles the queue waiting for offcore responses is fullCounts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entriesevent=0x32,period=100003,umask=0x1Counts the number of PREFETCHNTA instructions executedevent=0x32,period=100003,umask=0x8Counts the number of PREFETCHW instructions executedevent=0x32,period=100003,umask=0x2Counts the number of PREFETCHT0 instructions executedevent=0x32,period=100003,umask=0x4Counts the number of PREFETCHT1 or PREFETCHT2 instructions executedassists.fpCounts all microcode FP assistsCounts all microcode Floating Point assistsevent=0xc7,period=100003,umask=0x4Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsevent=0xc7,period=100003,umask=0x8Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsevent=0xc7,period=100003,umask=0x10Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsevent=0xc7,period=100003,umask=0x20Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsevent=0xc7,period=100003,umask=0x40event=0xc7,period=100003,umask=0x80event=0xc7,period=100003,umask=0x1Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsevent=0xc7,period=100003,umask=0x2Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these eventsevent=0xab,cmask=1,edge=1,period=100003,umask=0x2Decode Stream Buffer (DSB)-to-MITE transitions countCounts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitionsevent=0xab,period=100003,umask=0x2DSB-to-MITE switch true penalty cyclesDecode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITECounts retired Instructions who experienced Instruction L1 Cache true miss (Precise event)Counts retired Instructions who experienced Instruction L2 Cache true miss (Precise event)event=0xc6,period=100007,umask=0x1,frontend=0x500106Retired instructions after front-end starvation of at least 1 cycle (Precise event)Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall (Precise event)event=0xc6,period=100007,umask=0x1,frontend=0x508006Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event)event=0xc6,period=100007,umask=0x1,frontend=0x501006event=0xc6,period=100007,umask=0x1,frontend=0x500206Retired instructions after front-end starvation of at least 2 cycles (Precise event)Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall (Precise event)event=0xc6,period=100007,umask=0x1,frontend=0x510006Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event)event=0xc6,period=100007,umask=0x1,frontend=0x502006event=0xc6,period=100007,umask=0x1,frontend=0x500406Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event)event=0xc6,period=100007,umask=0x1,frontend=0x520006Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event)event=0xc6,period=100007,umask=0x1,frontend=0x504006Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event)event=0xc6,period=100007,umask=0x1,frontend=0x500806event=0x80,period=500009,umask=0x4Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularityCounts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accessesCounts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accessesCounts cycles where a code fetch is stalled due to L1 instruction cache tag missidq.dsb_cycles_anyCounts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathidq.dsb_cycles_okevent=0x79,cmask=5,period=2000003,umask=0x8Cycles DSB is delivering optimal number of UopsCounts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathidq.mite_cycles_anyCounts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB)idq.mite_cycles_okevent=0x79,cmask=5,period=2000003,umask=0x4Cycles MITE is delivering optimal number of UopsCounts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB)idq.ms_cycles_anyCycles when uops are being delivered to IDQ while MS is busyCounts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITEevent=0x79,cmask=1,edge=1,period=100003,umask=0x30Number of switches from DSB or MITE to the MSevent=0x79,period=100003,umask=0x30Uops delivered to IDQ while MS is busyevent=0x9c,period=1000003,umask=0x1Uops not delivered by IDQ when backend of the machine is not stalledCounts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycleevent=0x9c,cmask=5,period=1000003,umask=0x1Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalledCounts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycleevent=0x9c,cmask=1,inv=1,period=1000003,umask=0x1Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalledCounts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycleicl metrics100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS)100 * (( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD) + (10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS)TOPDOWN.SLOTSFraction of Physical Core issue-slots utilized by this Logical ProcessorTOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1Slots_UtilizationINST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )CPU_CLK_UNHALTED.DISTRIBUTEDBR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHESBR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHESFraction of branches of other types (not individually covered by other metrics in Info.Branches group)1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) )Other_Branches1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) / INST_RETIRED.ANY( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTEDCORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTEDCORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0C8 residency percent per package(cstate_pkg@c8\-residency@ / msr@tsc@) * 100C8_Pkg_ResidencyC9 residency percent per package(cstate_pkg@c9\-residency@ / msr@tsc@) * 100C9_Pkg_ResidencyC10 residency percent per package(cstate_pkg@c10\-residency@ / msr@tsc@) * 100C10_Pkg_Residencyevent=0xa3,cmask=2,period=1000003,umask=0x2event=0xa3,cmask=6,period=1000003,umask=0x6event=0xc8,period=100003,umask=0x4Number of times an HLE execution aborted due to any reasons (multiple categories may count as one)Counts the number of times HLE abort was triggeredevent=0xc8,period=100003,umask=0x80Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts)event=0xc8,period=100003,umask=0x8Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts)event=0xc8,period=100003,umask=0x20Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.)event=0xc8,period=100003,umask=0x2Counts the number of times HLE commit succeededevent=0xc8,period=100003,umask=0x1Counts the number of times we entered an HLE region. Does not count nested transactionsNumber of machine clears due to memory ordering conflictsCounts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architectureocr.demand_code_rd.l3_missCounts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cacheocr.demand_data_rd.l3_missCounts demand data reads that was not supplied by the L3 cacheocr.demand_rfo.l3_missCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cacheocr.hwpf_l1d_and_swpf.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00400Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cacheocr.hwpf_l2_data_rd.l3_missCounts hardware prefetch data reads (which bring data to L2)  that was not supplied by the L3 cacheocr.hwpf_l2_rfo.l3_missCounts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cacheocr.other.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC08000Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cacheocr.streaming_wr.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FFFC00800Counts streaming stores that was not supplied by the L3 cacheCounts demand data read requests that miss the L3 cacheevent=0x60,cmask=1,period=1000003,umask=0x10Cycles where at least one demand data read request known to have missed the L3 cache is pendingCycles where at least one demand data read request known to have missed the L3 cache is pending.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cacheevent=0xc9,period=100003,umask=0x4Number of times an RTM execution abortedCounts the number of times RTM abort was triggeredevent=0xc9,period=100003,umask=0x80Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)event=0xc9,period=100003,umask=0x8Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)event=0xc9,period=100003,umask=0x40Counts the number of times an RTM execution aborted due to incompatible memory typeevent=0xc9,period=100003,umask=0x20Counts the number of times an RTM execution aborted due to HLE-unfriendly instructionsevent=0xc9,period=100003,umask=0x2Counts the number of times RTM commit succeededevent=0xc9,period=100003,umask=0x1Counts the number of times we entered an RTM region. Does not count nested transactionsevent=0x5d,period=100003,umask=0x2Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional regionCounts Unfriendly TSX abort triggered by a vzeroupper instructionevent=0x5d,period=100003,umask=0x4Number of times an instruction execution caused the transactional nest count supported to be exceededCounts Unfriendly TSX abort triggered by a nest count that is too deeptx_mem.abort_capacity_readevent=0x54,period=100003,umask=0x80Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional readsSpeculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional readsevent=0x54,period=100003,umask=0x2Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writesSpeculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writesevent=0x54,period=100003,umask=0x1Counts the number of times a TSX line had a cache conflictevent=0x54,period=100003,umask=0x10Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatchevent=0x54,period=100003,umask=0x8Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not emptyevent=0x54,period=100003,umask=0x20Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Bufferevent=0x54,period=100003,umask=0x4Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lockevent=0x54,period=100003,umask=0x40Counts the number of times we could not allocate Lock BufferCounts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codesCounts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructionsCore cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructionsCounts demand instruction fetches and L1 instruction cache prefetches that have any type of responseocr.demand_code_rd.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000004Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the requestocr.demand_code_rd.local_dramCounts demand data reads that have any type of responseocr.demand_data_rd.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000001Counts demand data reads that DRAM supplied the requestocr.demand_data_rd.local_dramCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of responseocr.demand_rfo.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the requestocr.demand_rfo.local_dramocr.hwpf_l1d_and_swpf.any_responseCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of responseocr.hwpf_l1d_and_swpf.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000400Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the requestocr.hwpf_l1d_and_swpf.local_dramocr.hwpf_l2_data_rd.any_responseCounts hardware prefetch data reads (which bring data to L2)  that have any type of responseocr.hwpf_l2_data_rd.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000010Counts hardware prefetch data reads (which bring data to L2)  that DRAM supplied the requestocr.hwpf_l2_data_rd.local_dramocr.hwpf_l2_rfo.any_responseCounts hardware prefetch RFOs (which bring data to L2) that have any type of responseocr.hwpf_l2_rfo.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000020Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the requestocr.hwpf_l2_rfo.local_dramCounts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of responseocr.other.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184008000Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the requestocr.other.local_dramocr.streaming_wr.any_responseCounts streaming stores that have any type of responseocr.streaming_wr.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000800Counts streaming stores that DRAM supplied the requestocr.streaming_wr.local_dramevent=0x14,cmask=1,period=1000003,umask=0x9Cycles when divide unit is busy executing divide or square root operationsCounts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operationsassists.anyevent=0xc1,period=100003,umask=0x7Number of occurrences where a microcode assist is invoked by hardwareCounts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assistsAll branch instructions retired (Precise event)Counts all branch instructions retired (Precise event)br_inst_retired.condevent=0xc4,period=400009,umask=0x11Counts conditional branch instructions retired (Precise event)Not taken branch instructions retired (Precise event)Counts not taken branch instructions retired (Precise event)br_inst_retired.cond_takenTaken conditional branch instructions retired (Precise event)Counts taken conditional branch instructions retired (Precise event)Far branch instructions retired (Precise event)Counts far branch instructions retired (Precise event)br_inst_retired.indirectevent=0xc4,period=100003,umask=0x80Indirect near branch instructions retired (excluding returns) (Precise event)Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch (Precise event)Counts both direct and indirect near call instructions retired (Precise event)Counts return instructions retired (Precise event)Counts taken branch instructions retired (Precise event)event=0xc5,period=50021All mispredicted branch instructions retired (Precise event)Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path (Precise event)br_misp_retired.condevent=0xc5,period=50021,umask=0x11Counts mispredicted conditional branch instructions retired (Precise event)br_misp_retired.cond_ntakenevent=0xc5,period=50021,umask=0x10Mispredicted non-taken conditional branch instructions retired (Precise event)Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken (Precise event)br_misp_retired.cond_takenevent=0xc5,period=50021,umask=0x1number of branch instructions retired that were mispredicted and taken. Non PEBS (Precise event)Counts taken conditional mispredicted branch instructions retired (Precise event)br_misp_retired.indirectevent=0xc5,period=50021,umask=0x80All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event)Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event)br_misp_retired.indirect_callevent=0xc5,period=50021,umask=0x2Mispredicted indirect CALL instructions retired (Precise event)Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect (Precise event)event=0xc5,period=50021,umask=0x20Counts number of near branch instructions retired that were mispredicted and taken (Precise event)cpu_clk_unhalted.distributedevent=0xec,period=2000003,umask=0x2Cycle counts are evenly distributed between active threads in the CoreThis event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthreadCounts Core crystal clock cycles when current thread is unhalted and the other thread is haltedcpu_clk_unhalted.ref_distributedevent=0x3c,period=2000003,umask=0x8Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the CoreThis event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthreadCounts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this caseCounts core crystal clock cycles when the thread is unhaltedCounts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other eventsevent=0xa3,cmask=8,period=1000003,umask=0x8event=0xa3,cmask=1,period=1000003,umask=0x1event=0xa3,cmask=16,period=1000003,umask=0x10event=0xa3,cmask=12,period=1000003,umask=0xcevent=0xa3,cmask=5,period=1000003,umask=0x5event=0xa3,cmask=20,period=1000003,umask=0x14event=0xa3,cmask=4,period=1000003,umask=0x4event=0xa6,cmask=2,period=1000003,umask=0x40Cycles where the Store Buffer was full and no loads caused an execution stallCounts cycles where the Store Buffer was full and no loads caused an execution stallevent=0x87,period=500009,umask=0x1Number of instructions retired. Fixed Counter - architectural event (Precise event)Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event)Number of instructions retired. General Counter - architectural event (Precise event)Number of all retired NOP instructions (Precise event)Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Precise event)A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0 (Precise event)inst_retired.stall_cyclesevent=0xc0,cmask=1,inv=1,period=1000003,umask=0x1Cycles without actually retired instructionsThis event counts cycles without actually retired instructionsint_misc.all_recovery_cyclesCycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stallCounts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stallevent=0xd,period=500009,umask=0x80Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered pathCycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered pathevent=0xd,period=500009,umask=0x1Core cycles the allocator was stalled due to recovery from earlier clear event for this threadCounts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear eventint_misc.uop_droppingevent=0xd,period=1000003,umask=0x10TMA slots where uops got droppedEstimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasonsCounts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useFalse dependencies due to partial compare on addressCounts the number of times a load got blocked due to false dependencies due to partial compare on addressload_hit_prefetch.swpfCounts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchlsd.cycles_okevent=0xa8,cmask=5,period=2000003,umask=0x1Cycles optimal number of Uops delivered by the LSD, but did not come from the decoderCounts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector)Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector)Counts the number of machine clears (nukes) of any typemisc_retired.lbr_insertsevent=0xcc,period=100003,umask=0x20Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properlymisc_retired.pause_instevent=0xcc,period=100003,umask=0x40Number of retired PAUSE instructions. This event is not supported on first SKL and KBL productsCounts number of retired PAUSE instructions. This event is not supported on first SKL and KBL productsevent=0xa2,period=100003,umask=0x8resource_stalls.scoreboardevent=0xa2,period=100003,umask=0x2Counts cycles where the pipeline is stalled due to serializing operationsevent=0x5e,period=1000003,umask=0x1Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)event=0x5e,cmask=1,edge=1,inv=1,period=100003,umask=0x1Counts end of periods where the Reservation Station (RS) was emptyCounts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)topdown.backend_bound_slotsevent=0xa4,period=10000003,umask=0x2TMA slots where no uops were being issued due to lack of back-end resourcesCounts the number of Top-down Microarchitecture Analysis (TMA) method's  slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resourcestopdown.br_mispredict_slotsevent=0xa4,period=10000003,umask=0x8TMA slots wasted due to incorrect speculation by branch mispredictionsNumber of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch mispredictiontopdown.slotsevent=0,period=10000003,umask=0x4TMA slots available for an unhalted logical processor. Fixed counter - architectural eventNumber of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3)topdown.slots_pevent=0xa4,period=10000003,umask=0x1TMA slots available for an unhalted logical processor. General counter - architectural eventCounts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical coreuops_decoded.dec0event=0x56,period=1000003,umask=0x1Number of uops decoded out of instructions exclusively fetched by decoder 0Uops exclusively fetched by decoder 0uops_dispatched.port_0Number of uops executed on port 0uops_dispatched.port_1Number of uops executed on port 1uops_dispatched.port_2_3Number of uops executed on port 2 and 3Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3uops_dispatched.port_4_9Number of uops executed on port 4 and 9Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9uops_dispatched.port_5Number of uops executed on port 5uops_dispatched.port_6Number of uops executed on port 6uops_dispatched.port_7_8Number of uops executed on port 7 and 8Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8Counts the number of uops executed from any threadCounts cycles when at least 1 micro-op is executed from any thread on physical coreCounts cycles when at least 2 micro-ops are executed from any thread on physical coreCounts cycles when at least 3 micro-ops are executed from any thread on physical coreCounts cycles when at least 4 micro-ops are executed from any thread on physical coreuops_executed.cycles_ge_1uops_executed.cycles_ge_2uops_executed.cycles_ge_3uops_executed.cycles_ge_4Uops that RAT issues to RSevent=0xe,cmask=1,inv=1,period=1000003,umask=0x1Cycles when RAT does not issue Uops to RS for the threadevent=0xe,period=100003,umask=0x2uops_retired.slotsCounts the retirement slots used each cycleevent=0xc2,cmask=1,inv=1,period=1000003,umask=0x2event=0xc2,cmask=10,inv=1,period=1000003,umask=0x2Counts the number of cycles using always true condition (uops_ret &amp;lt; 16) applied to non PEBS uops retired eventevent=0x8,period=100003,umask=0x20Cycles when at least one PMH is busy with a page walk for a demand loadCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand loadevent=0x8,period=100003,umask=0x4Page walks completed due to a demand data load to a 2M/4M pagePage walks completed due to a demand data load to a 4K pageNumber of page walks outstanding for a demand load in the PMH each cycleCounts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycleCounts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)Cycles when at least one PMH is busy with a page walk for a storePage walks completed due to a demand data store to a 2M/4M pagePage walks completed due to a demand data store to a 4K pageNumber of page walks outstanding for a store in the PMH each cycleCounts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycleCounts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB)Cycles when at least one PMH is busy with a page walk for code (instruction fetch) requestCounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) requestNumber of page walks outstanding for an outstanding code request in the PMH each cycleCounts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycleCounts all requests that miss L2 cachemem_load_l3_hit_retired.xsnp_fwdTBD  Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_no_fwdOCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWDDemand Data Read transactions pending for off-core. Highly correlatedCounts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the coreCycles the superQ cannot take any more entriesCounts the cycles for which the thread is active and the superQ cannot take any more entriesexe_activity.bound_on_loadsevent=0xa6,cmask=5,period=2000003,umask=0x21Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycleCounts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycleevent=0xa6,period=1000003,umask=0x80Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter (Precise event)Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on addresstgl metricsSummaryBranches;FetchBW;PGO1 / IPCInstructions Per Cycle (per physical core)SMT;TmaL1FlopsUOPS_EXECUTED.THREAD / ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 )Pipeline;PortsUtilBrMispredictsBranches;InsTypeBranchesBranches;PGOFlops;FpArith;InsTypeLSDDSB;FetchBWActual Average Latency for L1 data-cache miss demand loads (in core cycles)MemoryBound;MemoryLatMemoryBound;MemoryBW( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CORE_CLKS )MemoryTLBMemoryBWMemoryBW;OffcoreCacheMissesFlops;HPC1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTEDCounts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page faultCache lines that are evicted by L2 cache when triggered by an L2 cache fillCounts the number of lines that are evicted by the L2 cache due to L2 cache fills.  Evicted lines are delivered to the L3, which may or may not cache them, according to system load and prioritiesCore-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD  Supports address when precise (Precise event)This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD  Supports address when precise (Precise event)Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches  Supports address when precise (Precise event)Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode)  Supports address when precise (Precise event)Retired instructions with at least 1 uncacheable load or Bus Lock  Supports address when precise (Precise event)Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock)  Supports address when precise (Precise event)Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches  Supports address when precise (Precise event)Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode)  Supports address when precise (Precise event)ocr.demand_code_rd.l3_hitCounts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socketCounts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the dataocr.demand_code_rd.snc_cache.hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000004Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_code_rd.snc_cache.hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000004Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_data_rd.l3_hitCounts demand data reads that hit in the L3 or were snooped from another core's caches on the same socketCounts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the dataCounts demand data reads that resulted in a snoop that hit in another core, which did not forward the dataCounts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreocr.demand_data_rd.remote_cache.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1030000001Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the dataocr.demand_data_rd.remote_cache.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x830000001Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreocr.demand_data_rd.snc_cache.hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000001Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_data_rd.snc_cache.hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000001Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_rfo.l3_hitCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socketCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the dataocr.demand_rfo.snc_cache.hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_rfo.snc_cache.hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.hwpf_l1d_and_swpf.l3_hitCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socketocr.hwpf_l3.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80082380Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socketocr.prefetches.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F803C27F0Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socketocr.reads_to_core.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F003C0477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socketocr.reads_to_core.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the dataocr.reads_to_core.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the dataocr.reads_to_core.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreocr.reads_to_core.remote_cache.snoop_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1830000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified)ocr.reads_to_core.remote_cache.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1030000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the dataocr.reads_to_core.remote_cache.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x830000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreocr.reads_to_core.snc_cache.hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.reads_to_core.snc_cache.hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x808000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.streaming_wr.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x80080800Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socketCounts cacheable and non-cacheable code reads to the coreCounts both cacheable and non-cacheable code reads to the coreevent=0x60,cmask=1,period=1000003,umask=0x2Cycles with outstanding code read requests pendingCycles with outstanding code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Reads.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestorevent=0x60,period=1000003,umask=0x2For every cycle, increments by the number of outstanding code read requests pendingFor every cycle, increments by the number of outstanding code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Reads.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestoricx metricsUOPS_RETIRED.SLOTS / INST_RETIRED.ANYUOPS_RETIRED.SLOTS / BR_INST_RETIRED.NEAR_TAKEN1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( cha_0@event\=0x0@ / duration_time )UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@event\=0x36\,umask\=0xC817FE01\,thresh\=1@( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / cha_0@event\=0x0@ ) 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / cha_0@event\=0x0@UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000000 / duration_time( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / 1000000000 / duration_timeC1 residency percent per core(cstate_core@c1\-residency@ / msr@tsc@) * 100C1_Core_ResidencyCounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 cachesocr.demand_code_rd.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400004Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyCounts demand data reads that were not supplied by the local socket's L1, L2, or L3 cachesocr.demand_data_rd.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400001Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FC00002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 cachesocr.demand_rfo.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F04400002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socketevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC00400Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 cachesocr.hwpf_l1d_and_swpf.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400400Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyocr.hwpf_l3.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x94002380Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 cachesocr.hwpf_l3.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84002380Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyocr.itom.l3_miss_localCounts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3FBFC08000Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 cachesocr.other.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84408000Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyocr.prefetches.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F844027F0Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyocr.reads_to_core.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FC00477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 cachesocr.reads_to_core.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F04400477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socketocr.reads_to_core.l3_miss_local_socketevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x70CC00477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Clusterevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x94000800Counts streaming stores that missed the local socket's L1, L2, and L3 cachesocr.streaming_wr.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x84000800Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyFor every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cacheFor every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.  Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cacheCycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cacheCycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.  Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cachecore_snoop_response.i_fwd_feevent=0xef,period=1000003,umask=0x20Hit snoop reply with data, line invalidatedCounts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache.  A single snoop response from the core counts on all hyperthreads of the corecore_snoop_response.i_fwd_mevent=0xef,period=1000003,umask=0x10HitM snoop reply with data, line invalidatedCounts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response).  A single snoop response from the core counts on all hyperthreads of the corecore_snoop_response.i_hit_fseevent=0xef,period=1000003,umask=0x2Hit snoop reply without sending the data, line invalidatedCounts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches.  A single snoop response from the core counts on all hyperthreads of the corecore_snoop_response.missevent=0xef,period=1000003,umask=0x1Line not found snoop replyCounts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Corecore_snoop_response.s_fwd_feevent=0xef,period=1000003,umask=0x40Hit snoop reply with data, line kept in Shared stateCounts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state.  A single snoop response from the core counts on all hyperthreads of the corecore_snoop_response.s_fwd_mevent=0xef,period=1000003,umask=0x8HitM snoop reply with data, line kept in Shared stateCounts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state.  A single snoop response from the core counts on all hyperthreads of the corecore_snoop_response.s_hit_fseevent=0xef,period=1000003,umask=0x4Hit snoop reply without sending the data, line kept in Shared stateCounts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state.  A single snoop response from the core counts on all hyperthreads of the coreevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000004Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAMCounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Clusterocr.demand_code_rd.snc_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000004Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000001Counts demand data reads that were supplied by DRAMCounts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Clusterocr.demand_data_rd.local_pmmCounts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Clusterocr.demand_data_rd.pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x703C00001Counts demand data reads that were supplied by PMMocr.demand_data_rd.remote_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x730000001Counts demand data reads that were supplied by DRAM attached to another socketocr.demand_data_rd.remote_pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x703000001Counts demand data reads that were supplied by PMM attached to another socketocr.demand_data_rd.snc_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000001Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_data_rd.snc_pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x700800001Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FFC0002event=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAMCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Clusterocr.demand_rfo.local_pmmCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Clusterocr.demand_rfo.pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x703C00002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMMocr.demand_rfo.remote_pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x703000002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socketocr.demand_rfo.snc_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_rfo.snc_pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x700800002Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000400Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAMCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Clusterocr.hwpf_l2.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10070Counts hardware prefetch (which bring data to L2) that have any type of responseocr.hwpf_l3.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x12380Counts hardware prefetches to the L3 only that have any type of responseocr.hwpf_l3.remoteevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x90002380Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socketocr.itom.remoteCounts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socketocr.reads_to_core.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F3FFC0477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of responseocr.reads_to_core.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x73C000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAMocr.reads_to_core.local_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x104000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Clusterocr.reads_to_core.local_pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100400477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those PMM accesses that are controlled by the close SNC Clusterocr.reads_to_core.local_socket_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x70C000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Clusterocr.reads_to_core.local_socket_pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x700C00477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Clusterocr.reads_to_core.remoteevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F33000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socketocr.reads_to_core.remote_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x730000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socketocr.reads_to_core.remote_pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x703000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socketocr.reads_to_core.snc_dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x708000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeocr.reads_to_core.snc_pmmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x700800477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeCounts retired mispredicted indirect (near taken) calls, including both register and memory indirect (Precise event)event=0xd3,umask=0x012LM Tag Check : Hit in Near Memory Cache. Unit: uncore_imc event=0xd3,umask=0x022LM Tag Check : Miss, no data in this line. Unit: uncore_imc event=0xd3,umask=0x042LM Tag Check : Miss, existing data may be evicted to Far Memory. Unit: uncore_imc unc_m_tagchk.nm_rd_hitevent=0xd3,umask=0x082LM Tag Check : Read Hit in Near Memory Cache. Unit: uncore_imc unc_m_tagchk.nm_wr_hitevent=0xd3,umask=0x102LM Tag Check : Write Hit in Near Memory Cache. Unit: uncore_imc event=0x2,umask=0x04DRAM Precharge commands. : Precharge due to read. Unit: uncore_imc event=0x2,umask=0x08DRAM Precharge commands. : Precharge due to write. Unit: uncore_imc event=0x4,umask=0x0fAll DRAM read CAS commands issued (including underfills). Unit: uncore_imc event=0x4,umask=0x30All DRAM write CAS commands issued. Unit: uncore_imc event=0x4,umask=0x3fAll DRAM CAS commands issued. Unit: uncore_imc unc_m_dram_refresh.opportunisticevent=0x45,umask=0x01Number of DRAM Refreshes Issued. Unit: uncore_imc unc_m_dram_refresh.panicevent=0x45,umask=0x02unc_m_dram_refresh.highevent=0x45,umask=0x04unc_m_rpq_inserts.pch0event=0x10,umask=0x01unc_m_rpq_inserts.pch1event=0x10,umask=0x02unc_m_wpq_inserts.pch0event=0x20,umask=0x01unc_m_wpq_inserts.pch1event=0x20,umask=0x02unc_m_pre_count.pgtevent=0x2,umask=0x10DRAM Precharge commands. : Precharge due to page table. Unit: uncore_imc DRAM Clockticks. Unit: uncore_imc unc_m_hclockticksHalf clockticks for IMC. Unit: uncore_imc unc_m_rpq_occupancy_pch0unc_m_rpq_occupancy_pch1unc_m_wpq_occupancy_pch0event=0x82unc_m_wpq_occupancy_pch1event=0x83unc_m_act_count.allevent=0x1,umask=0x0BDRAM Activate Count : All Activates. Unit: uncore_imc unc_m_pre_count.allevent=0x2,umask=0x1CDRAM Precharge commands. Unit: uncore_imc event=0xe0,umask=0x01PMM Read Pending Queue Occupancy. Unit: uncore_imc PMM Read Queue Inserts. Unit: uncore_imc PMM Write Queue Inserts. Unit: uncore_imc event=0xea,umask=0x01PMM Commands : All. Unit: uncore_imc event=0xea,umask=0x02PMM Commands : Reads - RPQ. Unit: uncore_imc event=0xea,umask=0x04PMM Commands : Writes. Unit: uncore_imc event=0xea,umask=0x08PMM Commands : Underfill reads. Unit: uncore_imc event=0xe4,umask=0x01PMM Write Pending Queue Occupancy. Unit: uncore_imc Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent. Unit: uncore_cha Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent. Unit: uncore_cha Local read requests that miss the SF/LLC and are sent to the CHA's home agent. Unit: uncore_cha Remote read requests sent to the CHA's home agent. Unit: uncore_cha Local write requests that miss the SF/LLC and are sent to the CHA's home agent. Unit: uncore_cha unc_cha_requests.writes_remoteevent=0x50,umask=0x08Remote write requests sent to the CHA's home agent. Unit: uncore_cha Clockticks of the uncore caching and home agent (CHA). Unit: uncore_cha CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH. Unit: uncore_cha unc_cha_llc_victims.allevent=0x37,umask=0x0FLines Victimized : All Lines Victimized. Unit: uncore_cha Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent. Unit: uncore_cha event=0x50,umask=0x0cLocal write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent. Unit: uncore_cha unc_cha_tor_inserts.iaevent=0x35,umask=0xC001FF01TOR Inserts : All requests from iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_hitevent=0x35,umask=0xC001FD01TOR Inserts : All requests from iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_crdevent=0x35,umask=0xC80FFD01TOR Inserts : CRds issued by iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_drdevent=0x35,umask=0xC817FD01TOR Inserts : DRds issued by iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_llcprefrfoevent=0x35,umask=0xCCC7FD01TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_rfoevent=0x35,umask=0xC807FD01TOR Inserts : RFOs issued by iA Cores that Hit the LLC. Unit: uncore_cha event=0x35,umask=0xC001FE01TOR Inserts : All requests from iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_crdevent=0x35,umask=0xC80FFE01TOR Inserts : CRds issued by iA Cores that Missed the LLC. Unit: uncore_cha event=0x35,umask=0xC817FE01unc_cha_tor_inserts.ia_miss_llcprefrfoevent=0x35,umask=0xCCC7FE01TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_rfoevent=0x35,umask=0xC807FE01TOR Inserts : RFOs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ioevent=0x35,umask=0xC001FF04TOR Inserts : All requests from IO Devices. Unit: uncore_cha unc_cha_tor_inserts.io_hitevent=0x35,umask=0xC001FD04TOR Inserts : All requests from IO Devices that hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_missevent=0x35,umask=0xC001FE04TOR Inserts : All requests from IO Devices that missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.iaevent=0x36,umask=0xC001FF01TOR Occupancy : All requests from iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_hitevent=0x36,umask=0xC001FD01TOR Occupancy : All requests from iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_missevent=0x36,umask=0xC001FE01TOR Occupancy : All requests from iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_crdevent=0x36,umask=0xC80FFE01TOR Occupancy : CRds issued by iA Cores that Missed the LLC. Unit: uncore_cha event=0x36,umask=0xC817FE01unc_cha_tor_occupancy.ia_miss_rfoevent=0x36,umask=0xC807FE01TOR Occupancy : RFOs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ioevent=0x36,umask=0xC001FF04TOR Occupancy : All requests from IO Devices. Unit: uncore_cha unc_cha_tor_occupancy.io_hitevent=0x36,umask=0xC001FD04TOR Occupancy : All requests from IO Devices that hit the LLC. Unit: uncore_cha unc_cha_tor_occupancy.io_missevent=0x36,umask=0xC001FE04TOR Occupancy : All requests from IO Devices that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_miss_itomevent=0x35,umask=0xCC43FE04TOR Inserts : ItoMs issued by IO Devices that missed the LLC. Unit: uncore_cha unc_cha_cms_clockticksevent=0xc0CMS Clockticks. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_crd_prefevent=0x35,umask=0xC88FFD01TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_drd_prefevent=0x35,umask=0xC897FD01TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_rfo_prefevent=0x35,umask=0xC887FD01TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_crd_prefevent=0x35,umask=0xC88FFE01TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_prefevent=0x35,umask=0xC897FE01TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_rfo_prefevent=0x35,umask=0xC887FE01TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_hit_itomevent=0x35,umask=0xCC43FD04TOR Inserts : ItoMs issued by IO Devices that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_itomevent=0x35,umask=0xCC43FF04TOR Inserts : ItoMs issued by IO Devices. Unit: uncore_cha unc_cha_tor_inserts.ia_rfo_prefevent=0x35,umask=0xC887FF01TOR Inserts : RFO_Prefs issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_rfoevent=0x35,umask=0xC807FF01TOR Inserts : RFOs issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_llcprefrfoevent=0x35,umask=0xCCC7FF01TOR Inserts : LLCPrefRFO issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_drd_prefevent=0x35,umask=0xC897FF01TOR Inserts : DRd_Prefs issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_crdevent=0x35,umask=0xC80FFF01TOR Inserts : CRDs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_rfoevent=0x36,umask=0xC807FF01TOR Occupancy : RFOs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_drdevent=0x36,umask=0xC817FF01TOR Occupancy : DRds issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_crdevent=0x36,umask=0xC80FFF01TOR Occupancy : CRDs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_localevent=0x36,umask=0xC816FE01TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_remoteevent=0x36,umask=0xC8177E01TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_localevent=0x35,umask=0xC816FE01TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_remoteevent=0x35,umask=0xC8177E01TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref_localevent=0x35,umask=0xC896FE01TOR Inserts; DRd Pref misses from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref_remoteevent=0x35,umask=0xC8977E01unc_cha_tor_inserts.ia_miss_rfo_localevent=0x35,umask=0xC806FE01TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_rfo_remoteevent=0x35,umask=0xC8077E01TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_rfo_pref_localevent=0x35,umask=0xC886FE01TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_rfo_pref_remoteevent=0x35,umask=0xC8877E01TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_clflushevent=0x35,umask=0xC8C7FF01TOR Inserts : CLFlushes issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_specitomevent=0x35,umask=0xCC57FF01TOR Inserts : SpecItoMs issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.io_itomcachenearevent=0x35,umask=0xCD43FF04TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices. Unit: uncore_cha unc_cha_tor_inserts.io_hit_itomcachenearevent=0x35,umask=0xCD43FD04TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_miss_itomcachenearevent=0x35,umask=0xCD43FE04TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pmmevent=0x35,umask=0xC8178A01TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_local_pmmevent=0x35,umask=0xC8168A01TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_remote_pmmevent=0x35,umask=0xC8170A01TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_full_streaming_wrevent=0x35,umask=0xc867fe01TOR Inserts; WCiLF misses from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_partial_streaming_wrevent=0x35,umask=0xc86ffe01TOR Inserts; WCiL misses from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pmmevent=0x36,umask=0xC8178A01TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_llcprefdataevent=0x35,umask=0xCCD7FE01TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_miss_pcirdcurevent=0x35,umask=0xC8F3FE04TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.io_miss_pcirdcurevent=0x36,umask=0xc8f3fe04TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_ddrevent=0x35,umask=0xC8178601TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_local_ddrevent=0x35,umask=0xC8168601TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_remote_ddrevent=0x35,umask=0xC8170601TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_ddrevent=0x36,umask=0xC8178601TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_hit_pcirdcurevent=0x35,umask=0xC8F3FD04TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.io_pcirdcurevent=0x35,umask=0xC8F3FF04TOR Inserts : PCIRdCurs issued by IO Devices. Unit: uncore_cha unc_cha_tor_inserts.ia_llcprefdataevent=0x35,umask=0xCCD7FF01TOR Inserts : LLCPrefData issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.io_pcirdcurevent=0x36,umask=0xC8F3FF04TOR Occupancy : PCIRdCurs issued by IO Devices. Unit: uncore_cha unc_cha_llc_lookup.data_readevent=0x34,umask=0x1BC1FFCache and Snoop Filter Lookups; Data Read Request. Unit: uncore_cha Clockticks of the integrated IO (IIO) traffic controller. Unit: uncore_iio Four byte data request of the CPU : Card writing to DRAM. Unit: uncore_iio Four byte data request of the CPU : Card reading from DRAM. Unit: uncore_iio unc_iio_data_req_of_cpu.cmpd.part0event=0x83,ch_mask=0x01,fc_mask=0x07,umask=0x80Data requested of the CPU : CmpD - device sending completion to CPU request. Unit: uncore_iio unc_iio_data_req_of_cpu.cmpd.part1event=0x83,ch_mask=0x02,fc_mask=0x07,umask=0x80unc_iio_data_req_of_cpu.cmpd.part2event=0x83,ch_mask=0x04,fc_mask=0x07,umask=0x80unc_iio_data_req_of_cpu.cmpd.part3event=0x83,ch_mask=0x08,fc_mask=0x07,umask=0x80Data requested by the CPU : Core writing to Card's MMIO space. Unit: uncore_iio Data requested by the CPU : Core reporting completion of Card read from Core DRAM. Unit: uncore_iio Number Transactions requested of the CPU : Card writing to DRAM. Unit: uncore_iio Number Transactions requested of the CPU : Card reading from DRAM. Unit: uncore_iio unc_iio_txn_req_of_cpu.cmpd.part0event=0x84,ch_mask=0x01,fc_mask=0x07,umask=0x80Number Transactions requested of the CPU : CmpD - device sending completion to CPU request. Unit: uncore_iio unc_iio_txn_req_of_cpu.cmpd.part1event=0x84,ch_mask=0x02,fc_mask=0x07,umask=0x80unc_iio_txn_req_of_cpu.cmpd.part2event=0x84,ch_mask=0x04,fc_mask=0x07,umask=0x80unc_iio_txn_req_of_cpu.cmpd.part3event=0x84,ch_mask=0x08,fc_mask=0x07,umask=0x80Number Transactions requested by the CPU : Core writing to Card's MMIO space. Unit: uncore_iio Number Transactions requested by the CPU : Core reading from Card's MMIO space. Unit: uncore_iio unc_iio_data_req_by_cpu.mem_write.part4event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x01unc_iio_data_req_by_cpu.mem_write.part5event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x01unc_iio_data_req_by_cpu.mem_write.part6event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x01unc_iio_data_req_by_cpu.mem_write.part7event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x01unc_iio_data_req_by_cpu.mem_read.part4event=0xc0,ch_mask=0x10,fc_mask=0x07,umask=0x04unc_iio_data_req_by_cpu.mem_read.part5event=0xc0,ch_mask=0x20,fc_mask=0x07,umask=0x04unc_iio_data_req_by_cpu.mem_read.part6event=0xc0,ch_mask=0x40,fc_mask=0x07,umask=0x04unc_iio_data_req_by_cpu.mem_read.part7event=0xc0,ch_mask=0x80,fc_mask=0x07,umask=0x04unc_iio_data_req_of_cpu.mem_write.part4event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x01unc_iio_data_req_of_cpu.mem_write.part5event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x01unc_iio_data_req_of_cpu.mem_write.part6event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x01unc_iio_data_req_of_cpu.mem_write.part7event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x01unc_iio_data_req_of_cpu.mem_read.part4event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x04unc_iio_data_req_of_cpu.mem_read.part5event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x04unc_iio_data_req_of_cpu.mem_read.part6event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x04unc_iio_data_req_of_cpu.mem_read.part7event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x04unc_iio_data_req_of_cpu.cmpd.part4event=0x83,ch_mask=0x10,fc_mask=0x07,umask=0x80unc_iio_data_req_of_cpu.cmpd.part5event=0x83,ch_mask=0x20,fc_mask=0x07,umask=0x80unc_iio_data_req_of_cpu.cmpd.part6event=0x83,ch_mask=0x40,fc_mask=0x07,umask=0x80unc_iio_data_req_of_cpu.cmpd.part7event=0x83,ch_mask=0x80,fc_mask=0x07,umask=0x80unc_iio_num_req_of_cpu.commit.allevent=0x85,ch_mask=0xFF,fc_mask=0x07,umask=0x01Number requests PCIe makes of the main die : All. Unit: uncore_iio unc_iio_txn_req_by_cpu.mem_write.part4event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x01unc_iio_txn_req_by_cpu.mem_write.part5event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x01unc_iio_txn_req_by_cpu.mem_write.part6event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x01unc_iio_txn_req_by_cpu.mem_write.part7event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x01unc_iio_txn_req_by_cpu.mem_read.part4event=0xc1,ch_mask=0x10,fc_mask=0x07,umask=0x04unc_iio_txn_req_by_cpu.mem_read.part5event=0xc1,ch_mask=0x20,fc_mask=0x07,umask=0x04unc_iio_txn_req_by_cpu.mem_read.part6event=0xc1,ch_mask=0x40,fc_mask=0x07,umask=0x04unc_iio_txn_req_by_cpu.mem_read.part7event=0xc1,ch_mask=0x80,fc_mask=0x07,umask=0x04unc_iio_txn_req_of_cpu.mem_write.part4event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x01unc_iio_txn_req_of_cpu.mem_write.part5event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x01unc_iio_txn_req_of_cpu.mem_write.part6event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x01unc_iio_txn_req_of_cpu.mem_write.part7event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x01unc_iio_txn_req_of_cpu.mem_read.part4event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x04unc_iio_txn_req_of_cpu.mem_read.part5event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x04unc_iio_txn_req_of_cpu.mem_read.part6event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x04unc_iio_txn_req_of_cpu.mem_read.part7event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x04unc_iio_txn_req_of_cpu.cmpd.part4event=0x84,ch_mask=0x10,fc_mask=0x07,umask=0x80unc_iio_txn_req_of_cpu.cmpd.part5event=0x84,ch_mask=0x20,fc_mask=0x07,umask=0x80unc_iio_txn_req_of_cpu.cmpd.part6event=0x84,ch_mask=0x40,fc_mask=0x07,umask=0x80unc_iio_txn_req_of_cpu.cmpd.part7event=0x84,ch_mask=0x80,fc_mask=0x07,umask=0x80unc_iio_clockticks_freerunFree running counter that increments for IIO clocktick. Unit: uncore_iio event=0xc2,ch_mask=0x01,fc_mask=0x04,umask=0x03event=0xc2,ch_mask=0x02,fc_mask=0x04,umask=0x03event=0xc2,ch_mask=0x04,fc_mask=0x04,umask=0x03event=0xc2,ch_mask=0x08,fc_mask=0x04,umask=0x03unc_iio_comp_buf_inserts.cmpd.part4event=0xc2,ch_mask=0x10,fc_mask=0x04,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 4. Unit: uncore_iio unc_iio_comp_buf_inserts.cmpd.part5event=0xc2,ch_mask=0x20,fc_mask=0x04,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 5. Unit: uncore_iio unc_iio_comp_buf_inserts.cmpd.part6event=0xc2,ch_mask=0x40,fc_mask=0x04,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 6. Unit: uncore_iio unc_iio_comp_buf_inserts.cmpd.part7event=0xc2,ch_mask=0x80,fc_mask=0x04,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 7. Unit: uncore_iio PCIe Completion Buffer Occupancy of completions with data : Part 0. Unit: uncore_iio unc_iio_comp_buf_occupancy.cmpd.part7event=0xd5,fc_mask=0x04,umask=0x80PCIe Completion Buffer Occupancy of completions with data : Part 7. Unit: uncore_iio unc_iio_comp_buf_occupancy.cmpd.part6event=0xd5,fc_mask=0x04,umask=0x40PCIe Completion Buffer Occupancy of completions with data : Part 6. Unit: uncore_iio unc_iio_comp_buf_occupancy.cmpd.part5event=0xd5,fc_mask=0x04,umask=0x20PCIe Completion Buffer Occupancy of completions with data : Part 5. Unit: uncore_iio unc_iio_comp_buf_occupancy.cmpd.part4event=0xd5,fc_mask=0x04,umask=0x10PCIe Completion Buffer Occupancy of completions with data : Part 4. Unit: uncore_iio PCIe Completion Buffer Occupancy of completions with data : Part 3. Unit: uncore_iio PCIe Completion Buffer Occupancy of completions with data : Part 2. Unit: uncore_iio PCIe Completion Buffer Occupancy of completions with data : Part 1. Unit: uncore_iio event=0xc2,ch_mask=0xff,fc_mask=0x04,umask=0x03PCIe Completion Buffer Inserts of completions with data: Part 0-7. Unit: uncore_iio event=0xd5,fc_mask=0x04,umask=0xffPCIe Completion Buffer Occupancy of completions with data : Part 0-7. Unit: uncore_iio unc_i_misc1.lost_fwdevent=0x1f,umask=0x10Misc Events - Set 1 : Lost Forward. Unit: uncore_irp unc_i_coherent_ops.wbmtoievent=0x10,umask=0x40Coherent Ops : WbMtoI. Unit: uncore_irp event=0xf,umask=0x04Total IRP occupancy of inbound read and write requests to coherent memory. Unit: uncore_irp unc_i_irp_all.inbound_inserts: All Inserts Inbound (p2p + faf + cset). Unit: uncore_irp event=0x11,umask=0x08unc_i_clockticksClockticks of the IO coherency tracker (IRP). Unit: uncore_irp unc_i_faf_fullevent=0x17FAF RF full. Unit: uncore_irp unc_i_faf_transactionsevent=0x16FAF allocation -- sent to ADQ. Unit: uncore_irp unc_i_snoop_resp.all_hit_mevent=0x12,umask=0x78Responses to snoops of any type that hit M line in the IIO cache. Unit: uncore_irp event=0x2d,umask=0x01Multi-socket cacheline Directory Lookups : Found in any state. Unit: uncore_m2m event=0x2d,umask=0x08Multi-socket cacheline Directory Lookups : Found in A state. Unit: uncore_m2m event=0x2d,umask=0x02Multi-socket cacheline Directory Lookups : Found in I state. Unit: uncore_m2m event=0x2d,umask=0x04Multi-socket cacheline Directory Lookups : Found in S state. Unit: uncore_m2m unc_m2m_tag_hit.nm_rd_hit_cleanevent=0x2c,umask=0x01Tag Hit : Clean NearMem Read Hit. Unit: uncore_m2m Tag Hit : Dirty NearMem Read Hit. Unit: uncore_m2m unc_m2m_clockticksClockticks of the mesh to memory (M2M). Unit: uncore_m2m unc_m2m_cms_clockticksCMS Clockticks. Unit: uncore_m2m event=0x37,umask=0x0720M2M Reads Issued to iMC : PMM - All Channels. Unit: uncore_m2m event=0x38,umask=0x1C80M2M Writes Issued to iMC : PMM - All Channels. Unit: uncore_m2m unc_m2p_clockticksClockticks of the mesh to PCI (M2P). Unit: uncore_m2pcie uncore_m2pcieunc_m2p_cms_clockticksCMS Clockticks. Unit: uncore_m2pcie unc_m3upi_clockticksClockticks of the mesh to UPI (M3UPI). Unit: uncore_m3upi unc_u_clockticksClockticks in the UBOX using a dedicated 48-bit Fixed Counter. Unit: uncore_ubox uncore_uboxValid Flits Received : All Data. Unit: uncore_upi Valid Flits Received : All Non Data. Unit: uncore_upi event=0x2,umask=0x0FValid Flits Sent : All Data. Unit: uncore_upi Valid Flits Sent : All Non Data. Unit: uncore_upi Number of kfclks. Unit: uncore_upi Cycles in L1. Unit: uncore_upi Cycles in L0p. Unit: uncore_upi Valid Flits Sent : Null FLITs transmitted to any slot. Unit: uncore_upi Valid Flits Received : Null FLITs received from any slot. Unit: uncore_upi unc_cha_tor_inserts.io_itomcachenear_localevent=0x35,umask=0xCD42FF04TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory. Unit: uncore_cha TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.io_itomcachenear_remoteevent=0x35,umask=0xCD437F04TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory. Unit: uncore_cha unc_cha_tor_inserts.io_itom_localevent=0x35,umask=0xCC42FF04TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory. Unit: uncore_cha TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.io_itom_remoteevent=0x35,umask=0xCC437F04TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory. Unit: uncore_cha event=0x2e,umask=0x01Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode. Unit: uncore_m2m Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM modeClockticks of the power control unit (PCU). Unit: uncore_pcu event=0x8,period=100003,umask=0x8Page walks completed due to a demand data load to a 1G pagePage walks completed due to a demand data store to a 1G pagecore_reject_l2q.anyCounts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full conditionCounts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event).  Counts on a per core basisCounts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetchesCounts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written backl2_reject_xq.anyCounts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full conditionCounts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link.  The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims)l2_request.allevent=0x24,period=200003Counts the total number of L2 Cache accesses. Counts on a per core basisCounts the total number of L2 Cache Accesses, includes hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.  Counts on a per core basisl2_request.hitevent=0x24,period=200003,umask=0x2Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basisCounts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basisl2_request.missCounts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basisCounts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basisl2_request.rejectsCounts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basisCounts the number of L2 Cache accesses that miss the L2 and get BBL reject  short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basisCounts the number of cacheable memory requests that miss in the LLC. Counts on a per core basisCounts the number of cacheable memory requests that miss in the Last Level Cache (LLC). If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basisCounts the number of cacheable memory requests that access the LLC. Counts on a per core basisCounts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basismem_bound_stalls.ifetchevent=0x34,period=200003,umask=0x38Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM)mem_bound_stalls.ifetch_dram_hitevent=0x34,period=200003,umask=0x20Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM)Counts the number of cycles a core is stalled due to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM)mem_bound_stalls.ifetch_l2_hitevent=0x34,period=200003,umask=0x8Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cacheCounts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cachemem_bound_stalls.ifetch_llc_hitevent=0x34,period=200003,umask=0x10Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/MCounts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/Mmem_bound_stalls.loadevent=0x34,period=200003,umask=0x7Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM)mem_bound_stalls.load_dram_hitevent=0x34,period=200003,umask=0x4Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM)mem_bound_stalls.load_l2_hitevent=0x34,period=200003,umask=0x1Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cachemem_bound_stalls.load_llc_hitevent=0x34,period=200003,umask=0x2Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/MCounts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/Mmem_bound_stalls.store_buffer_fullevent=0x34,period=200003,umask=0x40Counts the number of cycles a core is stalled due to a store buffer being fullCounts the number of load ops retired that hit in DRAM  Supports address when precise (Precise event)Counts the number of retired loads that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core  Supports address when precise (Precise event)Counts the number of load uops retired that hit in the L1 data cache  Supports address when precise (Precise event)Counts the number of load uops retired that miss in the L1 data cache  Supports address when precise (Precise event)Counts the number of load uops retired that hit in the L2 cache  Supports address when precise (Precise event)Counts the number of load uops retired that miss in the L2 cache  Supports address when precise (Precise event)event=0xd1,period=200003,umask=0x4Counts the number of load uops retired that hit in the L3 cache (Precise event)Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)  Supports address when precise (Precise event)Counts the number of load uops retired  Supports address when precise (Precise event)Counts the total number of load uops retired  Supports address when precise (Precise event)Counts the number of store uops retired  Supports address when precise (Precise event)Counts the total number of store uops retired  Supports address when precise (Precise event)Counts the number of load uops retired that performed one or more locks  Supports address when precise (Precise event)Counts the number of memory uops retired that were splits  Supports address when precise (Precise event)Counts the number of retired split loads uops  Supports address when precise (Precise event)Counts the number of retired split store uops  Supports address when precise (Precise event)ocr.all_code_rd.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0044Counts all code reads that were supplied by the L3 cacheocr.all_code_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10003C0044Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedocr.all_code_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0044Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedocr.all_code_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0044Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedocr.all_code_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0044Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missedocr.all_code_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0044Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the requestocr.corewb_m.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3001F803C0000Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cacheevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0004Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cacheCounts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedCounts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedCounts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedCounts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missedCounts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the requestocr.demand_data_and_l1pf_rd.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0001Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cacheocr.demand_data_and_l1pf_rd.l3_hit.snoop_hitmCounts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_no_fwdCounts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedocr.demand_data_and_l1pf_rd.l3_hit.snoop_hit_with_fwdCounts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedocr.demand_data_and_l1pf_rd.l3_hit.snoop_missCounts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missedocr.demand_data_and_l1pf_rd.l3_hit.snoop_not_neededCounts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the requestThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HITThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITMThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWDThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDEDevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0002Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cacheCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missedCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the requestocr.full_streaming_wr.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x801F803C0000Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cacheocr.hwpf_l1d_and_swpf.l3_hit.snoop_hitmCounts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedocr.hwpf_l2_code_rd.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0040Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cacheocr.hwpf_l2_code_rd.l3_hit.snoop_hitmCounts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedocr.hwpf_l2_code_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x4003C0040Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedocr.hwpf_l2_code_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003C0040Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedocr.hwpf_l2_code_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0040Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missedocr.hwpf_l2_code_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0040Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the requestocr.hwpf_l2_data_rd.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0010Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cacheCounts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedCounts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedocr.hwpf_l2_data_rd.l3_hit.snoop_hit_with_fwdCounts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedCounts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missedCounts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the requestocr.hwpf_l2_rfo.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0020Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cacheCounts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedCounts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedocr.hwpf_l2_rfo.l3_hit.snoop_hit_with_fwdCounts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedCounts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missedCounts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the requestocr.l1wb_m.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001F803C0000Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cacheocr.l2wb_m.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2001F803C0000Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cacheocr.partial_streaming_wr.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x401F803C0000Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cacheevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cacheCounts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedCounts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedCounts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedocr.reads_to_core.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2003C0477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missedocr.reads_to_core.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1003C0477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the requestevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1F803C0800Counts streaming stores that were supplied by the L3 cacheocr.uc_rd.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x101F803C0000Counts uncached memory reads that were supplied by the L3 cacheocr.uc_rd.l3_hit.snoop_hitmevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1010003C0000Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwardedocr.uc_rd.l3_hit.snoop_hit_no_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1004003C0000Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwardedocr.uc_rd.l3_hit.snoop_hit_with_fwdevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1008003C0000Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwardedocr.uc_rd.l3_hit.snoop_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002003C0000Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missedocr.uc_rd.l3_hit.snoop_not_neededevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1001003C0000Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the requestocr.uc_wr.l3_hitevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x201F803C0000Counts uncached memory writes that were supplied by the L3 cachetopdown_fe_bound.icacheevent=0x71,period=1000003,umask=0x20Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache missesCounts the number of cycles the floating point divider is busy.  Does not imply a stall waiting for the dividerCounts the number of floating point operations retired that required microcode assistCounts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uopsCounts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt) (Precise event)Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branchesCounts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branchesCounts the number of BACLEARS due to a conditional jumpbaclears.indirectevent=0xe6,period=200003,umask=0x2Counts the number of BACLEARS due to an indirect branchCounts the number of BACLEARS due to a return branchbaclears.uncondevent=0xe6,period=200003,umask=0x4Counts the number of BACLEARS due to a direct, unconditional jumpCounts the number of times a decode restriction reduces the decode throughput due to wrong instruction length predictionCounts the number of requests to the instruction cache for one or more bytes of a cache lineCounts the total number of requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same lineCounts the number of instruction cache hitsCounts the number of requests that hit in the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same lineCounts the number of instruction cache missesCounts the number of missed requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same lineCounts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguationCounts the number of misaligned load uops that are 4K page splits (Precise event)Counts the number of misaligned store uops that are 4K page splits (Precise event)ocr.all_code_rd.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000044Counts all code reads that were not supplied by the L3 cacheocr.all_code_rd.l3_miss_localocr.corewb_m.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3002184000000Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cacheocr.corewb_m.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000004Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cacheocr.demand_data_and_l1pf_rd.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000001Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cacheocr.demand_data_and_l1pf_rd.l3_miss_localThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISSThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCALevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000002Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cacheocr.full_streaming_wr.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x802184000000Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cacheocr.full_streaming_wr.l3_miss_localocr.hwpf_l2_code_rd.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000040Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cacheocr.hwpf_l2_code_rd.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000010Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cacheocr.hwpf_l2_data_rd.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000020Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cacheocr.hwpf_l2_rfo.l3_miss_localocr.l1wb_m.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1002184000000Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cacheocr.l1wb_m.l3_miss_localocr.l2wb_m.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2002184000000Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cacheocr.l2wb_m.l3_miss_localevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184008000Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cacheocr.partial_streaming_wr.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x402184000000Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cacheocr.partial_streaming_wr.l3_miss_localocr.prefetches.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000470Counts all hardware and software prefetches that were not supplied by the L3 cacheevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cacheevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2184000800Counts streaming stores that were not supplied by the L3 cacheocr.uc_rd.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x102184000000Counts uncached memory reads that were not supplied by the L3 cacheocr.uc_rd.l3_miss_localocr.uc_wr.l3_missevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x202184000000Counts uncached memory writes that were not supplied by the L3 cacheocr.uc_wr.l3_miss_localbus_lock.allevent=0x63,edge=1,period=200003This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKSbus_lock.block_cyclesevent=0x63,period=200003,umask=0x2Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other coresCounts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basisbus_lock.cycles_other_blockThis event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLESbus_lock.cycles_self_blockevent=0x63,period=200003,umask=0x1This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLESbus_lock.lock_cyclesCounts the number of unhalted cycles a core is blocked due to an accepted lock it issuedCounts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basisbus_lock.self_locksCounts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locksCounts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basisc0_stalls.load_dram_hitThis event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HITc0_stalls.load_l2_hitThis event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HITc0_stalls.load_llc_hitThis event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HITCounts the number of core cycles during which interrupts are masked (disabled)Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled)Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR)  because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be importantCounts the number of hardware interrupts received by the processorocr.all_code_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10044Counts all code reads that have any type of responseocr.all_code_rd.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000044Counts all code reads that were supplied by DRAMocr.all_code_rd.local_dramocr.all_code_rd.outstandingevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000044Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency)ocr.corewb_m.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x3000000010000Counts modified writebacks from L1 cache and L2 cache that have any type of responseocr.corewb_m.outstandingevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8003000000000000Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency)ocr.demand_data_and_l1pf_rd.any_responseCounts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of responseocr.demand_data_and_l1pf_rd.dramCounts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAMocr.demand_data_and_l1pf_rd.local_dramocr.demand_data_and_l1pf_rd.outstandingevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000001Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency)This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSEThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAMThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAMocr.demand_data_rd.outstandingThis event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDINGCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of responseCounts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAMocr.demand_rfo.outstandingevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000002Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency)ocr.full_streaming_wr.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x800000010000Counts streaming stores which modify a full 64 byte cacheline that have any type of responseCounts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of responseocr.hwpf_l2_code_rd.any_responseCounts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of responseocr.hwpf_l2_code_rd.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000040Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAMocr.hwpf_l2_code_rd.local_dramocr.hwpf_l2_code_rd.outstandingevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000040Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency)Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of responseCounts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAMCounts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of responseCounts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAMocr.hwpf_l2_rfo.outstandingevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000020Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency)ocr.l1wb_m.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x1000000010000Counts modified writebacks from L1 cache that miss the L2 cache that have any type of responseocr.l2wb_m.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2000000010000Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of responseCounts miscellaneous requests, such as I/O accesses, that have any type of responseocr.partial_streaming_wr.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x400000010000Counts streaming stores which modify only part of a 64 byte cacheline that have any type of responseocr.prefetches.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10470Counts all hardware and software prefetches that have any type of responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x10477event=0xb7,period=100003,umask=0x1,offcore_rsp=0x184000477ocr.reads_to_core.outstandingevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000000000000477Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency)ocr.uc_rd.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100000010000Counts uncached memory reads that have any type of responseocr.uc_rd.dramevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x100184000000Counts uncached memory reads that were supplied by DRAMocr.uc_rd.local_dramocr.uc_rd.outstandingevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x8000100000000000Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency)ocr.uc_wr.any_responseevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x200000010000Counts uncached memory writes that have any type of responseCounts the total number of branch instructions retired for all branch types (Precise event)Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for (Precise event)Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return (Precise event)Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches (Precise event)Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired (Precise event)Counts the total number of mispredicted branch instructions retired for all branch types (Precise event)Counts the total number of mispredicted branch instructions retired.  All branch type instructions are accounted for.  Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP.    A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path (Precise event)Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired (Precise event)Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired (Precise event)btclear.anyevent=0xe8,period=200003Counts the total number of BTCLEARSCounts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branchCounts the number of unhalted core clock cycles. (Fixed event)Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counterCounts the number of unhalted reference clock cycles at TSC frequencyCounts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)cpu_clk_unhalted.ref_tsc_pCounts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance countercycles_div_busy.anyThis event is deprecatedCounts the number of cycles the integer divider is busy.  Does not imply a stall waiting for the dividerCounts the total number of instructions retired. (Fixed event) (Precise event)Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0 (Precise event)Counts the total number of instructions retired (Precise event)Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter (Precise event)event=0x3,period=1000003,umask=0x4Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check (Precise event)ld_blocks.allevent=0x3,period=1000003,umask=0x10Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) (Precise event)event=0x3,period=1000003,umask=0x1Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready (Precise event)event=0x3,period=1000003,umask=0x2Counts the number of retired loads that are blocked because its address partially overlapped with an older store (Precise event)machine_clears.anyCounts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assistCounts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPUCounts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occursCounts the number of machine clears due typically to program modifying data (self modifying code) within 1K of a recently fetched code pagetopdown_bad_speculation.allevent=0x73,period=1000003,umask=0x6Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clearCounts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine cleartopdown_bad_speculation.fastnukeevent=0x73,period=1000003,umask=0x2Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clearstopdown_bad_speculation.machine_clearsCounts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguationtopdown_bad_speculation.mispredictevent=0x73,period=1000003,umask=0x4Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredictstopdown_bad_speculation.monukeThis event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKEtopdown_be_bound.allevent=0x74,period=1000003Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stallstopdown_be_bound.alloc_restrictionsevent=0x74,period=1000003,umask=0x1Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictionstopdown_be_bound.mem_schedulerevent=0x74,period=1000003,umask=0x2Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uopstopdown_be_bound.non_mem_schedulerevent=0x74,period=1000003,umask=0x8Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uopstopdown_be_bound.registerevent=0x74,period=1000003,umask=0x20Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)topdown_be_bound.reorder_bufferevent=0x74,period=1000003,umask=0x40Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls)topdown_be_bound.serializationevent=0x74,period=1000003,umask=0x10Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)topdown_be_bound.store_bufferevent=0x74,period=1000003,umask=0x4topdown_fe_bound.allevent=0x71,period=1000003Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stallstopdown_fe_bound.branch_detectevent=0x71,period=1000003,umask=0x2Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARSCounts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branchestopdown_fe_bound.branch_resteerevent=0x71,period=1000003,umask=0x40Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARSCounts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branchtopdown_fe_bound.ciscevent=0x71,period=1000003,umask=0x1Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS)topdown_fe_bound.decodeevent=0x71,period=1000003,umask=0x8Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stallstopdown_fe_bound.frontend_bandwidthevent=0x71,period=1000003,umask=0x8dCounts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitationstopdown_fe_bound.frontend_latencyevent=0x71,period=1000003,umask=0x72Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache missestopdown_fe_bound.itlbevent=0x71,period=1000003,umask=0x10Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB missesCounts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) missestopdown_fe_bound.otherevent=0x71,period=1000003,umask=0x80Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorizedtopdown_fe_bound.predecodeevent=0x71,period=1000003,umask=0x4Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodestopdown_retiring.allevent=0xc2,period=1000003Counts the total number of consumed retirement slots (Precise event)Counts the number of uops issued by the front end every cycleCounts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2.  Uops_issued correlates to the number of ROB entries.  If uop takes 2 ROB slots it counts as 2 uops_issuedCounts the total number of uops retired (Precise event)Counts the number of integer divide uops retired (Precise event)Counts the number of uops that are from complex flows issued by the micro-sequencer (MS) (Precise event)Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows (Precise event)uops_retired.x87Counts the number of x87 uops retired, includes those in MS flows (Precise event)DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of ActivatesCounts the total number of DRAM CAS commands issued on this channelNumber of DRAM Refreshes Issued : Counts the number of refreshes issuedHalf clockticks for IMCDRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channelDRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page TableRead Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requestsRead Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memoryWrite Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMCWrite Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode countsevent=0x35,umask=0xC001FE01,config1=0x40e33event=0x35,umask=0xC001FE01,config1=0x40040e33event=0x35,umask=0xC001FE01,config1=0x40041e33event=0x35,umask=0xC001FE01,config1=0x41833event=0x35,umask=0xC001FE01,config1=0x41a33CMS ClockticksCounts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channelsCounts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactionsLines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was inCounts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cachelineCounts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cachelineCounts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cachelineTOR Inserts : All requests from iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_drd_optevent=0x35,umask=0xC827FF01TOR Inserts : DRd_Opts issued by iA Cores. Unit: uncore_cha TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_drd_opt_prefevent=0x35,umask=0xC8A7FF01TOR Inserts : DRd_Opt_Prefs issued by iA Cores. Unit: uncore_cha TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_hit_drd_optevent=0x35,umask=0xC827FD01TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC. Unit: uncore_cha TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_hit_drd_opt_prefevent=0x35,umask=0xC8A7FD01TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC. Unit: uncore_cha TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_miss_drd_optevent=0x35,umask=0xC827FE01TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC. Unit: uncore_cha TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_miss_drd_opt_prefevent=0x35,umask=0xC8A7FE01TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC. Unit: uncore_cha TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts; Data read from local IA that misses in the snoop filterTOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_miss_ucrdfevent=0x35,umask=0xC877DE01TOR Inserts : UCRdFs issued by iA Cores that Missed LLC. Unit: uncore_cha TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_miss_wcilevent=0x35,umask=0xC86FFE01TOR Inserts : WCiLs issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_miss_wcilfevent=0x35,umask=0xC867FE01TOR Inserts : WCiLF issued by iA Cores that Missed the LLC. Unit: uncore_cha TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsunc_cha_tor_inserts.ia_miss_wilevent=0x35,umask=0xC87FDE01TOR Inserts : WiLs issued by iA Cores that Missed LLC. Unit: uncore_cha TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : All requests from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interruptsTOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsunc_cha_tor_occupancy.ia_drd_optevent=0x36,umask=0xC827FF01TOR Occupancy : DRd_Opts issued by iA Cores. Unit: uncore_cha TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsunc_cha_tor_occupancy.ia_drd_opt_prefevent=0x36,umask=0xC8A7FF01TOR Occupancy : DRd_Opt_Prefs issued by iA Cores. Unit: uncore_cha TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsunc_cha_tor_occupancy.ia_hit_drd_optevent=0x36,umask=0xC827FD01TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC. Unit: uncore_cha TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsunc_cha_tor_occupancy.ia_hit_drd_opt_prefevent=0x36,umask=0xC8A7FD01TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC. Unit: uncore_cha TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsunc_cha_tor_occupancy.ia_miss_drd_optevent=0x36,umask=0xC827FE01TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC. Unit: uncore_cha TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsTOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.     Does not include addressless requests such as locks and interruptsClockticks of the integrated IO (IIO) traffic controllerFree running counter that increments for integrated IO (IIO) traffic controller clockticksPCIe Completion Buffer Inserts of completions with data : Part 0-7PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7PCIe Completion Buffer Occupancy : Part 0-7PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die.  Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die.    Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPUNumber Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound.  Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound.  Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7Total IRP occupancy of inbound read and write requests to coherent memory.  This is effectively the sum of read occupancy and write occupancyClockticks of the IO coherency tracker (IRP)Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRPFAF RF fullFAF allocation -- sent to ADQ: All Inserts Inbound (p2p + faf + cset)Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committedResponses to snoops of any type (code, data, invalidate) that hit M line in the IIO cacheClockticks of the mesh to memory (M2M)Clockticks of the mesh to PCI (M2P)Clockticks in the UBOX using a dedicated 48-bit Fixed CounterClockticks of the power control unit (PCU)event=0x8,period=200003,umask=0x80Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cacheevent=0x8,period=200003,umask=0x20Counts the number of first level TLB misses but second level hits due to loads that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLBevent=0x8,period=200003,umask=0xeCounts the number of page walks completed due to load DTLB misses to any page sizeCounts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page faultCounts the number of page walks completed due to load DTLB misses to a 1G pageCounts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page faultCounts the number of page walks completed due to load DTLB misses to a 2M or 4M pageCounts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page faultCounts the number of page walks completed due to load DTLB misses to a 4K pageCounts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page faultCounts the number of page walks outstanding in the page miss handler (PMH) for loads every cycleCounts the number of page walks outstanding in the page miss handler (PMH) for loads every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervalsevent=0x49,period=2000003,umask=0x80Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cacheCounts the number of page walks due to storse that miss the PDE (Page Directory Entry) cacheevent=0x49,period=2000003,umask=0x20Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLBevent=0x49,period=200003,umask=0xeCounts the number of page walks completed due to store DTLB misses to any page sizeCounts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page faultevent=0x49,period=200003,umask=0x8Counts the number of page walks completed due to store DTLB misses to a 1G pageCounts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.  Includes page walks that page faultCounts the number of page walks completed due to store DTLB misses to a 2M or 4M pageCounts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page faultCounts the number of page walks completed due to store DTLB misses to a 4K pageCounts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page faultCounts the number of page walks outstanding in the page miss handler (PMH) for stores every cycleCounts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervalsept.epde_hitevent=0x4f,period=2000003,umask=0x2Counts the number of Extended Page Directory Entry hitsCounts the number of Extended Page Directory Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesept.epde_missevent=0x4f,period=2000003,umask=0x1Counts the number of Extended Page Directory Entry missesCounts the number Extended Page Directory Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesept.epdpe_hitevent=0x4f,period=2000003,umask=0x4Counts the number of Extended Page Directory Pointer Entry hitsCounts the number Extended Page Directory Pointer Entry hits.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesept.epdpe_missevent=0x4f,period=2000003,umask=0x8Counts the number of Extended Page Directory Pointer Entry missesCounts the number Extended Page Directory Pointer Entry misses.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesCounts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycleCounts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB cachesitlb.fillsCounts the number of times there was an ITLB miss and a new translation was filled into the ITLBCounts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLBitlb_misses.pde_cache_missevent=0x85,period=2000003,umask=0x80Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cacheevent=0x85,period=2000003,umask=0x20Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will results in a DTLB write from STLBevent=0x85,period=200003,umask=0xeCounts the number of page walks completed due to instruction fetch misses to any page sizeCounts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page faultevent=0x85,period=200003,umask=0x8Counts the number of page walks completed due to instruction fetch misses to a 1G pageCounts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages.  Includes page walks that page faultCounts the number of page walks completed due to instruction fetch misses to a 2M or 4M pageCounts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages.  Includes page walks that page faultCounts the number of page walks completed due to instruction fetch misses to a 4K pageCounts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages.  Includes page walks that page faultCounts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycleCounts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.  A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk)ld_blocks.dtlb_missevent=0x3,period=1000003,umask=0x8Counts the number of retired loads that are blocked due to a first level TLB miss (Precise event)Counts the number of memory retired ops that missed in the second level TLB  Supports address when precise (Precise event)Counts the number of load ops retired that miss in the second Level TLB  Supports address when precise (Precise event)Counts the number of store ops retired that miss in the second level TLB  Supports address when precise (Precise event)Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cacheCounts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/MCounts the number of cycles a core is stalled due to a demand load which hit in the L2 cacheCounts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/MCounts the number of load ops retired that hit in DRAM  Supports address when preciseehl metricsINST_RETIRED.ANY / cyclescyclesTotal number of retired Instructions64 * LONGEST_LAT_CACHE.MISS / 1000000000 (cycles / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 cycles / CPU_CLK_UNHALTED.REF_TSCcycles:k / cyclesCounts the total number of BACLEARSCounts the number of BACLEARS due to a non-indirect, non-conditional jumpCounts the number of memory ordering machine clears triggered by a snoop from an external agentCounts the number of memory ordering machine clears triggered by a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguationsevent=0xb7,period=100003,umask=0x1,offcore_rsp=0x2104000001event=0xb7,period=100003,umask=0x1,offcore_rsp=0x2104000002Counts the total number of machine clears including memory ordering, memory disambiguation, self-modifying code, page faults and floating point assistCounts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clearTotal pipeline cost of branch related instructions (used for program control-flow including function calls). Unit: cpu_core adl metricscpu_coreInstructions Per Cycle (per Logical Processor). Unit: cpu_core Cycles Per Instruction (per Logical Processor). Unit: cpu_core Per-Logical Processor actual clocks when the Logical Processor is active. Unit: cpu_core Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward). Unit: cpu_core Fraction of Physical Core issue-slots utilized by this Logical Processor. Unit: cpu_core The ratio of Executed- by Issued-Uops. Unit: cpu_core Instructions Per Cycle across hyper-threads (per physical core). Unit: cpu_core Floating Point Operations Per Cycle. Unit: cpu_core ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTEDActual per-core usage of the Floating Point execution units (regardless of the vector width). Unit: cpu_core ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed). Unit: cpu_core Number of Instructions per non-speculative Branch Misprediction (JEClear). Unit: cpu_core Core actual clocks when any Logical Processor is active on the Physical Core. Unit: cpu_core Instructions per Load (lower number means higher occurrence rate). Unit: cpu_core Instructions per Store (lower number means higher occurrence rate). Unit: cpu_core Instructions per Branch (lower number means higher occurrence rate). Unit: cpu_core Instructions per (near) call (lower number means higher occurrence rate). Unit: cpu_core Instruction per taken branch. Unit: cpu_core Branch instructions per taken branch. Unit: cpu_core Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate). Unit: cpu_core Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Unit: cpu_core Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Unit: cpu_core Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Unit: cpu_core Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Unit: cpu_core Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Unit: cpu_core Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST. Unit: cpu_core Average number of Uops issued by front-end when it issued something. Unit: cpu_core UOPS_ISSUED.ANY / cpu_core@UOPS_ISSUED.ANY\,cmask\=1@Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache). Unit: cpu_core Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Unit: cpu_core Number of Instructions per non-speculative DSB miss. Unit: cpu_core Fraction of branches that are non-taken conditionals. Unit: cpu_core Fraction of branches that are taken conditionals. Unit: cpu_core Fraction of branches that are CALL or RET. Unit: cpu_core Fraction of branches that are unconditional (direct or indirect) jumps. Unit: cpu_core Fraction of branches of other types (not individually covered by other metrics in Info.Branches group). Unit: cpu_core Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Unit: cpu_core Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor). Unit: cpu_core Average data fill bandwidth to the L1 data cache [GB / sec]. Unit: cpu_core Average data fill bandwidth to the L2 cache [GB / sec]. Unit: cpu_core Average per-core data fill bandwidth to the L3 cache [GB / sec]. Unit: cpu_core Average per-core data access bandwidth to the L3 cache [GB / sec]. Unit: cpu_core L1 cache true misses per kilo instruction for retired demand loads. Unit: cpu_core L1 cache true misses per kilo instruction for all demand loads (including speculative). Unit: cpu_core L2 cache true misses per kilo instruction for retired demand loads. Unit: cpu_core L2 cache misses per kilo instruction for all request types (including speculative). Unit: cpu_core L2 cache misses per kilo instruction for all demand loads  (including speculative). Unit: cpu_core L2 cache hits per kilo instruction for all request types (including speculative). Unit: cpu_core L2 cache hits per kilo instruction for all demand loads  (including speculative). Unit: cpu_core L3 cache true misses per kilo instruction for retired demand loads. Unit: cpu_core Fill Buffer (FB) true hits per kilo instructions for retired demand loads. Unit: cpu_core Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses. Unit: cpu_core ( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 4 * CPU_CLK_UNHALTED.DISTRIBUTED )Average CPU Utilization. Unit: cpu_core Measured Average Frequency for unhalted processors [GHz]. Unit: cpu_core Giga Floating Point Operations Per Second. Unit: cpu_core Average Frequency Utilization relative nominal frequency. Unit: cpu_core Fraction of cycles where both hardware Logical Processors were active. Unit: cpu_core Fraction of cycles spent in the Operating System (OS) Kernel mode. Unit: cpu_core Cycles Per Instruction for the Operating System (OS) Kernel mode. Unit: cpu_core Average external Memory Bandwidth Use for reads and writes [GB / sec]. Unit: cpu_core Average number of parallel requests to external memory. Accounts for all requests. Unit: cpu_core Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]. Unit: cpu_core Counts the number of issue slots  that were not consumed by the backend due to frontend stalls. Unit: cpu_atom cpu_atomTOPDOWN_FE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Unit: cpu_atom TOPDOWN_BAD_SPECULATION.ALL / (5 * CPU_CLK_UNHALTED.CORE)Counts the total number of issue slots  that were not consumed by the backend due to backend stalls. Unit: cpu_atom Counts the total number of issue slots  that were not consumed by the backend due to backend stalls.  Note that uops must be available for consumption in order for this event to count.  If a uop is not available (IQ is empty), this event will not count.   The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound.   The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot basedTOPDOWN_BE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)Counts the total number of issue slots  that were not consumed by the backend due to backend stalls.  Note that UOPS must be available for consumption in order for this event to count.  If a uop is not available (IQ is empty), this event will not count.  All of these subevents count backend stalls, in slots, due to a resource limitation.   These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based.  These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocationBackend_Bound_AuxCounts the numer of issue slots  that result in retirement slots. Unit: cpu_atom TOPDOWN_RETIRING.ALL / (5 * CPU_CLK_UNHALTED.CORE)Unit: cpu_atom CPU_CLK_UNHALTED.CORECPU_CLK_UNHALTED.CORE_PCLKS_P5 * CPU_CLK_UNHALTED.COREInstructions Per Cycle. Unit: cpu_atom INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORECycles Per Instruction. Unit: cpu_atom CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANYUops Per Instruction. Unit: cpu_atom UOPS_RETIRED.ALL / INST_RETIRED.ANYPercentage of total non-speculative loads with a store forward or unknown store address block. Unit: cpu_atom 100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADSStore_Fwd_BlocksPercentage of total non-speculative loads with a address aliasing block. Unit: cpu_atom 100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADSAddress_Alias_BlocksPercentage of total non-speculative loads that are splits. Unit: cpu_atom 100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADSLoad_SplitsInstructions per Branch (lower number means higher occurrence rate). Unit: cpu_atom Instruction per (near) call (lower number means higher occurrence rate). Unit: cpu_atom INST_RETIRED.ANY / BR_INST_RETIRED.CALLInstructions per Load. Unit: cpu_atom Instructions per Store. Unit: cpu_atom Number of Instructions per non-speculative Branch Misprediction. Unit: cpu_atom Instructions per Far Branch. Unit: cpu_atom INST_RETIRED.ANY / ( BR_INST_RETIRED.FAR_BRANCH / 2 )Ratio of all branches which mispredict. Unit: cpu_atom BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHESBranch_Mispredict_RatioRatio between Mispredicted branches and unknown branches. Unit: cpu_atom BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANYBranch_Mispredict_to_Unknown_Branch_RatioPercentage of all uops which are ucode ops. Unit: cpu_atom 100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALLMicrocode_Uop_RatioPercentage of all uops which are FPDiv uops. Unit: cpu_atom 100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALLFPDiv_Uop_RatioPercentage of all uops which are IDiv uops. Unit: cpu_atom 100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALLIDiv_Uop_RatioPercentage of all uops which are x87 uops. Unit: cpu_atom 100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALLX87_Uop_RatioAverage Frequency Utilization relative nominal frequency. Unit: cpu_atom CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSCFraction of cycles spent in Kernel mode. Unit: cpu_atom CPU_CLK_UNHALTED.CORE:k / CPU_CLK_UNHALTED.COREAverage CPU Utilization. Unit: cpu_atom Estimated Pause cost. In percent. Unit: cpu_atom 100 * SERIALIZATION.NON_C01_MS_SCB / ( 5 * CPU_CLK_UNHALTED.CORE )Estimated_Pause_CostCycle cost per L2 hit. Unit: cpu_atom MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HITCycles_per_Demand_Load_L2_HitCycle cost per LLC hit. Unit: cpu_atom MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HITCycles_per_Demand_Load_L3_HitCycle cost per DRAM hit. Unit: cpu_atom MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HITCycles_per_Demand_Load_DRAM_HitPercent of instruction miss cost that hit in the L2. Unit: cpu_atom 100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / ( MEM_BOUND_STALLS.IFETCH )Inst_Miss_Cost_L2Hit_PercentPercent of instruction miss cost that hit in the L3. Unit: cpu_atom 100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / ( MEM_BOUND_STALLS.IFETCH )Inst_Miss_Cost_L3Hit_PercentPercent of instruction miss cost that hit in DRAM. Unit: cpu_atom 100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / ( MEM_BOUND_STALLS.IFETCH )Inst_Miss_Cost_DRAMHit_Percentload ops retired per 1000 instruction. Unit: cpu_atom 1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANYMemLoadPKICounts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM). Unit: cpu_atom Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in DRAM or MMIO (Non-DRAM). Unit: cpu_atom Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2 cache. Unit: cpu_atom Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the last level cache or other core with HITE/F/M. Unit: cpu_atom Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM). Unit: cpu_atom Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM). Unit: cpu_atom Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache. Unit: cpu_atom Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M. Unit: cpu_atom Counts the number of load ops retired that hit in DRAM  Supports address when precise (Precise event). Unit: cpu_atom Counts the number of load ops retired that hit in the L2 cache  Supports address when precise (Precise event). Unit: cpu_atom Counts the number of load ops retired that hit in the L3 cache (Precise event). Unit: cpu_atom mem_scheduler_block.allevent=0x4,period=20003,umask=0x7Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full. Unit: cpu_atom mem_scheduler_block.ld_bufevent=0x4,period=20003,umask=0x2Counts the number of cycles that uops are blocked due to a load buffer full condition. Unit: cpu_atom mem_scheduler_block.rsvevent=0x4,period=20003,umask=0x4Counts the number of cycles that uops are blocked due to an RSV full condition. Unit: cpu_atom mem_scheduler_block.st_bufevent=0x4,period=20003,umask=0x1Counts the number of cycles that uops are blocked due to a store buffer full condition. Unit: cpu_atom Counts the number of load uops retired  Supports address when precise (Precise event). Unit: cpu_atom Counts the number of store uops retired  Supports address when precise (Precise event). Unit: cpu_atom mem_uops_retired.load_latency_gt_128event=0xd0,period=1000003,umask=0x5,ldlat=0x80Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise (Must be precise). Unit: cpu_atom mem_uops_retired.load_latency_gt_16event=0xd0,period=1000003,umask=0x5,ldlat=0x10Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise (Must be precise). Unit: cpu_atom mem_uops_retired.load_latency_gt_256event=0xd0,period=1000003,umask=0x5,ldlat=0x100Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise (Must be precise). Unit: cpu_atom mem_uops_retired.load_latency_gt_32event=0xd0,period=1000003,umask=0x5,ldlat=0x20Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise (Must be precise). Unit: cpu_atom mem_uops_retired.load_latency_gt_4event=0xd0,period=1000003,umask=0x5,ldlat=0x4Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise (Must be precise). Unit: cpu_atom mem_uops_retired.load_latency_gt_512event=0xd0,period=1000003,umask=0x5,ldlat=0x200Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise (Must be precise). Unit: cpu_atom mem_uops_retired.load_latency_gt_64event=0xd0,period=1000003,umask=0x5,ldlat=0x40Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise (Must be precise). Unit: cpu_atom mem_uops_retired.load_latency_gt_8event=0xd0,period=1000003,umask=0x5,ldlat=0x8Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled  Supports address when precise (Must be precise). Unit: cpu_atom Counts all the retired split loads  Supports address when precise (Precise event). Unit: cpu_atom mem_uops_retired.store_latencyevent=0xd0,period=1000003,umask=0x6Counts the number of stores uops retired. Counts with or without PEBS enabled (Precise event). Unit: cpu_atom Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses. Unit: cpu_atom Counts the number of cache lines replaced in L1 data cache. Unit: cpu_core Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Unit: cpu_core Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Unit: cpu_core This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS. Unit: cpu_core l1d_pend_miss.l2_stallsNumber of cycles a demand request has waited due to L1D due to lack of L2 resources. Unit: cpu_core Number of L1D misses that are outstanding. Unit: cpu_core Cycles with L1D load Misses outstanding. Unit: cpu_core event=0x25,period=100003,umask=0x1fL2 cache lines filling L2. Unit: cpu_core All L2 requests.[This event is alias to L2_RQSTS.REFERENCES]. Unit: cpu_core Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]. Unit: cpu_core L2 code requests. Unit: cpu_core Demand Data Read requests. Unit: cpu_core Demand requests that miss L2 cache. Unit: cpu_core RFO requests to L2 cache. Unit: cpu_core L2 cache hits when fetching instructions, code reads. Unit: cpu_core L2 cache misses when fetching instructions. Unit: cpu_core Demand Data Read requests that hit L2 cache. Unit: cpu_core Demand Data Read miss L2, no rejects. Unit: cpu_core Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]. Unit: cpu_core All L2 requests.[This event is alias to L2_REQUEST.ALL]. Unit: cpu_core RFO requests that hit L2 cache. Unit: cpu_core RFO requests that miss L2 cache. Unit: cpu_core SW prefetch requests that hit L2 cache. Unit: cpu_core SW prefetch requests that miss L2 cache. Unit: cpu_core TBD. Unit: cpu_core All retired load instructions  Supports address when precise (Precise event). Unit: cpu_core All retired store instructions  Supports address when precise (Precise event). Unit: cpu_core All retired memory instructions  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions with locked access  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions that split across a cacheline boundary  Supports address when precise (Precise event). Unit: cpu_core Retired store instructions that split across a cacheline boundary  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions that miss the STLB  Supports address when precise (Precise event). Unit: cpu_core Retired store instructions that miss the STLB  Supports address when precise (Precise event). Unit: cpu_core mem_load_completed.l1_miss_anyevent=0x43,period=1000003,umask=0xfdCompleted demand load uops that miss the L1 d-cache. Unit: cpu_core Retired load instructions whose data sources were HitM responses from shared L3  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions whose data sources were hits in L3 without snoops required  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions which data sources missed L3 but serviced from local dram  Supports address when precise. Unit: cpu_core Retired instructions with at least 1 uncacheable load or lock  Supports address when precise (Precise event). Unit: cpu_core Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions with L1 cache hits as data sources  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions missed L1 cache as data sources  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions with L2 cache hits as data sources  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions missed L2 cache as data sources  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions with L3 cache hits as data sources  Supports address when precise (Precise event). Unit: cpu_core Retired load instructions missed L3 cache as data sources  Supports address when precise (Precise event). Unit: cpu_core mem_store_retired.l2_hitevent=0x44,period=200003,umask=0x1mem_uop_retired.anyevent=0xe5,period=1000003,umask=0x3Retired memory uops for any access. Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0001Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x8003C0001DEMAND_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD. Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0002Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. Unit: cpu_core event=0x21,period=100003,umask=0x80offcore_requests.data_rdevent=0x21,period=100003,umask=0x8Demand and prefetch data reads. Unit: cpu_core event=0x21,period=100003,umask=0x1Demand Data Read requests sent to uncore. Unit: cpu_core event=0x20,period=1000003,umask=0x8This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD. Unit: cpu_core event=0x20,cmask=1,period=1000003,umask=0x8event=0x20,cmask=1,period=1000003,umask=0x4For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1. Unit: cpu_core offcore_requests_outstanding.data_rdevent=0x40,period=100003,umask=0x1Number of PREFETCHNTA instructions executed. Unit: cpu_core event=0x40,period=100003,umask=0x8Number of PREFETCHW instructions executed. Unit: cpu_core event=0x40,period=100003,umask=0x2Number of PREFETCHT0 instructions executed. Unit: cpu_core event=0x40,period=100003,umask=0x4Number of PREFETCHT1 or PREFETCHT2 instructions executed. Unit: cpu_core Counts the number of floating point operations retired that required microcode assist. Unit: cpu_atom Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt) (Precise event). Unit: cpu_atom arith.fpdiv_activeevent=0xb0,cmask=1,period=1000003,umask=0x1Counts all microcode FP assists. Unit: cpu_core assists.sse_avx_mixevent=0xc1,period=1000003,umask=0x10fp_arith_dispatched.port_0event=0xb3,period=2000003,umask=0x1fp_arith_dispatched.port_1event=0xb3,period=2000003,umask=0x2fp_arith_dispatched.port_5event=0xb3,period=2000003,umask=0x4Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. Unit: cpu_core Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. Unit: cpu_atom Counts the number of requests to the instruction cache for one or more bytes of a cache line. Unit: cpu_atom Counts the number of instruction cache misses. Unit: cpu_atom decode.lcpStalls caused by changing prefix length of the instruction. Unit: cpu_core event=0x61,period=100003,umask=0x2DSB-to-MITE switch true penalty cycles. Unit: cpu_core Retired Instructions who experienced DSB miss (Precise event). Unit: cpu_core Retired Instructions who experienced a critical DSB miss (Precise event). Unit: cpu_core Retired Instructions who experienced iTLB true miss (Precise event). Unit: cpu_core Retired Instructions who experienced Instruction L1 Cache true miss (Precise event). Unit: cpu_core Retired Instructions who experienced Instruction L2 Cache true miss (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x600106Retired instructions after front-end starvation of at least 1 cycle (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x608006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x601006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x600206Retired instructions after front-end starvation of at least 2 cycles (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x610006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x602006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x600406Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x620006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x604006Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core event=0xc6,period=100007,umask=0x1,frontend=0x600806Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event). Unit: cpu_core Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event). Unit: cpu_core frontend_retired.unknown_branchevent=0xc6,period=100007,umask=0x1,frontend=0x17TBD (Precise event). Unit: cpu_core icache_data.stallsCycles where a code fetch is stalled due to L1 instruction cache miss. Unit: cpu_core icache_tag.stallsCycles where a code fetch is stalled due to L1 instruction cache tag miss. Unit: cpu_core Cycles Decode Stream Buffer (DSB) is delivering any Uop. Unit: cpu_core event=0x79,cmask=6,period=2000003,umask=0x8Cycles DSB is delivering optimal number of Uops. Unit: cpu_core Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Unit: cpu_core Cycles MITE is delivering any Uop. Unit: cpu_core event=0x79,cmask=6,period=2000003,umask=0x4Cycles MITE is delivering optimal number of Uops. Unit: cpu_core Uops delivered to Instruction Decode Queue (IDQ) from MITE path. Unit: cpu_core event=0x79,cmask=1,period=2000003,umask=0x20Cycles when uops are being delivered to IDQ while MS is busy. Unit: cpu_core event=0x79,cmask=1,edge=1,period=100003,umask=0x20Number of switches from DSB or MITE to the MS. Unit: cpu_core event=0x79,period=1000003,umask=0x20Uops delivered to IDQ while MS is busy. Unit: cpu_core Uops not delivered by IDQ when backend of the machine is not stalled. Unit: cpu_core event=0x9c,cmask=6,period=1000003,umask=0x1Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled. Unit: cpu_core Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled. Unit: cpu_core ld_head.any_at_retevent=0x5,period=1000003,umask=0xffCounts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires. Unit: cpu_atom ld_head.l1_bound_at_retevent=0x5,period=1000003,umask=0xf4Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring. Unit: cpu_atom ld_head.other_at_retevent=0x5,period=1000003,umask=0xc0Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases when load subsequently retires when load subsequently retires. Unit: cpu_atom ld_head.pgwalk_at_retevent=0x5,period=1000003,umask=0xa0Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk when load subsequently retires. Unit: cpu_atom ld_head.st_addr_at_retevent=0x5,period=1000003,umask=0x84Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match when load subsequently retires. Unit: cpu_atom Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation. Unit: cpu_atom Counts demand data reads that were not supplied by the L3 cache. Unit: cpu_atom event=0xb7,period=100003,umask=0x1,offcore_rsp=0x3F84400002Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Unit: cpu_atom Execution stalls while L3 cache miss demand load is outstanding. Unit: cpu_core Number of machine clears due to memory ordering conflicts. Unit: cpu_core memory_activity.cycles_l1d_missevent=0x47,cmask=2,period=1000003,umask=0x2Cycles while L1 cache miss demand load is outstanding. Unit: cpu_core memory_activity.stalls_l1d_missevent=0x47,cmask=3,period=1000003,umask=0x3Execution stalls while L1 cache miss demand load is outstanding. Unit: cpu_core memory_activity.stalls_l2_missevent=0x47,cmask=5,period=1000003,umask=0x5memory_activity.stalls_l3_missevent=0x47,cmask=9,period=1000003,umask=0x9Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles  Supports address when precise (Must be precise). Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles  Supports address when precise (Must be precise). Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles  Supports address when precise (Must be precise). Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles  Supports address when precise (Must be precise). Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles  Supports address when precise (Must be precise). Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles  Supports address when precise (Must be precise). Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles  Supports address when precise (Must be precise). Unit: cpu_core Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles  Supports address when precise (Must be precise). Unit: cpu_core mem_trans_retired.store_sampleevent=0xcd,period=1000003,umask=0x2Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility  Supports address when precise (Must be precise). Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00001Counts demand data reads that were not supplied by the L3 cache. Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00002Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Unit: cpu_core Counts demand data reads that have any type of response. Unit: cpu_atom Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Unit: cpu_atom Counts streaming stores that have any type of response. Unit: cpu_atom event=0xc1,period=100003,umask=0x1fNumber of occurrences where a microcode assist is invoked by hardware. Unit: cpu_core assists.hardwareevent=0xc1,period=100003,umask=0x4Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC). Unit: cpu_core assists.page_faultevent=0xc1,period=1000003,umask=0x8core_power.license_1core_power.license_2core_power.license_3event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10001Counts demand data reads that have any type of response. Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10002Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Unit: cpu_core event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10800Counts streaming stores that have any type of response. Unit: cpu_core xq.full_cyclesevent=0x2d,cmask=1,period=1000003,umask=0x1Counts the total number of branch instructions retired for all branch types (Precise event). Unit: cpu_atom This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL (Precise event). Unit: cpu_atom Counts the number of far branch instructions retired, includes far jump, far call and return, and Interrupt call and return (Precise event). Unit: cpu_atom Counts the number of near CALL branch instructions retired (Precise event). Unit: cpu_atom Counts the total number of mispredicted branch instructions retired for all branch types (Precise event). Unit: cpu_atom Counts the number of unhalted core clock cycles. (Fixed event). Unit: cpu_atom Counts the number of unhalted core clock cycles. Unit: cpu_atom Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event). Unit: cpu_atom Counts the number of instructions retired. (Fixed event) (Precise event). Unit: cpu_atom This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS (Precise event). Unit: cpu_atom ld_blocks.address_aliasCounts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check (Precise event). Unit: cpu_atom Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready (Precise event). Unit: cpu_atom Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU. Unit: cpu_atom machine_clears.mrn_nukeevent=0xc3,period=1000003,umask=0x80Counts the number of machines clears due to memory renaming. Unit: cpu_atom Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs (Precise event). Unit: cpu_atom machine_clears.slowevent=0xc3,period=20003,umask=0x6fCounts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP. Unit: cpu_atom Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page. Unit: cpu_atom serialization.non_c01_ms_scbevent=0x75,period=200003,umask=0x2Counts the number of issue slots not consumed due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing uops from the UROM until a specified older uop retires. Unit: cpu_atom event=0x73,period=1000003Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears. Unit: cpu_atom event=0x73,period=1000003,umask=0x3Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation. Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts. Unit: cpu_atom topdown_bad_speculation.nukeevent=0x73,period=1000003,umask=0x1Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke). Unit: cpu_atom Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls. Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions. Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops. Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops. Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls). Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls). Unit: cpu_atom Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS). Unit: cpu_atom Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS). Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized. Unit: cpu_atom Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes. Unit: cpu_atom Counts the total number of consumed retirement slots (Precise event). Unit: cpu_atom Counts the total number of uops retired (Precise event). Unit: cpu_atom Counts the number of integer divide uops retired (Precise event). Unit: cpu_atom Counts the number of uops that are from complex flows issued by the micro-sequencer (MS) (Precise event). Unit: cpu_atom Counts the number of x87 uops retired, includes those in MS flows (Precise event). Unit: cpu_atom event=0xb0,cmask=1,period=1000003,umask=0x9This event is deprecated. Refer to new event ARITH.DIV_ACTIVE. Unit: cpu_core arith.div_activeCycles when divide unit is busy executing divide or square root operations. Unit: cpu_core arith.fp_divider_activeThis event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE. Unit: cpu_core arith.int_divider_activeevent=0xb0,cmask=1,period=1000003,umask=0x8All branch instructions retired (Precise event). Unit: cpu_core Conditional branch instructions retired (Precise event). Unit: cpu_core Not taken branch instructions retired (Precise event). Unit: cpu_core Taken conditional branch instructions retired (Precise event). Unit: cpu_core Far branch instructions retired (Precise event). Unit: cpu_core Indirect near branch instructions retired (excluding returns) (Precise event). Unit: cpu_core Direct and indirect near call instructions retired (Precise event). Unit: cpu_core Return instructions retired (Precise event). Unit: cpu_core Taken branch instructions retired (Precise event). Unit: cpu_core All mispredicted branch instructions retired (Precise event). Unit: cpu_core event=0xc5,period=400009,umask=0x11Mispredicted conditional branch instructions retired (Precise event). Unit: cpu_core Mispredicted non-taken conditional branch instructions retired (Precise event). Unit: cpu_core number of branch instructions retired that were mispredicted and taken. Non PEBS (Precise event). Unit: cpu_core Mispredicted indirect CALL retired (Precise event). Unit: cpu_core Number of near branch instructions retired that were mispredicted and taken (Precise event). Unit: cpu_core This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event). Unit: cpu_core Cycle counts are evenly distributed between active threads in the Core. Unit: cpu_core Core crystal clock cycles when this thread is unhalted and the other thread is halted. Unit: cpu_core cpu_clk_unhalted.pauseevent=0xec,period=2000003,umask=0x40cpu_clk_unhalted.pause_instevent=0xec,cmask=1,edge=1,period=2000003,umask=0x40Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core. Unit: cpu_core Reference cycles when the core is not in halt state. Unit: cpu_core Core cycles when the thread is not in halt state. Unit: cpu_core Thread cycles when thread is not in halt state. Unit: cpu_core Cycles while L2 cache miss demand load is outstanding. Unit: cpu_core Cycles while memory subsystem has an outstanding load. Unit: cpu_core Execution stalls while L2 cache miss demand load is outstanding. Unit: cpu_core Total execution stalls. Unit: cpu_core Cycles total of 1 uop is executed on all ports and Reservation Station was not empty. Unit: cpu_core Cycles total of 2 uops are executed on all ports and Reservation Station was not empty. Unit: cpu_core Cycles total of 3 uops are executed on all ports and Reservation Station was not empty. Unit: cpu_core Cycles total of 4 uops are executed on all ports and Reservation Station was not empty. Unit: cpu_core Execution stalls while memory subsystem has an outstanding load. Unit: cpu_core Cycles where the Store Buffer was full and no loads caused an execution stall. Unit: cpu_core event=0x75,period=2000003,umask=0x1Instruction decoders utilized in a cycle. Unit: cpu_core Number of instructions retired. Fixed Counter - architectural event (Precise event). Unit: cpu_core Number of instructions retired. General Counter - architectural event (Precise event). Unit: cpu_core inst_retired.macro_fusedevent=0xc0,period=2000003,umask=0x10Number of all retired NOP instructions. Unit: cpu_core Precise instruction retired with PEBS precise-distribution (Precise event). Unit: cpu_core inst_retired.rep_iterationevent=0xc0,period=2000003,umask=0x8event=0xad,period=500009,umask=0x80Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path. Unit: cpu_core event=0xad,period=500009,umask=0x1Core cycles the allocator was stalled due to recovery from earlier clear event for this thread. Unit: cpu_core int_misc.unknown_branch_cyclesevent=0xad,period=1000003,umask=0x40,frontend=0x7event=0xad,period=1000003,umask=0x10TMA slots where uops got dropped. Unit: cpu_core int_vec_retired.128bitevent=0xe7,period=1000003,umask=0x13int_vec_retired.256bitevent=0xe7,period=1000003,umask=0xacint_vec_retired.add_128event=0xe7,period=1000003,umask=0x3integer ADD, SUB, SAD 128-bit vector instructions. Unit: cpu_core int_vec_retired.add_256event=0xe7,period=1000003,umask=0xcinteger ADD, SUB, SAD 256-bit vector instructions. Unit: cpu_core int_vec_retired.mul_256event=0xe7,period=1000003,umask=0x80int_vec_retired.shufflesevent=0xe7,period=1000003,umask=0x40int_vec_retired.vnni_128event=0xe7,period=1000003,umask=0x10int_vec_retired.vnni_256event=0xe7,period=1000003,umask=0x20event=0x3,period=100003,umask=0x4False dependencies in MOB due to partial compare on address. Unit: cpu_core event=0x3,period=100003,umask=0x88The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. Unit: cpu_core event=0x3,period=100003,umask=0x82Loads blocked due to overlapping with a preceding store that cannot be forwarded. Unit: cpu_core Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch. Unit: cpu_core Cycles Uops delivered by the LSD, but didn't come from the decoder. Unit: cpu_core event=0xa8,cmask=6,period=2000003,umask=0x1Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder. Unit: cpu_core Number of Uops delivered by the LSD. Unit: cpu_core Number of machine clears (nukes) of any type. Unit: cpu_core Self-modifying code (SMC) detected. Unit: cpu_core misc2_retired.lfenceevent=0xe0,period=400009,umask=0x20Increments whenever there is an update to the LBR array. Unit: cpu_core Cycles stalled due to no store buffers available. (not including draining form sync). Unit: cpu_core Counts cycles where the pipeline is stalled due to serializing operations. Unit: cpu_core TMA slots where no uops were being issued due to lack of back-end resources. Unit: cpu_core topdown.bad_spec_slotsevent=0xa4,period=10000003,umask=0x4TMA slots wasted due to incorrect speculations. Unit: cpu_core TMA slots wasted due to incorrect speculation by branch mispredictions. Unit: cpu_core topdown.memory_bound_slotsevent=0xa4,period=10000003,umask=0x10TMA slots available for an unhalted logical processor. Fixed counter - architectural event. Unit: cpu_core TMA slots available for an unhalted logical processor. General counter - architectural event. Unit: cpu_core uops_decoded.dec0_uopsevent=0x76,period=1000003,umask=0x1Uops executed on port 0. Unit: cpu_core event=0xb2,period=2000003,umask=0x2Uops executed on port 1. Unit: cpu_core uops_dispatched.port_2_3_10event=0xb2,period=2000003,umask=0x4Uops executed on ports 2, 3 and 10. Unit: cpu_core event=0xb2,period=2000003,umask=0x10Uops executed on ports 4 and 9. Unit: cpu_core uops_dispatched.port_5_11event=0xb2,period=2000003,umask=0x20Uops executed on ports 5 and 11. Unit: cpu_core event=0xb2,period=2000003,umask=0x40Uops executed on port 6. Unit: cpu_core event=0xb2,period=2000003,umask=0x80Uops executed on ports 7 and 8. Unit: cpu_core Cycles at least 1 micro-op is executed from any thread on physical core. Unit: cpu_core Cycles at least 2 micro-op is executed from any thread on physical core. Unit: cpu_core Cycles at least 3 micro-op is executed from any thread on physical core. Unit: cpu_core Cycles at least 4 micro-op is executed from any thread on physical core. Unit: cpu_core Cycles where at least 1 uop was executed per-thread. Unit: cpu_core Cycles where at least 2 uops were executed per-thread. Unit: cpu_core Cycles where at least 3 uops were executed per-thread. Unit: cpu_core Cycles where at least 4 uops were executed per-thread. Unit: cpu_core uops_executed.stallsCounts number of cycles no uops were dispatched to be executed on this thread. Unit: cpu_core This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS. Unit: cpu_core Counts the number of uops to be executed per-thread each cycle. Unit: cpu_core Counts the number of x87 uops dispatched. Unit: cpu_core event=0xae,period=2000003,umask=0x1Uops that RAT issues to RS. Unit: cpu_core uops_retired.cyclesevent=0xc2,cmask=1,period=1000003,umask=0x2Cycles with retired uop(s). Unit: cpu_core uops_retired.heavyevent=0xc2,period=2000003,umask=0x4,frontend=0x8Retirement slots used. Unit: cpu_core Cycles without actually retired uops. Unit: cpu_core This event is deprecated. Refer to new event UOPS_RETIRED.STALLS. Unit: cpu_core Number of clocks. Unit: uncore_imc unc_m_vc0_requests_rdIncoming VC0 read request. Unit: uncore_imc unc_m_vc0_requests_wrevent=0x3Incoming VC0 write request. Unit: uncore_imc unc_m_vc1_requests_rdIncoming VC1 read request. Unit: uncore_imc unc_m_vc1_requests_wrIncoming VC1 write request. Unit: uncore_imc unc_m_prefetch_rdIncoming read prefetch request from IA. Unit: uncore_imc unc_m_dram_thermal_hotAny Rank at Hot state. Unit: uncore_imc unc_m_dram_thermal_warmevent=0x1aAny Rank at Warm state. Unit: uncore_imc unc_m_dram_page_hit_rdevent=0x1cincoming read request page status is Page Hit. Unit: uncore_imc unc_m_dram_page_empty_rdevent=0x1dincoming read request page status is Page Empty. Unit: uncore_imc unc_m_dram_page_miss_rdevent=0x1eincoming read request page status is Page Miss. Unit: uncore_imc unc_m_dram_page_hit_wrevent=0x1fincoming write request page status is Page Hit. Unit: uncore_imc unc_m_dram_page_empty_wrincoming write request page status is Page Empty. Unit: uncore_imc unc_m_dram_page_miss_wrincoming write request page status is Page Miss. Unit: uncore_imc unc_m_cas_count_rdevent=0x22Read CAS command sent to DRAM. Unit: uncore_imc unc_m_cas_count_wrWrite CAS command sent to DRAM. Unit: uncore_imc unc_m_act_count_rdACT command for a read request sent to DRAM. Unit: uncore_imc unc_m_act_count_wrACT command for a write request sent to DRAM. Unit: uncore_imc unc_m_act_count_totalACT command sent to DRAM. Unit: uncore_imc unc_m_pre_count_page_missPRE command sent to DRAM for a read/write request. Unit: uncore_imc unc_m_pre_count_idlePRE command sent to DRAM due to page table idle timer expiration. Unit: uncore_imc unc_mc0_rdcas_count_freerunCounts every 64B read  request entering the Memory Controller 0 to DRAM (sum of all channels). Unit: uncore_imc unc_mc1_rdcas_count_freerunCounts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels). Unit: uncore_imc unc_mc0_wrcas_count_freerunCounts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM. Unit: uncore_imc unc_mc1_wrcas_count_freerunCounts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM. Unit: uncore_imc This 48-bit fixed counter counts the UCLK cycles. Unit: uncore_clock uncore_clockEach cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. Unit: uncore_arb Counts the number of page walks completed due to load DTLB misses to any page size. Unit: cpu_atom event=0x49,period=2000003,umask=0xeCounts the number of page walks completed due to store DTLB misses to any page size. Unit: cpu_atom ld_head.dtlb_miss_at_retevent=0x5,period=1000003,umask=0x90Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss when load subsequently retires. Unit: cpu_atom event=0x12,period=100003,umask=0x20Loads that miss the DTLB and hit the STLB. Unit: cpu_core event=0x12,cmask=1,period=100003,umask=0x10Cycles when at least one PMH is busy with a page walk for a demand load. Unit: cpu_core event=0x12,period=100003,umask=0xeLoad miss in all TLB levels causes a page walk that completes. (All page sizes). Unit: cpu_core event=0x12,period=100003,umask=0x8Page walks completed due to a demand data load to a 1G page. Unit: cpu_core event=0x12,period=100003,umask=0x4Page walks completed due to a demand data load to a 2M/4M page. Unit: cpu_core event=0x12,period=100003,umask=0x2Page walks completed due to a demand data load to a 4K page. Unit: cpu_core event=0x12,period=100003,umask=0x10Number of page walks outstanding for a demand load in the PMH each cycle. Unit: cpu_core event=0x13,period=100003,umask=0x20Stores that miss the DTLB and hit the STLB. Unit: cpu_core event=0x13,cmask=1,period=100003,umask=0x10Cycles when at least one PMH is busy with a page walk for a store. Unit: cpu_core event=0x13,period=100003,umask=0xeStore misses in all TLB levels causes a page walk that completes. (All page sizes). Unit: cpu_core event=0x13,period=100003,umask=0x8Page walks completed due to a demand data store to a 1G page. Unit: cpu_core event=0x13,period=100003,umask=0x4Page walks completed due to a demand data store to a 2M/4M page. Unit: cpu_core event=0x13,period=100003,umask=0x2Page walks completed due to a demand data store to a 4K page. Unit: cpu_core event=0x13,period=100003,umask=0x10Number of page walks outstanding for a store in the PMH each cycle. Unit: cpu_core event=0x11,period=100003,umask=0x20Instruction fetch requests that miss the ITLB and hit the STLB. Unit: cpu_core event=0x11,cmask=1,period=100003,umask=0x10Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. Unit: cpu_core event=0x11,period=100003,umask=0xeCode miss in all TLB levels causes a page walk that completes. (All page sizes). Unit: cpu_core event=0x11,period=100003,umask=0x4Code miss in all TLB levels causes a page walk that completes. (2M/4M). Unit: cpu_core event=0x11,period=100003,umask=0x2Code miss in all TLB levels causes a page walk that completes. (4K). Unit: cpu_core event=0x11,period=100003,umask=0x10Number of page walks outstanding for an outstanding code request in the PMH each cycle. Unit: cpu_core This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLSevent=0x26,period=200003,umask=0x2L2_LINES_OUT.NON_SILENTevent=0x26,period=200003,umask=0x1All L2 requests.[This event is alias to L2_RQSTS.REFERENCES]Counts all L2 requests.[This event is alias to L2_RQSTS.REFERENCES]Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.MISS]Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.MISS]All L2 requests.[This event is alias to L2_REQUEST.ALL]Counts all L2 requests.[This event is alias to L2_REQUEST.ALL]LONGEST_LAT_CACHE.MISSCompleted demand load uops that miss the L1 d-cacheNumber of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)Retired load instructions which data sources missed L3 but serviced from local dram  Supports address when preciseRetired load instructions which data sources missed L3 but serviced from local DRAM  Supports address when preciseevent=0xd3,period=1000003,umask=0x2MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM  Supports address when preciseevent=0xd3,period=1000003,umask=0x4MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM  Supports address when preciseRetired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all cachesCounts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3event=0xd1,period=1000003,umask=0x80Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches  Supports address when preciseCounts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3  Supports address when preciseMEM_STORE_RETIRED.L2_HITRetired memory uops for any accessNumber of retired micro-operations (uops) for load or store memory accessesevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F803C0004event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C0004event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008000004event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808000004event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F803C0001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x4003C0001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1030000001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x830000001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008000001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808000001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F803C0002event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008000002event=0x2a,period=100003,umask=0x1,offcore_rsp=0x808000002event=0x2a,period=100003,umask=0x1,offcore_rsp=0x80082380event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F003C4477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socketevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x10003C4477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the dataevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x4003C4477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the dataevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x8003C4477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x1830004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified)event=0x2a,period=100003,umask=0x1,offcore_rsp=0x1030004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the dataevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x830004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x1008004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x808004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x80080800OFFCORE_REQUESTS.ALL_REQUESTSThis event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RDOFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RDOFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFOOFFCORE_REQUESTS_OUTSTANDING.DATA_RDARITH.FPDIV_ACTIVEASSISTS.SSE_AVX_MIXFP_ARITH_DISPATCHED.PORT_0FP_ARITH_DISPATCHED.PORT_1FP_ARITH_DISPATCHED.PORT_5fp_arith_inst_retired2.128b_packed_halfevent=0xcf,period=100003,umask=0x4FP_ARITH_INST_RETIRED2.128B_PACKED_HALFfp_arith_inst_retired2.256b_packed_halfevent=0xcf,period=100003,umask=0x8FP_ARITH_INST_RETIRED2.256B_PACKED_HALFfp_arith_inst_retired2.512b_packed_halfevent=0xcf,period=100003,umask=0x10FP_ARITH_INST_RETIRED2.512B_PACKED_HALFfp_arith_inst_retired2.complex_scalar_halfevent=0xcf,period=100003,umask=0x2FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALFfp_arith_inst_retired2.scalarevent=0xcf,period=100003,umask=0x3Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complexFP_ARITH_INST_RETIRED2.SCALARfp_arith_inst_retired2.scalar_halfevent=0xcf,period=100003,umask=0x1FP_ARITH_INST_RETIRED2.SCALAR_HALFfp_arith_inst_retired2.vectorevent=0xcf,period=100003,umask=0x1cNumber of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retiredFP_ARITH_INST_RETIRED2.VECTORfrontend_retired.ms_flowsevent=0xc6,period=100007,umask=0x1,frontend=0x8FRONTEND_RETIRED.MS_FLOWS (Precise event)FRONTEND_RETIRED.UNKNOWN_BRANCH (Precise event)Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularityCounts the total number of uops delivered by the Microcode Sequencer (MS)MEMORY_ACTIVITY.STALLS_L2_MISSMEMORY_ACTIVITY.STALLS_L3_MISSRetired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility  Supports address when precise (Must be precise)event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3FBFC00004event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FC00002event=0x2a,period=100003,umask=0x1,offcore_rsp=0x94002380event=0x2a,period=100003,umask=0x1,offcore_rsp=0x84002380event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FC04477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 cachesevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x70CC04477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.  It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAMevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x94000800event=0x2a,period=100003,umask=0x1,offcore_rsp=0x84000800ASSISTS.PAGE_FAULTexe.amx_busyevent=0xb7,period=2000003,umask=0x2Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operationevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x10004event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C000004event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104000004event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708000004event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C000001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104000001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x730000001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x703000001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708000001event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FFC0002event=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C000002event=0x2a,period=100003,umask=0x1,offcore_rsp=0x104000002event=0x2a,period=100003,umask=0x1,offcore_rsp=0x708000002event=0x2a,period=100003,umask=0x1,offcore_rsp=0x10070Counts hardware prefetches (which bring data to L2) that have any type of responseevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x12380event=0x2a,period=100003,umask=0x1,offcore_rsp=0x90002380event=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F3FFC4477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of responseevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x73C004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAMevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x104004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Clusterevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x70C004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Clusterevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x700C04477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode.  In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Clusterevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x3F33004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socketevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x730004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socketocr.reads_to_core.remote_memoryevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x733004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socketevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x703004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socketevent=0x2a,period=100003,umask=0x1,offcore_rsp=0x708004477Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeocr.write_estimate.memoryevent=0x2a,period=100003,umask=0x1,offcore_rsp=0xFBFF80822Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)rs_empty.cyclesevent=0xa5,period=1000003,umask=0x7Counts cycles during which the reservation station (RS) is empty for this logical processorXQ.FULL_CYCLESamx_ops_retired.bf16event=0xce,period=1000003,umask=0x2AMX_OPS_RETIRED.BF16amx_ops_retired.int8event=0xce,period=1000003,umask=0x1AMX_OPS_RETIRED.INT8This event is deprecated. Refer to new event ARITH.DIV_ACTIVEThis event is deprecated. Refer to new event ARITH.FPDIV_ACTIVEarith.idiv_activeevent=0xb0,period=1000003,umask=0x8This event counts the cycles the integer divider is busyARITH.IDIV_ACTIVEThis event is deprecated. Refer to new event ARITH.IDIV_ACTIVEevent=0xc5,period=100003,umask=0x80Miss-predicted near indirect branch instructions retired (excluding returns) (Precise event)Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch (Precise event)Mispredicted indirect CALL retired (Precise event)This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired (Precise event)cpu_clk_unhalted.c01event=0xec,period=2000003,umask=0x10Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized stateCounts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructionscpu_clk_unhalted.c02event=0xec,period=2000003,umask=0x20Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized stateCounts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.  This state can be entered via the TPAUSE or UMWAIT instructionscpu_clk_unhalted.c0_waitevent=0xec,period=2000003,umask=0x70Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI stateCounts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instructionCPU_CLK_UNHALTED.PAUSECPU_CLK_UNHALTED.PAUSE_INSTCounts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this caseCycles no uop executed while RS was not empty, the SB was not full and there was no outstanding loadNumber of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding loadINST_RETIRED.MACRO_FUSEDNumber of all retired NOP instructionsPrecise instruction retired with PEBS precise-distribution (Precise event)A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0 (Precise event)INST_RETIRED.REP_ITERATIONint_misc.mba_stallsevent=0xad,period=1000003,umask=0x20INT_MISC.MBA_STALLSINT_MISC.UNKNOWN_BRANCH_CYCLESINT_VEC_RETIRED.128BITINT_VEC_RETIRED.256BITinteger ADD, SUB, SAD 128-bit vector instructionsNumber of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructionsinteger ADD, SUB, SAD 256-bit vector instructionsNumber of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructionsINT_VEC_RETIRED.MUL_256INT_VEC_RETIRED.SHUFFLESINT_VEC_RETIRED.VNNI_128INT_VEC_RETIRED.VNNI_256MISC2_RETIRED.LFENCENumber of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resourcesTMA slots wasted due to incorrect speculationsNumber of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculationsNumber of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of specualtive operations that were issued but not retired as well as the out-of-order engine recovery past a branch mispredictionTOPDOWN.MEMORY_BOUND_SLOTSUOPS_DECODED.DEC0_UOPSNumber of uops dispatch to execution  port 0Number of uops dispatch to execution  port 1Uops executed on ports 2, 3 and 10Number of uops dispatch to execution ports 2, 3 and 10Uops executed on ports 4 and 9Number of uops dispatch to execution ports 4 and 9Uops executed on ports 5 and 11Number of uops dispatch to execution ports 5 and 11Uops executed on port 6Number of uops dispatch to execution  port 6Uops executed on ports 7 and 8Number of uops dispatch to execution  ports 7 and 8This event is deprecated. Refer to new event UOPS_EXECUTED.STALLSCycles with retired uop(s)Counts cycles where at least one uop has retiredUOPS_RETIRED.HEAVYUOPS_RETIRED.MSThis event is deprecated. Refer to new event UOPS_RETIRED.STALLSevent=0x1,umask=0x0000000001IMC Clockticks at DCLK frequency. Unit: uncore_imc IMC Clockticks at HCLK frequency. Unit: uncore_imc event=0x5,umask=0x00000000c1All DRAM read CAS commands issued (does not include underfills). Unit: uncore_imc event=0x5,umask=0x00000000c4DRAM underfill read CAS commands issued. Unit: uncore_imc event=0x5,umask=0x00000000cfevent=0x5,umask=0x00000000f0event=0x10,umask=0x0000000001event=0x10,umask=0x0000000002event=0x20,umask=0x0000000001event=0x20,umask=0x0000000002unc_m_pmm_rpq_occupancy.all_sch0event=0xe0,umask=0x0000000001PMM Read Pending Queue occupancy. Unit: uncore_imc unc_m_pmm_rpq_occupancy.all_sch1event=0xe0,umask=0x0000000002PMM Read Pending Queue inserts. Unit: uncore_imc event=0xe4,umask=0x03PMM Write Pending Queue inserts. Unit: uncore_imc unc_m_pmm_wpq_occupancy.all_sch0event=0xe4,umask=0x0000000001unc_m_pmm_wpq_occupancy.all_sch1event=0xe4,umask=0x0000000002event=0x2,umask=0x00000000ffActivate due to read, write, underfill, or bypass. Unit: uncore_imc event=0x3,umask=0x0000000011Precharge due to read on page miss. Unit: uncore_imc event=0x3,umask=0x0000000022Precharge due to write on page miss. Unit: uncore_imc event=0x3,umask=0x0000000088DRAM Precharge commands. : Precharge due to (?). Unit: uncore_imc event=0x3,umask=0x00000000ffPrecharge due to read, write, underfill, or PGT. Unit: uncore_imc event=0x5,umask=0x00000000ffunc_m_cas_count.rd_pre_regevent=0x5,umask=0x00000000c2DRAM RD_CAS and WR_CAS Commands. Unit: uncore_imc unc_m_cas_count.rd_pre_underfillevent=0x5,umask=0x00000000c8unc_m_cas_count.wr_preevent=0x5,umask=0x00000000e0unc_m_pmm_rpq_occupancy.no_gnt_sch0event=0xe0,umask=0x0000000004unc_m_pmm_rpq_occupancy.no_gnt_sch1event=0xe0,umask=0x0000000008unc_m_pre_count.rd_pch0event=0x3,umask=0x0000000001unc_m_pre_count.wr_pch0event=0x3,umask=0x0000000002unc_m_pre_count.ufill_pch0event=0x3,umask=0x0000000004unc_m_pre_count.pgt_pch0event=0x3,umask=0x0000000008DRAM Precharge commands. : Prechages from Page Table. Unit: uncore_imc unc_m_pre_count.rd_pch1event=0x3,umask=0x0000000010unc_m_pre_count.wr_pch1event=0x3,umask=0x0000000020unc_m_pre_count.ufill_pch1event=0x3,umask=0x0000000040unc_m_pre_count.pgt_pch1event=0x3,umask=0x0000000080unc_m_pre_count.ufillevent=0x3,umask=0x0000000044unc_m_cas_count.wr_nonpreevent=0x5,umask=0x00000000D0DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre. Unit: uncore_imc unc_m_cas_count.pch0event=0x5,umask=0x0000000040DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0. Unit: uncore_imc unc_m_cas_count.pch1event=0x5,umask=0x0000000080DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1. Unit: uncore_imc unc_m_pmm_rpq_occupancy.gnt_wait_sch0event=0xe0,umask=0x0000000010unc_m_pmm_rpq_occupancy.gnt_wait_sch1event=0xe0,umask=0x0000000020UPI Clockticks. Unit: uncore_upi event=0x2,umask=0x000000000fIRP Clockticks. Unit: uncore_irp M2P Clockticks. Unit: uncore_m2pcie event=0x1,ch_mask=0x0000IIO Clockticks. Unit: uncore_iio event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000001Write request of 4 bytes made by IIO Part0 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000001Write request of 4 bytes made by IIO Part1 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000001Write request of 4 bytes made by IIO Part2 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000001Write request of 4 bytes made by IIO Part3 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000002event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000002event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000002event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000002event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000001Data requested of the CPU : Card writing to DRAM. Unit: uncore_iio event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000001event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000001event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000001unc_iio_data_req_of_cpu.peer_write.part4event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000002Data requested of the CPU : Card writing to another Card (same or different stack). Unit: uncore_iio unc_iio_data_req_of_cpu.peer_write.part5event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000002unc_iio_data_req_of_cpu.peer_write.part6event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000002unc_iio_data_req_of_cpu.peer_write.part7event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000002event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000002Number Transactions requested of the CPU : Card writing to another Card (same or different stack). Unit: uncore_iio event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000002event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000002event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000002unc_iio_txn_req_of_cpu.peer_write.part4event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000002unc_iio_txn_req_of_cpu.peer_write.part5event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000002unc_iio_txn_req_of_cpu.peer_write.part6event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000002unc_iio_txn_req_of_cpu.peer_write.part7event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000002M2M Clockticks. Unit: uncore_m2m M3UPI Clockticks. Unit: uncore_m3upi event=0x50,umask=0x0000000001Read requests from a unit on this socket. Unit: uncore_cha event=0x50,umask=0x0000000002Read requests from a remote socket. Unit: uncore_cha event=0x50,umask=0x0000000004Write Requests from a unit on this socket. Unit: uncore_cha event=0x50,umask=0x0000000008Read and Write Requests; Writes Remote. Unit: uncore_cha unc_cha_requests.invitoeevent=0x50,umask=0x0000000030Requests for exclusive ownership of a cache line without receiving data. Unit: uncore_cha CHA Clockticks. Unit: uncore_cha event=0x35,umask=0x00c80ffe01TOR Inserts for CRd misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c817fe01TOR Inserts for DRd misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c897fe01TOR Inserts for DRd Pref misses from local IA. Unit: uncore_cha event=0x35,umask=0x00cc43ff04TOR Inserts for ItoM from local IO. Unit: uncore_cha event=0x35,umask=0x00c816fe01TOR Inserts for DRd misses from local IA targeting local memory. Unit: uncore_cha event=0x35,umask=0x00c8177e01TOR Inserts for DRd misses from local IA targeting remote memory. Unit: uncore_cha event=0x35,umask=0x00C896FE01TOR Inserts for DRd Pref misses from local IA targeting local memory. Unit: uncore_cha event=0x35,umask=0x00C8977E01TOR Inserts for DRd Pref misses from local IA targeting remote memory. Unit: uncore_cha event=0x36,umask=0x00c817fe01TOR Occupancy for DRd misses from local IA. Unit: uncore_cha event=0x36,umask=0x00c816fe01TOR Occupancy for DRd misses from local IA targeting local memory. Unit: uncore_cha event=0x36,umask=0x00c8177e01TOR Occupancy for DRd misses from local IA targeting remote memory. Unit: uncore_cha event=0x35,umask=0x00c8178a01TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha event=0x35,umask=0x00c8178601TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha event=0x36,umask=0x00c8178601TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha event=0x36,umask=0x00c8178a01TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha event=0x35,umask=0x00c8f3ff04TOR Inserts for RdCur from local IO. Unit: uncore_cha event=0x35,umask=0x00cd43ff04TOR Inserts for ItoMCacheNears from IO devices. Unit: uncore_cha unc_upi_txl_flits.slot0event=0x2,umask=0x0000000001Valid Flits Sent : Slot 0. Unit: uncore_upi unc_upi_txl_flits.slot1event=0x2,umask=0x0000000002Valid Flits Sent : Slot 1. Unit: uncore_upi unc_upi_txl_flits.slot2event=0x2,umask=0x0000000004Valid Flits Sent : Slot 2. Unit: uncore_upi event=0x2,umask=0x0000000008Valid Flits Sent : Data. Unit: uncore_upi unc_upi_txl_flits.llcrdevent=0x2,umask=0x0000000010Valid Flits Sent : LLCRD Not Empty. Unit: uncore_upi unc_upi_txl_flits.nullevent=0x2,umask=0x0000000020Valid Flits Sent : Slot NULL or LLCRD Empty. Unit: uncore_upi unc_upi_txl_flits.llctrlevent=0x2,umask=0x0000000040Valid Flits Sent : LLCTRL. Unit: uncore_upi unc_upi_txl_flits.prothdrevent=0x2,umask=0x0000000080Valid Flits Sent : Protocol Header. Unit: uncore_upi event=0x2,umask=0x0000000097event=0x2,umask=0x0000000047Valid Flits Sent : Idle. Unit: uncore_upi event=0x2,umask=0x0000000027All Null Flits. Unit: uncore_upi unc_upi_rxl_flits.slot0Valid Flits Received : Slot 0. Unit: uncore_upi unc_upi_rxl_flits.slot1Valid Flits Received : Slot 1. Unit: uncore_upi unc_upi_rxl_flits.slot2Valid Flits Received : Slot 2. Unit: uncore_upi unc_upi_rxl_flits.dataValid Flits Received : Data. Unit: uncore_upi unc_upi_rxl_flits.llcrdValid Flits Received : LLCRD Not Empty. Unit: uncore_upi unc_upi_rxl_flits.nullValid Flits Received : Slot NULL or LLCRD Empty. Unit: uncore_upi unc_upi_rxl_flits.llctrlValid Flits Received : LLCTRL. Unit: uncore_upi unc_upi_rxl_flits.prothdrValid Flits Received : Protocol Header. Unit: uncore_upi event=0x3,umask=0x000000000fevent=0x3,umask=0x0000000097unc_upi_rxl_flits.idleevent=0x3,umask=0x0000000047Valid Flits Received : Idle. Unit: uncore_upi event=0x3,umask=0x0000000027unc_upi_txl_basic_hdr_match.ncbevent=0x4,umask=0x000000000eMatches on Transmit path of a UPI Port : Non-Coherent Bypass. Unit: uncore_upi unc_upi_txl_basic_hdr_match.ncb_opcevent=0x4,umask=0x000000010eMatches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode. Unit: uncore_upi unc_upi_txl_basic_hdr_match.ncsevent=0x4,umask=0x000000000fMatches on Transmit path of a UPI Port : Non-Coherent Standard. Unit: uncore_upi unc_upi_txl_basic_hdr_match.ncs_opcevent=0x4,umask=0x000000010fMatches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode. Unit: uncore_upi unc_upi_rxl_basic_hdr_match.ncbevent=0x5,umask=0x000000000eMatches on Receive path of a UPI Port : Non-Coherent Bypass. Unit: uncore_upi unc_upi_rxl_basic_hdr_match.ncb_opcevent=0x5,umask=0x000000010eMatches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode. Unit: uncore_upi unc_upi_rxl_basic_hdr_match.ncsevent=0x5,umask=0x000000000fMatches on Receive path of a UPI Port : Non-Coherent Standard. Unit: uncore_upi unc_upi_rxl_basic_hdr_match.ncs_opcevent=0x5,umask=0x000000010fMatches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode. Unit: uncore_upi event=0x12,umask=0x0000000001Direct packet attempts : D2C. Unit: uncore_upi unc_upi_rxl_inserts.slot0event=0x30,umask=0x0000000001RxQ Flit Buffer Allocations : Slot 0. Unit: uncore_upi unc_upi_rxl_inserts.slot1event=0x30,umask=0x0000000002RxQ Flit Buffer Allocations : Slot 1. Unit: uncore_upi unc_upi_rxl_inserts.slot2event=0x30,umask=0x0000000004RxQ Flit Buffer Allocations : Slot 2. Unit: uncore_upi event=0x31,umask=0x0000000001RxQ Flit Buffer Bypassed : Slot 0. Unit: uncore_upi event=0x31,umask=0x0000000002RxQ Flit Buffer Bypassed : Slot 1. Unit: uncore_upi event=0x31,umask=0x0000000004RxQ Flit Buffer Bypassed : Slot 2. Unit: uncore_upi unc_upi_rxl_occupancy.slot0event=0x32,umask=0x0000000001RxQ Occupancy - All Packets : Slot 0. Unit: uncore_upi unc_upi_rxl_occupancy.slot1event=0x32,umask=0x0000000002RxQ Occupancy - All Packets : Slot 1. Unit: uncore_upi unc_upi_rxl_occupancy.slot2event=0x32,umask=0x0000000004RxQ Occupancy - All Packets : Slot 2. Unit: uncore_upi unc_upi_txl_insertsevent=0x40Tx Flit Buffer Allocations. Unit: uncore_upi Tx Flit Buffer Bypassed. Unit: uncore_upi unc_upi_txl_occupancyevent=0x42Tx Flit Buffer Occupancy. Unit: uncore_upi FAF - request insert from TC. Unit: uncore_irp FAF occupancy. Unit: uncore_irp event=0x11,umask=0x0000000008event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000004Read request for 4 bytes made by IIO Part0 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000004Read request for 4 bytes made by IIO Part1 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000004Read request for 4 bytes made by IIO Part2 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000004Read request for 4 bytes made by IIO Part3 to Memory. Unit: uncore_iio event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000004Data requested of the CPU : Card reading from DRAM. Unit: uncore_iio event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000004event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000004event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000004event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000001event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000001event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000001event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000001event=0x84,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000004event=0x84,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000004event=0x84,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000004event=0x84,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000004event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000001event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000001event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000001event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000001event=0x84,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000004event=0x84,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000004event=0x84,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000004event=0x84,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000004event=0xc0,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000001event=0xc0,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000001event=0xc0,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000001event=0xc0,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000001event=0xc0,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000001Data requested by the CPU : Core writing to Cards MMIO space. Unit: uncore_iio event=0xc0,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000001event=0xc0,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000001event=0xc0,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000001event=0xc1,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000001event=0xc1,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000001event=0xc1,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000001event=0xc1,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000001event=0xc1,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000004event=0xc1,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000004event=0xc1,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000004event=0xc1,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000004event=0xc1,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000001Number Transactions requested by the CPU : Core writing to Cards MMIO space. Unit: uncore_iio event=0xc1,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000001event=0xc1,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000001event=0xc1,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000001event=0xc1,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000004Number Transactions requested by the CPU : Core reading from Cards MMIO space. Unit: uncore_iio event=0xc1,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000004event=0xc1,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000004event=0xc1,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000004event=0x83,ch_mask=0x0001,fc_mask=0x07,umask=0x0000000080event=0x83,ch_mask=0x0002,fc_mask=0x07,umask=0x0000000080event=0x83,ch_mask=0x0004,fc_mask=0x07,umask=0x0000000080event=0x83,ch_mask=0x0008,fc_mask=0x07,umask=0x0000000080event=0x83,ch_mask=0x0010,fc_mask=0x07,umask=0x0000000080event=0x83,ch_mask=0x0020,fc_mask=0x07,umask=0x0000000080event=0x83,ch_mask=0x0040,fc_mask=0x07,umask=0x0000000080event=0x83,ch_mask=0x0080,fc_mask=0x07,umask=0x0000000080event=0xc2,ch_mask=0x01,fc_mask=0x07,umask=0x0000000004event=0xc2,ch_mask=0x02,fc_mask=0x07,umask=0x0000000004event=0xc2,ch_mask=0x04,fc_mask=0x07,umask=0x0000000004event=0xc2,ch_mask=0x08,fc_mask=0x07,umask=0x0000000004event=0xc2,ch_mask=0x10,fc_mask=0x07,umask=0x0000000004event=0xc2,ch_mask=0x20,fc_mask=0x07,umask=0x0000000004event=0xc2,ch_mask=0x40,fc_mask=0x07,umask=0x0000000004event=0xc2,ch_mask=0x80,fc_mask=0x07,umask=0x0000000004event=0xd5,fc_mask=0x04,umask=0x00000000ffUNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS. Unit: uncore_iio AD Ingress (from CMS) : AD Ingress (from CMS) Allocations. Unit: uncore_m2m event=0x16,umask=0x07event=0x17,umask=0x07event=0x18,umask=0x03event=0x19,umask=0x07event=0x1a,umask=0x07event=0x1b,umask=0x07event=0x1c,umask=0x03event=0x20,umask=0x08event=0x20,umask=0x04event=0x21,umask=0x0320event=0x21,umask=0x0340event=0x21,umask=0x0301event=0x21,umask=0x0304event=0x21,umask=0x0302event=0x21,umask=0x0310event=0x21,umask=0x0308unc_m2m_tracker_inserts.ch0event=0x32,umask=0x0000000104Tracker Inserts : Channel 0. Unit: uncore_m2m unc_m2m_tracker_inserts.ch1event=0x32,umask=0x0000000204Tracker Inserts : Channel 1. Unit: uncore_m2m unc_m2m_tracker_occupancy.ch0event=0x33,umask=0x0000000001Tracker Occupancy : Channel 0. Unit: uncore_m2m unc_m2m_tracker_occupancy.ch1event=0x33,umask=0x0000000002Tracker Occupancy : Channel 1. Unit: uncore_m2m unc_m2m_prefcam_demand_drops.ch0_xptevent=0x58,umask=0x0000000001Data Prefetches Dropped. Unit: uncore_m2m unc_m2m_prefcam_demand_drops.ch0_upievent=0x58,umask=0x0000000002unc_m2m_prefcam_demand_drops.ch1_xptevent=0x58,umask=0x0000000004unc_m2m_prefcam_demand_drops.ch1_upievent=0x58,umask=0x0000000008unc_m2m_prefcam_inserts.upi_allchevent=0x56,umask=0x000000000aPrefetch CAM Inserts : UPI - All Channels. Unit: uncore_m2m unc_m2m_prefcam_inserts.xpt_allchevent=0x56,umask=0x0000000005Prefetch CAM Inserts : XPT - All Channels. Unit: uncore_m2m unc_m2m_prefcam_demand_drops.xpt_allchevent=0x58,umask=0x0000000005unc_m2m_prefcam_demand_merge.upi_allchevent=0x5d,umask=0x000000000a: UPI - All Channels. Unit: uncore_m2m unc_m2m_prefcam_demand_merge.xpt_allchevent=0x5d,umask=0x0000000005: XPT - All Channels. Unit: uncore_m2m FlowQ Generated Prefetch. Unit: uncore_m3upi unc_m3upi_d2u_sentevent=0x2aD2U Sent. Unit: uncore_m3upi unc_m3upi_d2c_sentevent=0x2bD2C Sent. Unit: uncore_m3upi unc_m3upi_cms_clockticksM3UPI CMS Clockticks. Unit: uncore_m3upi event=0x50,umask=0x0000000010event=0x50,umask=0x0000000003Read requests made into the CHA. Unit: uncore_cha event=0x50,umask=0x000000000cWrite requests made into the CHA. Unit: uncore_cha event=0x53,umask=0x0000000002event=0x53,umask=0x0000000001event=0x54,umask=0x0000000001event=0x54,umask=0x0000000002unc_cha_osb.local_invitoeevent=0x55,umask=0x0000000001OSB Snoop Broadcast : Local InvItoE. Unit: uncore_cha unc_cha_osb.local_readevent=0x55,umask=0x0000000002OSB Snoop Broadcast : Local Rd. Unit: uncore_cha unc_cha_llc_lookup.data_rdevent=0x34,umask=0x00001bc1ffunc_cha_llc_lookup.remote_snpevent=0x34,umask=0x00001c19ffCache and Snoop Filter Lookups; Snoop Requests from a Remote Socket. Unit: uncore_cha unc_cha_tor_inserts.snps_from_remevent=0x35,umask=0x00c001ff08TOR Inserts; All Snoops from Remote. Unit: uncore_cha unc_cha_tor_inserts.allevent=0x35,umask=0x00C001FFffTOR Inserts : All. Unit: uncore_cha event=0x35,umask=0x00c001ff01TOR Inserts; All from Local IA. Unit: uncore_cha event=0x35,umask=0x00c001fd01TOR Inserts; Hits from Local IA. Unit: uncore_cha event=0x35,umask=0x00c80ffd01TOR Inserts; CRd hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c817fd01TOR Inserts; DRd hits from local IA. Unit: uncore_cha event=0x35,umask=0x00ccc7fd01TOR Inserts; LLCPrefRFO hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c807fd01TOR Inserts; RFO hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c001fe01TOR Inserts; misses from Local IA. Unit: uncore_cha event=0x35,umask=0x00ccc7fe01TOR Inserts; LLCPrefRFO misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c807fe01TOR Inserts; RFO misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c001ff04TOR Inserts; All from local IO. Unit: uncore_cha event=0x35,umask=0x00c001fd04TOR Inserts; Hits from local IO. Unit: uncore_cha event=0x35,umask=0x00c001fe04TOR Inserts; Misses from local IO. Unit: uncore_cha event=0x35,umask=0x00cc43fe04TOR Inserts; ItoM misses from local IO. Unit: uncore_cha unc_cha_tor_inserts.io_miss_rfoevent=0x35,umask=0x00c803fe04TOR Inserts; RFO misses from local IO. Unit: uncore_cha unc_cha_tor_inserts.irq_iaevent=0x35,umask=0x0000000001TOR Inserts : IRQ - iA. Unit: uncore_cha unc_cha_tor_inserts.evictevent=0x35,umask=0x0000000002TOR Inserts : SF/LLC Evictions. Unit: uncore_cha unc_cha_tor_inserts.prq_iosfevent=0x35,umask=0x0000000004TOR Inserts : PRQ - IOSF. Unit: uncore_cha unc_cha_tor_inserts.ipqevent=0x35,umask=0x0000000008TOR Inserts : IPQ. Unit: uncore_cha unc_cha_tor_inserts.irq_non_iaevent=0x35,umask=0x0000000010TOR Inserts : IRQ - Non iA. Unit: uncore_cha unc_cha_tor_inserts.prq_non_iosfevent=0x35,umask=0x0000000020TOR Inserts : PRQ - Non IOSF. Unit: uncore_cha unc_cha_tor_inserts.rrqevent=0x35,umask=0x0000000040TOR Inserts : RRQ. Unit: uncore_cha unc_cha_tor_inserts.wbqevent=0x35,umask=0x0000000080TOR Inserts : WBQ. Unit: uncore_cha unc_cha_tor_inserts.loc_ioevent=0x35,umask=0x00C000FF04TOR Inserts : All from Local IO. Unit: uncore_cha unc_cha_tor_inserts.loc_iaevent=0x35,umask=0x00c000ff01TOR Inserts : All from Local iA. Unit: uncore_cha unc_cha_tor_inserts.loc_allevent=0x35,umask=0x00C000FF05TOR Inserts : All from Local iA and IO. Unit: uncore_cha unc_cha_tor_inserts.rem_snpsevent=0x35,umask=0x00C001FF08TOR Inserts : All Snoops from Remote. Unit: uncore_cha unc_cha_tor_inserts.rem_allevent=0x35,umask=0x00C001FFC8TOR Inserts : All from Remote. Unit: uncore_cha unc_cha_tor_inserts.hitevent=0x35TOR Inserts : Just Hits. Unit: uncore_cha unc_cha_tor_inserts.missTOR Inserts : Just Misses. Unit: uncore_cha unc_cha_tor_inserts.mmcfgTOR Inserts : MMCFG Access. Unit: uncore_cha unc_cha_tor_inserts.mmioTOR Inserts : MMIO Access. Unit: uncore_cha unc_cha_tor_inserts.local_tgtTOR Inserts : Just Local Targets. Unit: uncore_cha unc_cha_tor_inserts.remote_tgtTOR Inserts : Just Remote Targets. Unit: uncore_cha unc_cha_tor_inserts.match_opcTOR Inserts : Match the Opcode in b[29:19] of the extended umask field. Unit: uncore_cha unc_cha_tor_inserts.premorph_opcTOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field. Unit: uncore_cha unc_cha_tor_inserts.noncohTOR Inserts : Just NonCoherent. Unit: uncore_cha unc_cha_tor_inserts.isocTOR Inserts : Just ISOC. Unit: uncore_cha event=0x35,umask=0x00c88ffd01TOR Inserts; CRd Pref hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c897fd01TOR Inserts; DRd Pref hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c827fd01TOR Inserts; DRd Opt hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c8a7fd01TOR Inserts; DRd Opt Pref hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c887fd01TOR Inserts; RFO Pref hits from local IA. Unit: uncore_cha event=0x35,umask=0x00c88ffe01TOR Inserts; CRd Pref misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c827fe01TOR Inserts; DRd Opt misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c8a7fe01TOR Inserts; DRd Opt Pref misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c887fe01TOR Inserts; RFO pref misses from local IA. Unit: uncore_cha event=0x35,umask=0x00cc43fd04TOR Inserts; ItoM hits from local IO. Unit: uncore_cha unc_cha_tor_inserts.io_hit_rfoevent=0x35,umask=0x00c803fd04TOR Inserts; RFO hits from local IO. Unit: uncore_cha unc_cha_tor_inserts.io_rfoevent=0x35,umask=0x00c803ff04TOR Inserts; RFO from local IO. Unit: uncore_cha event=0x35,umask=0x00c887ff01TOR Inserts; RFO pref from local IA. Unit: uncore_cha event=0x35,umask=0x00c807ff01TOR Inserts; RFO from local IA. Unit: uncore_cha event=0x35,umask=0x00ccc7ff01TOR Inserts; LLCPrefRFO from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_drdevent=0x35,umask=0x00c817ff01TOR Inserts; DRd from local IA. Unit: uncore_cha event=0x35,umask=0x00c897ff01TOR Inserts; DRd Pref from local IA. Unit: uncore_cha event=0x35,umask=0x00c827ff01TOR Inserts; DRd Opt from local IA. Unit: uncore_cha event=0x35,umask=0x00c8a7ff01TOR Inserts; DRd Opt Pref from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_crd_prefevent=0x35,umask=0x00C88FFF01TOR Inserts; CRd Pref from local IA. Unit: uncore_cha event=0x35,umask=0x00c80fff01TOR Inserts; CRd from local IA. Unit: uncore_cha event=0x35,umask=0x00c806fe01TOR Inserts RFO misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c8077e01event=0x35,umask=0x00c886fe01TOR Inserts; RFO prefetch misses from local IA. Unit: uncore_cha event=0x35,umask=0x00c8877e01event=0x35,umask=0x00c8c7ff01TOR Inserts;CLFlush from Local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_clflushoptevent=0x35,umask=0x00c8d7ff01TOR Inserts;CLFlushOpt from Local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_itomevent=0x35,umask=0x00cc47ff01TOR Inserts;ItoM from Local IA. Unit: uncore_cha event=0x35,umask=0x00cc57ff01TOR Inserts;SpecItoM from Local IA. Unit: uncore_cha unc_cha_tor_occupancy.snps_from_remevent=0x36,umask=0x00c001ff08TOR Occupancy; All Snoops from Remote. Unit: uncore_cha unc_cha_tor_occupancy.allevent=0x36,umask=0x00C001FFffTOR Occupancy : All. Unit: uncore_cha event=0x36,umask=0x00c001ff01TOR Occupancy; All from local IA. Unit: uncore_cha event=0x36,umask=0x00c001fd01TOR Occupancy; Hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_crdevent=0x36,umask=0x00c80ffd01TOR Occupancy; CRd hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_drdevent=0x36,umask=0x00c817fd01TOR Occupancy; DRd hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_llcprefrfoevent=0x36,umask=0x00ccc7fd01TOR Occupancy; LLCPrefRFO hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_rfoevent=0x36,umask=0x00c807fd01TOR Occupancy; RFO hits from local IA. Unit: uncore_cha event=0x36,umask=0x00c001fe01TOR Occupancy; Misses from Local IA. Unit: uncore_cha event=0x36,umask=0x00c80ffe01TOR Occupancy; CRd misses from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_llcprefrfoevent=0x36,umask=0x00ccc7fe01TOR Occupancy; LLCPrefRFO misses from local IA. Unit: uncore_cha event=0x36,umask=0x00c807fe01TOR Occupancy; RFO misses from local IA. Unit: uncore_cha event=0x36,umask=0x00c001ff04TOR Occupancy; All from local IO. Unit: uncore_cha event=0x36,umask=0x00c001fd04TOR Occupancy; Hits from local IO. Unit: uncore_cha event=0x36,umask=0x00c001fe04TOR Occupancy; Misses from local IO. Unit: uncore_cha unc_cha_tor_occupancy.io_miss_rfoevent=0x36,umask=0x00c803fe04TOR Occupancy; RFO misses from local IO. Unit: uncore_cha unc_cha_tor_occupancy.io_miss_itomevent=0x36,umask=0x00cc43fe04TOR Occupancy; ITOM misses from local IO. Unit: uncore_cha unc_cha_tor_occupancy.irq_iaevent=0x36,umask=0x0000000001TOR Occupancy : IRQ - iA. Unit: uncore_cha unc_cha_tor_occupancy.evictevent=0x36,umask=0x0000000002TOR Occupancy : SF/LLC Evictions. Unit: uncore_cha unc_cha_tor_occupancy.prqevent=0x36,umask=0x0000000004TOR Occupancy : PRQ - IOSF. Unit: uncore_cha unc_cha_tor_occupancy.ipqevent=0x36,umask=0x0000000008TOR Occupancy : IPQ. Unit: uncore_cha unc_cha_tor_occupancy.irq_non_iaevent=0x36,umask=0x0000000010TOR Occupancy : IRQ - Non iA. Unit: uncore_cha unc_cha_tor_occupancy.prq_non_iosfevent=0x36,umask=0x0000000020TOR Occupancy : PRQ - Non IOSF. Unit: uncore_cha unc_cha_tor_occupancy.rrqevent=0x36,umask=0x0000000040TOR Occupancy : RRQ. Unit: uncore_cha unc_cha_tor_occupancy.wbqevent=0x36,umask=0x0000000080TOR Occupancy : WBQ. Unit: uncore_cha unc_cha_tor_occupancy.loc_ioevent=0x36,umask=0x00C000FF04TOR Occupancy : All from Local IO. Unit: uncore_cha unc_cha_tor_occupancy.loc_iaevent=0x36,umask=0x00C000FF01TOR Occupancy : All from Local iA. Unit: uncore_cha unc_cha_tor_occupancy.loc_allevent=0x36,umask=0x00C000FF05TOR Occupancy : All from Local iA and IO. Unit: uncore_cha unc_cha_tor_occupancy.rem_snpsevent=0x36,umask=0x00C001FF08TOR Occupancy : All Snoops from Remote. Unit: uncore_cha unc_cha_tor_occupancy.rem_allevent=0x36,umask=0x00C001FFC8TOR Occupancy : All from Remote. Unit: uncore_cha unc_cha_tor_occupancy.hitevent=0x36TOR Occupancy : Just Hits. Unit: uncore_cha unc_cha_tor_occupancy.missTOR Occupancy : Just Misses. Unit: uncore_cha unc_cha_tor_occupancy.mmcfgTOR Occupancy : MMCFG Access. Unit: uncore_cha unc_cha_tor_occupancy.mmioTOR Occupancy : MMIO Access. Unit: uncore_cha unc_cha_tor_occupancy.local_tgtTOR Occupancy : Just Local Targets. Unit: uncore_cha unc_cha_tor_occupancy.remote_tgtTOR Occupancy : Just Remote Targets. Unit: uncore_cha unc_cha_tor_occupancy.match_opcTOR Occupancy : Match the Opcode in b[29:19] of the extended umask field. Unit: uncore_cha unc_cha_tor_occupancy.premorph_opcTOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field. Unit: uncore_cha unc_cha_tor_occupancy.noncohTOR Occupancy : Just NonCoherent. Unit: uncore_cha unc_cha_tor_occupancy.isocTOR Occupancy : Just ISOC. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_crd_prefevent=0x36,umask=0x00c88ffd01TOR Occupancy; CRd Pref hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_drd_prefevent=0x36,umask=0x00c897fd01TOR Occupancy; DRd Pref hits from local IA. Unit: uncore_cha event=0x36,umask=0x00c827fd01TOR Occupancy; DRd Opt hits from local IA. Unit: uncore_cha event=0x36,umask=0x00c8a7fd01TOR Occupancy; DRd Opt Pref hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_rfo_prefevent=0x36,umask=0x00c887fd01TOR Occupancy; RFO Pref hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_crd_prefevent=0x36,umask=0x00c88ffe01TOR Occupancy; CRd Pref misses from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_prefevent=0x36,umask=0x00c897fe01TOR Occupancy; DRd Pref misses from local IA. Unit: uncore_cha event=0x36,umask=0x00c827fe01TOR Occupancy; DRd Opt misses from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_opt_prefevent=0x36,umask=0x00c8a7fe01TOR Occupancy; DRd Opt Pref misses from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_rfo_prefevent=0x36,umask=0x00c887fe01TOR Occupancy; RFO prefetch misses from local IA. Unit: uncore_cha unc_cha_tor_occupancy.io_hit_itomevent=0x36,umask=0x00cc43fd04TOR Occupancy; ITOM hits from local IO. Unit: uncore_cha unc_cha_tor_occupancy.io_hit_rfoevent=0x36,umask=0x00c803fd04TOR Occupancy; RFO hits from local IO. Unit: uncore_cha unc_cha_tor_occupancy.io_rfoevent=0x36,umask=0x00c803ff04TOR Occupancy; ItoM from local IO. Unit: uncore_cha unc_cha_tor_occupancy.io_itomevent=0x36,umask=0x00cc43ff04TOR Occupancy; ITOM from local IO. Unit: uncore_cha event=0x36,umask=0x00c807ff01TOR Occupancy; RFO from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_rfo_prefevent=0x36,umask=0x00c887ff01TOR Occupancy; RFO prefetch from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_llcprefrfoevent=0x36,umask=0x00ccc7ff01TOR Occupancy; LLCPrefRFO from local IA. Unit: uncore_cha event=0x36,umask=0x00c817ff01TOR Occupancy; DRd from local IA. Unit: uncore_cha event=0x36,umask=0x00c827ff01TOR Occupancy; DRd Opt from local IA. Unit: uncore_cha event=0x36,umask=0x00c8a7ff01TOR Occupancy; DRd Opt Pref from local IA. Unit: uncore_cha event=0x36,umask=0x00c80fff01TOR Occupancy; CRd from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_crd_prefevent=0x36,umask=0x00c88fff01TOR Occupancy; CRd Pref from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_drd_prefevent=0x36,umask=0x00c897ff01TOR Occupancy; DRd Pref from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_localevent=0x36,umask=0x00C896FE01unc_cha_tor_occupancy.ia_miss_drd_pref_remoteevent=0x36,umask=0x00C8977E01unc_cha_tor_occupancy.ia_miss_rfo_localevent=0x36,umask=0x00c806fe01unc_cha_tor_occupancy.ia_miss_rfo_remoteevent=0x36,umask=0x00c8077e01unc_cha_tor_occupancy.ia_miss_rfo_pref_localevent=0x36,umask=0x00c886fe01unc_cha_tor_occupancy.ia_miss_rfo_pref_remoteevent=0x36,umask=0x00c8877e01event=0x37,umask=0x0000000002All LLC lines in E state that are victimized on a fill. Unit: uncore_cha event=0x37,umask=0x0000000001All LLC lines in M state that are victimized on a fill. Unit: uncore_cha event=0x37,umask=0x0000000004All LLC lines in S state that are victimized on a fill. Unit: uncore_cha event=0x35,umask=0x00cd43fd04event=0x35,umask=0x00cd43fe04unc_cha_tor_inserts.ia_miss_drdpteevent=0x35,umask=0x00c837fe01TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_drdpteevent=0x35,umask=0x00c837fd01TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_drdpteevent=0x35,umask=0x00c837ff01TOR Inserts : DRd PTEs issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_wbeftoeevent=0x35,umask=0xcc3fff01TOR Inserts : WBEFtoEs issued by an IA Core.  Non Modified Write Backs. Unit: uncore_cha event=0x35,umask=0x00c8f3fd04TOR Inserts; RdCur and FsRdCur hits from local IO. Unit: uncore_cha event=0x35,umask=0x00c8f3fe04TOR Inserts; RdCur and FsRdCur misses from local IO. Unit: uncore_cha unc_cha_tor_occupancy.io_hit_pcirdcurevent=0x36,umask=0x00c8f3fd04TOR Occupancy; RdCur and FsRdCur hits from local IO. Unit: uncore_cha event=0x36,umask=0x00c8f3fe04TOR Occupancy; RdCur and FsRdCur misses from local IO. Unit: uncore_cha event=0x36,umask=0x00c8f3ff04TOR Occupancy; RdCur and FsRdCur from local IO. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_llcprefcodeevent=0x35,umask=0x00cccffd01TOR Inserts; LLCPrefCode hits from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_llcprefdataevent=0x35,umask=0x00ccd7fd01TOR Inserts; LLCPrefData hits from local IA. Unit: uncore_cha event=0x35,umask=0x00ccd7ff01TOR Inserts; LLCPrefData from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_llcprefcodeevent=0x35,umask=0x00cccffe01TOR Inserts; LLCPrefCode misses from local IA. Unit: uncore_cha event=0x35,umask=0x00ccd7fe01TOR Inserts; LLCPrefData misses from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_llcprefcodeevent=0x36,umask=0x00cccffd01TOR Occupancy; LLCPrefCode hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_llcprefdataevent=0x36,umask=0x00ccd7fd01TOR Occupancy; LLCPrefData hits from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_llcprefdataevent=0x36,umask=0x00ccd7ff01TOR Occupancy; LLCPrefData from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_llcprefcodeevent=0x36,umask=0x00cccffe01TOR Occupancy; LLCPrefCode misses from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_llcprefdataevent=0x36,umask=0x00ccd7fe01TOR Occupancy; LLCPrefData misses from local IA. Unit: uncore_cha unc_cha_tor_inserts.ia_llcprefcodeevent=0x35,umask=0x00cccfff01TOR Inserts; LLCPrefCode from local IA. Unit: uncore_cha unc_cha_tor_occupancy.ia_llcprefcodeevent=0x36,umask=0x00cccfff01TOR Occupancy; LLCPrefCode from local IA. Unit: uncore_cha event=0x35,umask=0x00c8168a01event=0x35,umask=0x00c8170a01event=0x35,umask=0x00c8168601event=0x35,umask=0x00c8170601unc_cha_tor_inserts.ia_miss_drd_pref_pmmevent=0x35,umask=0x00C8978A01TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref_local_pmmevent=0x35,umask=0x00C8968A01TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref_remote_pmmevent=0x35,umask=0x00C8970A01TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref_ddrevent=0x35,umask=0x00C8978601TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref_local_ddrevent=0x35,umask=0x00C8968601TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_drd_pref_remote_ddrevent=0x35,umask=0x00C8970601TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_crd_localevent=0x35,umask=0x00C80EFE01TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_crd_remoteevent=0x35,umask=0x00C80F7E01TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_crd_pref_localevent=0x35,umask=0x00C88EFE01TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_crd_pref_remoteevent=0x35,umask=0x00C88F7E01TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_itomcachenearevent=0x35,umask=0x00CD47FF01TOR Inserts : ItoMCacheNears issued by iA Cores. Unit: uncore_cha unc_cha_tor_inserts.ia_wbmtoievent=0x35,umask=0x00cc27ff01TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs. Unit: uncore_cha unc_cha_tor_inserts.ia_hit_itomevent=0x35,umask=0x00CC47FD01TOR Inserts : ItoMs issued by iA Cores that Hit LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_itomevent=0x35,umask=0x00CC47FE01TOR Inserts : ItoMs issued by iA Cores that Missed LLC. Unit: uncore_cha event=0x35,umask=0x00C877DE01event=0x35,umask=0x00C87FDE01unc_cha_tor_inserts.ia_wcilfevent=0x35,umask=0x00C867FF01TOR Inserts : WCiLF issued by iA Cores. Unit: uncore_cha event=0x35,umask=0x00C867FE01unc_cha_tor_inserts.ia_miss_wcilf_pmmevent=0x35,umask=0x00C8678A01TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_local_wcilf_pmmevent=0x35,umask=0x00C8668A01TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_remote_wcilf_pmmevent=0x35,umask=0x00C8670A01TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_wcilf_ddrevent=0x35,umask=0x00C8678601TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_local_wcilf_ddrevent=0x35,umask=0x00C8668601TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_remote_wcilf_ddrevent=0x35,umask=0x00C8670601TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_wcilevent=0x35,umask=0x00C86FFF01TOR Inserts : WCiLs issued by iA Cores. Unit: uncore_cha event=0x35,umask=0x00C86FFE01unc_cha_tor_inserts.ia_miss_wcil_pmmevent=0x35,umask=0x00C86F8A01TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_local_wcil_pmmevent=0x35,umask=0x00C86E8A01TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_remote_wcil_pmmevent=0x35,umask=0x00C86F0A01TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_wcil_ddrevent=0x35,umask=0x00C86F8601TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_local_wcil_ddrevent=0x35,umask=0x00C86E8601TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_inserts.ia_miss_remote_wcil_ddrevent=0x35,umask=0x00C86F0601TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_inserts.io_wbmtoievent=0x35,umask=0x00CC23FF04TOR Inserts : WbMtoIs issued by IO Devices. Unit: uncore_cha unc_cha_tor_inserts.io_clflushevent=0x35,umask=0x00C8C3FF04TOR Inserts : CLFlushes issued by IO Devices. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_local_pmmevent=0x36,umask=0x00c8168a01TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_remote_pmmevent=0x36,umask=0x00c8170a01TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_local_ddrevent=0x36,umask=0x00c8168601TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_remote_ddrevent=0x36,umask=0x00c8170601TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_pmmevent=0x36,umask=0x00c8978a01TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_local_pmmevent=0x36,umask=0x00c8968a01TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_remote_pmmevent=0x36,umask=0x00c8970a01TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_ddrevent=0x36,umask=0x00c8978601TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_local_ddrevent=0x36,umask=0x00c8968601TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_drd_pref_remote_ddrevent=0x36,umask=0x00c8970601TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_crd_localevent=0x36,umask=0x00c80efe01TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_crd_remoteevent=0x36,umask=0x00c80f7e01TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_crd_pref_localevent=0x36,umask=0x00c88efe01TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_crd_pref_remoteevent=0x36,umask=0x00c88f7e01TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_clflushevent=0x36,umask=0x00c8c7ff01TOR Occupancy : CLFlushes issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_clflushoptevent=0x36,umask=0x00c8d7ff01TOR Occupancy : CLFlushOpts issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_itomcachenearevent=0x36,umask=0x00cd47ff01TOR Occupancy : ItoMCacheNears issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_specitomevent=0x36,umask=0x00cc57ff01TOR Occupancy : SpecItoMs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_wbmtoievent=0x36,umask=0x00cc27ff01TOR Occupancy : WbMtoIs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_itomevent=0x36,umask=0x00cc47ff01TOR Occupancy : ItoMs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_hit_itomevent=0x36,umask=0x00cc47fd01TOR Occupancy : ItoMs issued by iA Cores that Hit LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_itomevent=0x36,umask=0x00cc47fe01TOR Occupancy : ItoMs issued by iA Cores that Missed LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_ucrdfevent=0x36,umask=0x00c877de01TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_wilevent=0x36,umask=0x00c87fde01TOR Occupancy : WiLs issued by iA Cores that Missed LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_wcilfevent=0x36,umask=0x00c867ff01TOR Occupancy : WCiLF issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_wcilfevent=0x36,umask=0x00c867fe01TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_wcilf_pmmevent=0x36,umask=0x00c8678a01TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_local_wcilf_pmmevent=0x36,umask=0x00c8668a01TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_remote_wcilf_pmmevent=0x36,umask=0x00c8670a01TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_wcilf_ddrevent=0x36,umask=0x00c8678601TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_local_wcilf_ddrevent=0x36,umask=0x00c8668601TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_remote_wcilf_ddrevent=0x36,umask=0x00c8670601TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_wcilevent=0x36,umask=0x00c86fff01TOR Occupancy : WCiLs issued by iA Cores. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_wcilevent=0x36,umask=0x00c86ffe01TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_wcil_pmmevent=0x36,umask=0x00c86f8a01TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_local_wcil_pmmevent=0x36,umask=0x00c86e8a01TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_remote_wcil_pmmevent=0x36,umask=0x00c86f0a01TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_wcil_ddrevent=0x36,umask=0x00c86f8601TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_local_wcil_ddrevent=0x36,umask=0x00c86e8601TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally. Unit: uncore_cha unc_cha_tor_occupancy.ia_miss_remote_wcil_ddrevent=0x36,umask=0x00c86f0601TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely. Unit: uncore_cha unc_cha_tor_occupancy.io_wbmtoievent=0x36,umask=0x00cc23ff04TOR Occupancy : WbMtoIs issued by IO Devices. Unit: uncore_cha unc_cha_tor_occupancy.io_clflushevent=0x36,umask=0x00c8c3ff04TOR Occupancy : CLFlushes issued by IO Devices. Unit: uncore_cha unc_cha_tor_occupancy.io_hit_itomcachenearevent=0x36,umask=0x00cd43fd04TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC. Unit: uncore_cha unc_cha_tor_occupancy.io_miss_itomcachenearevent=0x36,umask=0x00cd43fe04TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC. Unit: uncore_cha unc_cha_tor_occupancy.pmmTOR Occupancy : PMM Access. Unit: uncore_cha unc_cha_tor_inserts.pmmTOR Inserts : PMM Access. Unit: uncore_cha unc_cha_tor_occupancy.ddrTOR Occupancy : DDR Access. Unit: uncore_cha unc_cha_tor_inserts.ddrTOR Inserts : DDR Access. Unit: uncore_cha PCU PCLK Clockticks. Unit: uncore_pcu bp_l1_btb_correctevent=0x8aL1 BTB Correctionbranchbp_l2_btb_correctevent=0x8bL2 BTB Correctionbp_dyn_ind_predevent=0x8eDynamic Indirect PredictionsIndirect Branch Prediction for potential multi-target branch (speculative)bp_de_redirectevent=0x91Decoder Overrides Existing Branch Prediction (speculative)bp_l1_tlb_fetch_hitevent=0x94The number of instruction fetches that hit in the L1 ITLBic_fw32The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses)ic_fw32_missThe number of 32B fetch windows tried to read the L1 IC and missed in the full tagic_cache_fill_l2The number of 64 byte instruction cache line was fulfilled from the L2 cacheic_cache_fill_sysThe number of 64 byte instruction cache line fulfilled from system memory or another cachebp_l1_tlb_miss_l2_hitevent=0x84The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLBbp_l1_tlb_miss_l2_missThe number of instruction fetches that miss in both the L1 and L2 TLBsbp_snp_re_syncThe number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely eventic_fetch_stall.ic_stall_anyevent=0x87,umask=0x04Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1)ic_fetch_stall.ic_stall_dq_emptyevent=0x87,umask=0x02Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ emptyic_fetch_stall.ic_stall_back_pressureevent=0x87,umask=0x01Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressureic_cache_inval.l2_invalidating_probeevent=0x8c,umask=0x02IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another coreic_cache_inval.fill_invalidatedevent=0x8c,umask=0x01IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another corebp_tlb_relevent=0x99The number of ITLB reload requestsl2_request_g1.rd_blk_levent=0x60,umask=0x80All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and software prefetch)l2_request_g1.rd_blk_xevent=0x60,umask=0x40All L2 Cache Requests (Breakdown 1 - Common). Data cache storesl2_request_g1.ls_rd_blk_c_sevent=0x60,umask=0x20All L2 Cache Requests (Breakdown 1 - Common). Data cache shared readsl2_request_g1.cacheable_ic_readevent=0x60,umask=0x10All L2 Cache Requests (Breakdown 1 - Common). Instruction cache readsl2_request_g1.change_to_xevent=0x60,umask=0x08All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current statel2_request_g1.prefetch_l2_cmdevent=0x60,umask=0x04All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmdl2_request_g1.l2_hw_pfevent=0x60,umask=0x02All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon eventl2_request_g1.group2event=0x60,umask=0x01Miscellaneous events covered in more detail by l2_request_g2 (PMCx061)l2_request_g1.all_no_prefetchevent=0x60,umask=0xf9l2_request_g2.group1event=0x61,umask=0x80Miscellaneous events covered in more detail by l2_request_g1 (PMCx060)l2_request_g2.ls_rd_sizedevent=0x61,umask=0x40All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sizedl2_request_g2.ls_rd_sized_ncevent=0x61,umask=0x20All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheablel2_request_g2.ic_rd_sizedevent=0x61,umask=0x10All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sizedl2_request_g2.ic_rd_sized_ncevent=0x61,umask=0x08All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheablel2_request_g2.smc_invalevent=0x61,umask=0x04All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidatesl2_request_g2.bus_locks_originatorevent=0x61,umask=0x02All L2 Cache Requests (Breakdown 2 - Rare). Bus locksl2_request_g2.bus_locks_responsesevent=0x61,umask=0x01All L2 Cache Requests (Breakdown 2 - Rare). Bus lock responsel2_latency.l2_cycles_waiting_on_fillsevent=0x62,umask=0x01Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be usedl2_wcb_req.wcb_writeevent=0x63,umask=0x40LS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) write requestsl2_wcb_req.wcb_closeevent=0x63,umask=0x20LS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) close requestsl2_wcb_req.zero_byte_storeevent=0x63,umask=0x04LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requestsl2_wcb_req.cl_zeroevent=0x63,umask=0x01LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requestsl2_cache_req_stat.ls_rd_blk_csevent=0x64,umask=0x80Core to L2 cacheable request access status (not including L2 Prefetch). Data cache shared read hit in L2l2_cache_req_stat.ls_rd_blk_l_hit_xevent=0x64,umask=0x40Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2l2_cache_req_stat.ls_rd_blk_l_hit_sevent=0x64,umask=0x20Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit on shared line in L2l2_cache_req_stat.ls_rd_blk_xevent=0x64,umask=0x10Core to L2 cacheable request access status (not including L2 Prefetch). Data cache store or state change hit in L2l2_cache_req_stat.ls_rd_blk_cevent=0x64,umask=0x08Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types)l2_cache_req_stat.ic_fill_hit_xevent=0x64,umask=0x04Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2l2_cache_req_stat.ic_fill_hit_sevent=0x64,umask=0x02Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2l2_cache_req_stat.ic_fill_missevent=0x64,umask=0x01Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2l2_cache_req_stat.ic_access_in_l2event=0x64,umask=0x07Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2l2_cache_req_stat.ic_dc_miss_in_l2event=0x64,umask=0x09Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types)l2_cache_req_stat.ic_dc_hit_in_l2event=0x64,umask=0xf6Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types)l2_fill_pending.l2_fill_busyevent=0x6d,umask=0x01Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2l2_pf_hit_l2event=0x70,umask=0xffL2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf insteadl2_pf_miss_l2_hit_l3event=0x71,umask=0xffL2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3l2_pf_miss_l2_l3event=0x72,umask=0xffL2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 cachesl3_request_g1.caching_l3_cache_accessesevent=0x1,umask=0x80Caching: L3 cache accesses. Unit: amd_l3 amd_l3l3_lookup_state.all_l3_req_typsevent=0x4,umask=0xffAll L3 Request Types. Unit: amd_l3 l3_comb_clstr_state.other_l3_miss_typsevent=0x6,umask=0xfeOther L3 Miss Request Types. Unit: amd_l3 l3_comb_clstr_state.request_missevent=0x6,umask=0x01L3 cache misses. Unit: amd_l3 xi_sys_fill_latencyevent=0x90,umask=0x00L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignores SliceMask and ThreadMask. Unit: amd_l3 xi_ccx_sdp_req1.all_l3_miss_req_typsevent=0x9a,umask=0x3fAll L3 Miss Request Types. Ignores SliceMask and ThreadMask. Unit: amd_l3 ex_ret_instrRetired Instructionsex_ret_copsevent=0xc1Retired UopsThe number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4ex_ret_brnevent=0xc2Retired Branch InstructionsThe number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interruptsex_ret_brn_mispevent=0xc3Retired Branch Instructions MispredictedThe number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)ex_ret_brn_tknevent=0xc4Retired Taken Branch InstructionsThe number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interruptsex_ret_brn_tkn_mispevent=0xc5Retired Taken Branch Instructions MispredictedThe number of retired taken branch instructions that were mispredictedex_ret_brn_farevent=0xc6Retired Far Control TransfersThe number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch predictionex_ret_brn_resyncevent=0xc7Retired Branch ResyncsThe number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rareex_ret_near_retevent=0xc8Retired Near ReturnsThe number of near return instructions (RET or RET Iw) retiredex_ret_near_ret_mispredevent=0xc9Retired Near Returns MispredictedThe number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instructionex_ret_brn_ind_mispevent=0xcaRetired Indirect Branch Instructions Mispredictedex_ret_mmx_fp_instr.sse_instrevent=0xcb,umask=0x04SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)ex_ret_mmx_fp_instr.mmx_instrevent=0xcb,umask=0x02MMX instructionsThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructionsex_ret_mmx_fp_instr.x87_instrevent=0xcb,umask=0x01x87 instructionsThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructionsex_ret_condevent=0xd1Retired Conditional Branch Instructionsex_div_busyevent=0xd3Div Cycles Busy countex_div_countevent=0xd4Div Op Countex_tagged_ibs_ops.ibs_count_rolloverevent=0x1cf,umask=0x04Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retiredex_tagged_ibs_ops.ibs_tagged_ops_retevent=0x1cf,umask=0x02Tagged IBS Ops. Number of Ops tagged by IBS that retiredex_tagged_ibs_ops.ibs_tagged_opsevent=0x1cf,umask=0x01Tagged IBS Ops. Number of Ops tagged by IBSex_ret_fus_brnch_instevent=0x1d0The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3remote_outbound_data_controller_0event=0x7c7,umask=0x02Unit: amd_df data fabricRemote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0amd_dfremote_outbound_data_controller_1event=0x807,umask=0x02Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1remote_outbound_data_controller_2event=0x847,umask=0x02Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2remote_outbound_data_controller_3event=0x887,umask=0x02Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3dram_channel_data_controller_0event=0x7,umask=0x38DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0dram_channel_data_controller_1event=0x47,umask=0x38dram_channel_data_controller_2event=0x87,umask=0x38dram_channel_data_controller_3event=0xc7,umask=0x38dram_channel_data_controller_4event=0x107,umask=0x38dram_channel_data_controller_5event=0x147,umask=0x38dram_channel_data_controller_6event=0x187,umask=0x38dram_channel_data_controller_7event=0x1c7,umask=0x38fpu_pipe_assignment.dualevent=0,umask=0xf0Total number multi-pipe uOps assigned to all pipesThe number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipesfpu_pipe_assignment.dual3event=0,umask=0x80Total number multi-pipe uOps assigned to pipe 3The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3fpu_pipe_assignment.dual2event=0,umask=0x40Total number multi-pipe uOps assigned to pipe 2The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2fpu_pipe_assignment.dual1event=0,umask=0x20Total number multi-pipe uOps assigned to pipe 1The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1fpu_pipe_assignment.dual0event=0,umask=0x10Total number multi-pipe uOps assigned to pipe 0The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 0fpu_pipe_assignment.totalevent=0,umask=0x0fTotal number uOps assigned to all fpu pipesThe number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipesfpu_pipe_assignment.total3event=0,umask=0x08Total number of fp uOps on pipe 3The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3fpu_pipe_assignment.total2event=0,umask=0x04Total number of fp uOps on pipe 2The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2fpu_pipe_assignment.total1event=0,umask=0x02Total number of fp uOps on pipe 1The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1fpu_pipe_assignment.total0Total number of fp uOps  on pipe 0The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0fp_sched_emptyThis is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the schedulerfp_retx87_fp_ops.allevent=0x2,umask=0x07All OpsThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8fp_retx87_fp_ops.div_sqr_r_opsDivide and square root OpsThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Opsfp_retx87_fp_ops.mul_opsevent=0x2,umask=0x02Multiply OpsThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply Opsfp_retx87_fp_ops.add_sub_opsAdd/subtract OpsThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Opsfp_ret_sse_avx_ops.allevent=0x3,umask=0xffAll FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.dp_mult_add_flopsevent=0x3,umask=0x80Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSfp_ret_sse_avx_ops.dp_div_flopsevent=0x3,umask=0x40Double precision divide/square root FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision divide/square root FLOPSfp_ret_sse_avx_ops.dp_mult_flopsevent=0x3,umask=0x20Double precision multiply FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision multiply FLOPSfp_ret_sse_avx_ops.dp_add_sub_flopsevent=0x3,umask=0x10Double precision add/subtract FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Double precision add/subtract FLOPSfp_ret_sse_avx_ops.sp_mult_add_flopsevent=0x3,umask=0x08Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSfp_ret_sse_avx_ops.sp_div_flopsevent=0x3,umask=0x04Single-precision divide/square root FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPSfp_ret_sse_avx_ops.sp_mult_flopsSingle-precision multiply FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPSfp_ret_sse_avx_ops.sp_add_sub_flopsSingle-precision add/subtract FLOPSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPSfp_num_mov_elim_scal_op.optimizedevent=0x4,umask=0x08Number of Scalar Ops optimizedThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimizedfp_num_mov_elim_scal_op.opt_potentialevent=0x4,umask=0x04Number of Ops that are candidates for optimization (have Z-bit either set or pass)This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass)fp_num_mov_elim_scal_op.sse_mov_ops_elimevent=0x4,umask=0x02Number of SSE Move Ops eliminatedThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminatedfp_num_mov_elim_scal_op.sse_mov_opsevent=0x4,umask=0x01Number of SSE Move OpsThis is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Opsfp_retired_ser_ops.x87_ctrl_retevent=0x5,umask=0x08x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bitsThe number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bitsfp_retired_ser_ops.x87_bot_retevent=0x5,umask=0x04x87 bottom-executing uOps retiredThe number of serializing Ops retired. x87 bottom-executing uOps retiredfp_retired_ser_ops.sse_ctrl_retevent=0x5,umask=0x02SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bitsThe number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bitsfp_retired_ser_ops.sse_bot_retevent=0x5,umask=0x01SSE bottom-executing uOps retiredThe number of serializing Ops retired. SSE bottom-executing uOps retiredls_locks.bus_lockevent=0x25,umask=0x01Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory typels_dispatch.ld_st_dispatchevent=0x29,umask=0x04Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Storesls_dispatch.store_dispatchevent=0x29,umask=0x02Counts the number of stores dispatched to the LS unit. Unit Masks ADDedls_dispatch.ld_dispatchevent=0x29,umask=0x01Counts the number of loads dispatched to the LS unit. Unit Masks ADDedls_stlfNumber of STLF hitsls_dc_accessesThe number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative eventls_mab_alloc.dc_prefetcherevent=0x41,umask=0x08LS MAB allocates by type - DC prefetcherls_mab_alloc.storesevent=0x41,umask=0x02LS MAB allocates by type - storesls_mab_alloc.loadsevent=0x41,umask=0x01LS MAB allocates by type - loadsls_l1_d_tlb_miss.allevent=0x45,umask=0xffL1 DTLB Miss or Reload off all sizesls_l1_d_tlb_miss.tlb_reload_1g_l2_missevent=0x45,umask=0x80L1 DTLB Miss of a page of 1G sizels_l1_d_tlb_miss.tlb_reload_2m_l2_missevent=0x45,umask=0x40L1 DTLB Miss of a page of 2M sizels_l1_d_tlb_miss.tlb_reload_32k_l2_missevent=0x45,umask=0x20L1 DTLB Miss of a page of 32K sizels_l1_d_tlb_miss.tlb_reload_4k_l2_missevent=0x45,umask=0x10L1 DTLB Miss of a page of 4K sizels_l1_d_tlb_miss.tlb_reload_1g_l2_hitevent=0x45,umask=0x08L1 DTLB Reload of a page of 1G sizels_l1_d_tlb_miss.tlb_reload_2m_l2_hitL1 DTLB Reload of a page of 2M sizels_l1_d_tlb_miss.tlb_reload_32k_l2_hitL1 DTLB Reload of a page of 32K sizels_l1_d_tlb_miss.tlb_reload_4k_l2_hitL1 DTLB Reload of a page of 4K sizels_tablewalker.isideevent=0x46,umask=0x0cTotal Page Table Walks on I-sidels_tablewalker.ic_type1event=0x46,umask=0x08Total Page Table Walks IC Type 1ls_tablewalker.ic_type0event=0x46,umask=0x04Total Page Table Walks IC Type 0ls_tablewalker.dsideevent=0x46,umask=0x03Total Page Table Walks on D-sidels_tablewalker.dc_type1event=0x46,umask=0x02Total Page Table Walks DC Type 1ls_tablewalker.dc_type0event=0x46,umask=0x01Total Page Table Walks DC Type 0ls_misal_accessesevent=0x47Misaligned loadsls_pref_instr_disp.prefetch_ntaevent=0x4b,umask=0x04Software Prefetch Instructions (PREFETCHNTA instruction) Dispatchedls_pref_instr_disp.store_prefetch_wevent=0x4b,umask=0x02Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatchedls_pref_instr_disp.load_prefetch_wevent=0x4b,umask=0x01Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2ls_inef_sw_pref.mab_mch_cntevent=0x52,umask=0x02The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request bufferls_inef_sw_pref.data_pipe_sw_pf_dc_hitevent=0x52,umask=0x01The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hitls_not_halted_cycevent=0x76Cycles not in Haltic_oc_mode_switch.oc_ic_mode_switchevent=0x28a,umask=0x02OC Mode Switch. OC to IC mode switchic_oc_mode_switch.ic_oc_mode_switchevent=0x28a,umask=0x01OC Mode Switch. IC to OC mode switchde_dis_dispatch_token_stalls0.retire_token_stallevent=0xaf,umask=0x40Cycles where a dispatch group is valid but does not get dispatched due to a token stall. RETIRE Tokens unavailablede_dis_dispatch_token_stalls0.agsq_token_stallevent=0xaf,umask=0x20Cycles where a dispatch group is valid but does not get dispatched due to a token stall. AGSQ Tokens unavailablede_dis_dispatch_token_stalls0.alu_token_stallevent=0xaf,umask=0x10Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailablede_dis_dispatch_token_stalls0.alsq3_0_token_stallevent=0xaf,umask=0x08Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailablede_dis_dispatch_token_stalls0.alsq3_token_stallevent=0xaf,umask=0x04Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailablede_dis_dispatch_token_stalls0.alsq2_token_stallevent=0xaf,umask=0x02Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailablede_dis_dispatch_token_stalls0.alsq1_token_stallevent=0xaf,umask=0x01Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailableExecution-Time Branch Misprediction Ratio (Non-Speculative)recommended100%d_ratio(ex_ret_brn_misp, ex_ret_brn)branch_misprediction_ratiobranch_predictionall_dc_accessesevent=0x29,umask=0x07All L1 Data Cache AccessesAll L2 Cache Accessesl2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3all_l2_cache_accessesl2_cachel2_cache_accesses_from_ic_missesL2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)l2_cache_accesses_from_dc_missesevent=0x60,umask=0xc8L2 Cache Accesses from L1 Data Cache Misses (including prefetch)L2 Cache Accesses from L2 HWPFl2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3l2_cache_accesses_from_l2_hwpfAll L2 Cache Missesl2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3all_l2_cache_missesl2_cache_misses_from_ic_missL2 Cache Misses from L1 Instruction Cache Missesl2_cache_misses_from_dc_missesL2 Cache Misses from L1 Data Cache MissesL2 Cache Misses from L2 HWPFl2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3l2_cache_misses_from_l2_hwpfAll L2 Cache Hitsl2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2all_l2_cache_hitsl2_cache_hits_from_ic_missesevent=0x64,umask=0x06L2 Cache Hits from L1 Instruction Cache Missesl2_cache_hits_from_dc_missesevent=0x64,umask=0x70L2 Cache Hits from L1 Data Cache Missesl2_cache_hits_from_l2_hwpfL2 Cache Hits from L2 HWPFl3_accessesL3 Accesses. Unit: amd_l3 l3_missesL3 Misses (includes Chg2X). Unit: amd_l3 Average L3 Read Miss Latency (in core clocks)1core clocks(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typsl3_read_miss_latencyl3_cacheL1 Instruction Cache (32B) Fetch Miss Ratiod_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss)ic_fetch_miss_ratioL1 ITLB Missesbp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_missl1_itlb_missestlbl2_itlb_missesevent=0x85,umask=0x07L2 ITLB Misses & Instruction page walksl1_dtlb_missesL1 DTLB Missesl2_dtlb_missesevent=0x45,umask=0xf0L2 DTLB Misses & Data page walksall_tlbs_flushedevent=0x78,umask=0xdfAll TLBs Flusheduops_dispatchedevent=0xaa,umask=0x03Micro-ops Dispatchedsse_avx_stallsevent=0xe,umask=0x0eMixed SSE/AVX Stallsuops_retiredMicro-ops RetiredApproximate: Outbound data bytes for all Remote Links for a node (die)3e-5MiBremote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3all_remote_links_outbounddata_fabricApproximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)6.1e-5MiBdram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7nps1_die_to_dramL1 Branch Prediction Overrides Existing Prediction (speculative)L2 Branch Prediction Overrides Existing Prediction (speculative)event=0x94,umask=0xffbp_l1_tlb_fetch_hit.if1gevent=0x94,umask=0x04The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB pagebp_l1_tlb_fetch_hit.if2mevent=0x94,umask=0x02The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB pagebp_l1_tlb_fetch_hit.if4kevent=0x94,umask=0x01The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB pagebp_l1_tlb_miss_l2_tlb_missevent=0x85,umask=0xffbp_l1_tlb_miss_l2_tlb_miss.if1gevent=0x85,umask=0x04The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB pagebp_l1_tlb_miss_l2_tlb_miss.if2mevent=0x85,umask=0x02The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB pagebp_l1_tlb_miss_l2_tlb_miss.if4kevent=0x85,umask=0x01The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB pageThe number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8ex_ret_cond_mispevent=0xd2Retired Conditional Branch Instructions MispredictedRetired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8Total number of fp uOpsTotal number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPSTotal number uOps assigned to pipe 3Total number uOps assigned to pipe 2Total number uOps assigned to pipe 1All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.mac_flopsMultiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.div_flopsDivide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.mult_flopsMultiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15fp_ret_sse_avx_ops.add_sub_flopsAdd/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesNumber of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesNumber of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesNumber of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemesSSE bottom-executing uOps retired. The number of serializing Ops retiredx87 bottom-executing uOps retired. The number of serializing Ops retiredx87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retiredfp_disp_faults.ymm_spill_faultevent=0xe,umask=0x08Floating Point Dispatch Faults. YMM spill faultfp_disp_faults.ymm_fill_faultevent=0xe,umask=0x04Floating Point Dispatch Faults. YMM fill faultfp_disp_faults.xmm_fill_faultevent=0xe,umask=0x02Floating Point Dispatch Faults. XMM fill faultfp_disp_faults.x87_fill_faultevent=0xe,umask=0x01Floating Point Dispatch Faults. x87 fill faultls_bad_status2.stli_otherevent=0x24,umask=0x02Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reasonStore-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element storesls_locks.spec_lock_hi_specevent=0x25,umask=0x08Retired lock instructions. High speculative cacheable lock speculation succeededls_locks.spec_lock_lo_specevent=0x25,umask=0x04Retired lock instructions. Low speculative cacheable lock speculation succeededls_locks.non_spec_lockevent=0x25,umask=0x02Retired lock instructions. Non-speculative lock succeededRetired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lockls_ret_cl_flushNumber of retired CLFLUSH instructionsls_ret_cpuidNumber of retired CPUID instructionsDispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an addressNumber of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedNumber of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedls_smi_rxNumber of SMIs receivedls_int_takenevent=0x2cNumber of interrupts takenls_rdtscevent=0x2dNumber of reads of the TSC (RDTSC instructions). The count is speculativels_st_commit_cancel2.st_commit_cancel_wcb_fullevent=0x37A non-cacheable store and the non-cacheable commit buffer is fullNumber of accesses to the dcache for load/store referencesLS MAB Allocates by Type. DC prefetcherLS MAB Allocates by Type. StoresLS MAB Allocates by Type. Loadsls_refills_from_sys.ls_mabresp_rmt_dramevent=0x43,umask=0x40Demand Data Cache Fills by Data Source. DRAM or IO from different diels_refills_from_sys.ls_mabresp_rmt_cacheevent=0x43,umask=0x10Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different diels_refills_from_sys.ls_mabresp_lcl_dramevent=0x43,umask=0x08Demand Data Cache Fills by Data Source. DRAM or IO from this thread's diels_refills_from_sys.ls_mabresp_lcl_cacheevent=0x43,umask=0x02Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's diels_refills_from_sys.ls_mabresp_lcl_l2event=0x43,umask=0x01Demand Data Cache Fills by Data Source. Local L2 hitAll L1 DTLB Misses or ReloadsL1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLBL1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLBls_l1_d_tlb_miss.tlb_reload_coalesced_page_missL1 DTLB Miss. DTLB reload coalesced page missL1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLBL1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLBL1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLBls_l1_d_tlb_miss.tlb_reload_coalesced_page_hitL1 DTLB Miss. DTLB reload hit a coalesced pageL1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLBls_pref_instr_dispevent=0x4b,umask=0xffSoftware Prefetch Instructions Dispatched (Speculative)Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevells_pref_instr_disp.prefetch_wSoftware Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHWls_pref_instr_disp.prefetchSoftware Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevells_sw_pf_dc_fill.ls_mabresp_rmt_dramevent=0x59,umask=0x40Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote)ls_sw_pf_dc_fill.ls_mabresp_rmt_cacheevent=0x59,umask=0x10Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote)ls_sw_pf_dc_fill.ls_mabresp_lcl_dramevent=0x59,umask=0x08Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die.  From DRAM (home node local)ls_sw_pf_dc_fill.ls_mabresp_lcl_cacheevent=0x59,umask=0x02Software Prefetch Data Cache Fills by Data Source. From another cache (home node local)ls_sw_pf_dc_fill.ls_mabresp_lcl_l2Software Prefetch Data Cache Fills by Data Source. Local L2 hitls_hw_pf_dc_fill.ls_mabresp_rmt_dramevent=0x5a,umask=0x40Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote)ls_hw_pf_dc_fill.ls_mabresp_rmt_cacheevent=0x5a,umask=0x10Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote)ls_hw_pf_dc_fill.ls_mabresp_lcl_dramevent=0x5a,umask=0x08Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local)ls_hw_pf_dc_fill.ls_mabresp_lcl_cacheevent=0x5a,umask=0x02Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local)ls_hw_pf_dc_fill.ls_mabresp_lcl_l2event=0x5a,umask=0x01Hardware Prefetch Data Cache Fills by Data Source. Local L2 hitls_tlb_flushevent=0x78All TLB Flushesde_dis_uop_queue_empty_di0event=0xa9Cycles where the Micro-Op Queue is emptyde_dis_uops_from_decoderevent=0xaa,umask=0xffOps dispatched from either the decoders, OpCache or bothde_dis_uops_from_decoder.opcache_dispatchedevent=0xaa,umask=0x02Count of dispatched Ops from OpCachede_dis_uops_from_decoder.decoder_dispatchedevent=0xaa,umask=0x01Count of dispatched Ops from Decoderde_dis_dispatch_token_stalls1.fp_misc_rsrc_stallevent=0xae,umask=0x80Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP opsde_dis_dispatch_token_stalls1.fp_sch_rsrc_stallevent=0xae,umask=0x40Cycles where a dispatch group is valid but does not get dispatched due to a token stall. FP scheduler resource stall. Applies to ops that use the FP schedulerde_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stallevent=0xae,umask=0x20Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Floating point register file resource stall. Applies to all FP ops that have a destination registerde_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stallevent=0xae,umask=0x10Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Taken branch buffer resource stallde_dis_dispatch_token_stalls1.int_sched_misc_token_stallevent=0xae,umask=0x08Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stallde_dis_dispatch_token_stalls1.store_queue_token_stallevent=0xae,umask=0x04Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semanticsde_dis_dispatch_token_stalls1.load_queue_token_stallevent=0xae,umask=0x02Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semanticsde_dis_dispatch_token_stalls1.int_phy_reg_file_token_stallevent=0xae,umask=0x01Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination registerde_dis_dispatch_token_stalls0.sc_agu_dispatch_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. SC AGU dispatch stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ3_0_TokenStalld_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss)bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_missThe number of times a branch used the indirect predictor to make a predictionDecode RedirectsThe number of times the instruction decoder overrides the predicted targetThe number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (1G page size)The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB hit (2M page size)The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB hit (4K or 16K page size)Core to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit in L2. ModifiableCore to L2 cacheable request access status (not including L2 Prefetch). Data cache read hit non-modifiable line in L2Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types). Use l2_cache_misses_from_dc_misses insteadCore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit non-modifiable line in L2Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2. Use l2_cache_misses_from_ic_miss insteadL2 prefetcher misses in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 cachesInstruction Cache Refills from L2. The number of 64 byte instruction cache line was fulfilled from the L2 cacheInstruction Cache Refills from System. The number of 64 byte instruction cache line fulfilled from system memory or another cachebp_l1_tlb_miss_l2_tlb_hitL1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLBbp_l1_tlb_miss_l2_tlb_miss.coalesced_4kevent=0x85,umask=0x08The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for >4K Coalesced pageThe number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 1G pageThe number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk for 2M pageThe number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses. Walk to 4K pageic_tag_hit_miss.all_instruction_cache_accessesevent=0x18e,umask=0x1fAll Instruction Cache Accesses. Counts various IC tag related hit and miss eventsic_tag_hit_miss.instruction_cache_missevent=0x18e,umask=0x18Instruction Cache Miss. Counts various IC tag related hit and miss eventsic_tag_hit_miss.instruction_cache_hitevent=0x18e,umask=0x07Instruction Cache Hit. Counts various IC tag related hit and miss eventsop_cache_hit_miss.all_op_cache_accessesevent=0x28f,umask=0x07All Op Cache accesses. Counts Op Cache micro-tag hit/miss eventsop_cache_hit_miss.op_cache_missevent=0x28f,umask=0x04Op Cache Miss. Counts Op Cache micro-tag hit/miss eventsop_cache_hit_miss.op_cache_hitevent=0x28f,umask=0x03Op Cache Hit. Counts Op Cache micro-tag hit/miss eventsAll L3 Request Types. All L3 cache Requests. Unit: amd_l3 event=0x90xi_ccx_sdp_req1event=0x9a,umask=0xffL3 Misses by Request Type. Ignores SliceID, EnAllSlices, CoreID, EnAllCores and ThreadMask. Requires unit mask 0xFF to engage event for counting. Unit: amd_l3 ex_ret_opsRetired Ops. Use macro_ops_retired insteadThe number of macro-ops retiredThe number of retired branch instructions, that were mispredictedThe number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are countedThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPSex_ret_ind_brch_instrevent=0xccRetired Indirect Branch Instructions. The number of indirect branches retiredex_ret_msprd_brnch_instr_dir_msmtchevent=0x1c7Retired Mispredicted Branch Instructions due to Direction MismatchThe number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatchex_ret_fused_instrCounts retired Fused InstructionsMultiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEventDivide/square root FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEventMultiply FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEventAdd/subtract FLOPs. This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEventSSE/AVX bottom-executing ops retired. The number of serializing Ops retiredSSE/AVX control word mispredict traps. The number of serializing Ops retiredx87 bottom-executing ops retired. The number of serializing Ops retiredRetired lock instructions. Comparable to legacy bus lockThe number of retired CLFLUSH instructions. This is a non-speculative eventThe number of CPUID instructions retiredLoad-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedDispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedDispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDedCounts the number of SMIs receivedCounts the number of interrupts takenls_mab_alloc.all_allocationsevent=0x41,umask=0x7fAll Allocations. Counts when a LS pipe allocates a MAB entryls_mab_alloc.hardware_prefetcher_allocationsevent=0x41,umask=0x40Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entryls_mab_alloc.load_store_allocationsevent=0x41,umask=0x3fLoad Store Allocations. Counts when a LS pipe allocates a MAB entryls_dmnd_fills_from_sys.mem_io_remoteDemand Data Cache Fills by Data Source. From DRAM or IO connected in different Nodels_dmnd_fills_from_sys.ext_cache_remoteDemand Data Cache Fills by Data Source. From CCX Cache in different Nodels_dmnd_fills_from_sys.mem_io_localDemand Data Cache Fills by Data Source. From DRAM or IO connected in same nodels_dmnd_fills_from_sys.ext_cache_localevent=0x43,umask=0x04Demand Data Cache Fills by Data Source. From cache of different CCX in same nodels_dmnd_fills_from_sys.int_cacheDemand Data Cache Fills by Data Source. From L3 or different L2 in same CCXls_dmnd_fills_from_sys.lcl_l2Demand Data Cache Fills by Data Source. From Local L2 to the corels_any_fills_from_sys.mem_io_remoteevent=0x44,umask=0x40Any Data Cache Fills by Data Source. From DRAM or IO connected in different Nodels_any_fills_from_sys.ext_cache_remoteevent=0x44,umask=0x10Any Data Cache Fills by Data Source. From CCX Cache in different Nodels_any_fills_from_sys.mem_io_localevent=0x44,umask=0x08Any Data Cache Fills by Data Source. From DRAM or IO connected in same nodels_any_fills_from_sys.ext_cache_localevent=0x44,umask=0x04Any Data Cache Fills by Data Source. From cache of different CCX in same nodels_any_fills_from_sys.int_cacheevent=0x44,umask=0x02Any Data Cache Fills by Data Source. From L3 or different L2 in same CCXls_any_fills_from_sys.lcl_l2event=0x44,umask=0x01Any Data Cache Fills by Data Source. From Local L2 to the coreAll L1 DTLB Misses or Reloads. Use l1_dtlb_misses insteadL1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLBL1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLBL1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLBL1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLBL1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLBls_misal_loads.ma4kevent=0x47,umask=0x02The number of 4KB misaligned (i.e., page crossing) loadsls_misal_loads.ma64event=0x47,umask=0x01The number of 64B misaligned (i.e., cacheline crossing) loadsSoftware Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHWSoftware Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevells_sw_pf_dc_fills.mem_io_remoteSoftware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Nodels_sw_pf_dc_fills.ext_cache_remoteSoftware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Nodels_sw_pf_dc_fills.mem_io_localSoftware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same nodels_sw_pf_dc_fills.ext_cache_localevent=0x59,umask=0x04Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same nodels_sw_pf_dc_fills.int_cacheSoftware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCXls_sw_pf_dc_fills.lcl_l2Software Prefetch Data Cache Fills by Data Source. From Local L2 to the corels_hw_pf_dc_fills.mem_io_remoteHardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Nodels_hw_pf_dc_fills.ext_cache_remoteHardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Nodels_hw_pf_dc_fills.mem_io_localHardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same nodels_hw_pf_dc_fills.ext_cache_localevent=0x5a,umask=0x04Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same nodels_hw_pf_dc_fills.int_cacheHardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCXls_hw_pf_dc_fills.lcl_l2Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the corels_alloc_mab_countevent=0x5fCount of Allocated MabsThis event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events]ls_tlb_flush.all_tlb_flushesevent=0x78,umask=0xffAll TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed insteadde_dis_cops_from_decoder.disp_op_type.any_integer_dispatchevent=0xab,umask=0x08Any Integer dispatch. Types of Oops Dispatched from Decoderde_dis_cops_from_decoder.disp_op_type.any_fp_dispatchevent=0xab,umask=0x04Any FP dispatch. Types of Oops Dispatched from Decoderde_dis_dispatch_token_stalls1.fp_flush_recovery_stallCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP Flush recovery stallCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. FP scheduler resource stall. Applies to ops that use the FP schedulerCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Floating point register file resource stall. Applies to all FP ops that have a destination registerde_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrcCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Taken branch buffer resource stallde_dis_dispatch_token_stalls1.store_queue_rsrc_stallCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Store Queue resource stall. Applies to all ops with store semanticsde_dis_dispatch_token_stalls1.load_queue_rsrc_stallCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Load Queue resource stall. Applies to all ops with load semanticsde_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stallCycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall. Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination registerde_dis_dispatch_token_stalls2.retire_token_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. Insufficient Retire Queue tokens availablede_dis_dispatch_token_stalls2.agsq_token_stallde_dis_dispatch_token_stalls2.int_sch3_token_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 3 availablede_dis_dispatch_token_stalls2.int_sch2_token_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 2 availablede_dis_dispatch_token_stalls2.int_sch1_token_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 1 availablede_dis_dispatch_token_stalls2.int_sch0_token_stallCycles where a dispatch group is valid but does not get dispatched due to a token stall. No tokens for Integer Scheduler Queue 0 availableall_data_cache_accessesevent=0x60,umask=0xe8L2 Cache Misses from L2 Cache HWPFevent=0x64,umask=0xf0L2 Cache Hits from L2 Cache HWPFl3_cache_accessesL3 Cache Accesses. Unit: amd_l3 L3 Misses (includes cacheline state change requests). Unit: amd_l3 (xi_sys_fill_latency * 16) / xi_ccx_sdp_req1Op Cache (64B) Fetch Miss Ratiod_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)op_cache_fetch_miss_ratioInstruction Cache (32B) Fetch Miss Ratiod_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)l1_data_cache_fills_from_memoryevent=0x44,umask=0x48L1 Data Cache Fills: From Memoryl1_data_cache_fills_from_remote_nodeevent=0x44,umask=0x50L1 Data Cache Fills: From Remote Nodel1_data_cache_fills_from_within_same_ccxevent=0x44,umask=0x03L1 Data Cache Fills: From within same CCXl1_data_cache_fills_from_external_ccx_cacheevent=0x44,umask=0x14L1 Data Cache Fills: From External CCX Cachel1_data_cache_fills_allevent=0x44,umask=0xffL1 Data Cache Fills: Allbp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_missMacro-ops Dispatchedde_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatchmacro_ops_dispatcheddecodermacro_ops_retiredMacro-ops RetiredL2 branch prediction overrides existing prediction (speculative)Dynamic indirect predictions (branch used the indirect predictor to make a prediction)Instruction decoder corrects the predicted target and resteers the branch predictorRetired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)Retired branch instructions mispredictedRetired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)Retired taken branch instructions mispredictedRetired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch predictionRetired near returns (RET or RET Iw)Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instructionRetired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instructionRetired indirect branch instructionsRetired conditional branch instructionsRetired branch instructions mispredicted due to direction mismatchex_ret_uncond_brnch_instr_mispredevent=0x1c8Retired unconditional indirect branch instructions mispredictedex_ret_uncond_brnch_instrevent=0x1c9Retired unconditional branch instructionsMiss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocationsMiss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocationsMiss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocationsls_dmnd_fills_from_sys.local_l2Demand data cache fills from local L2 cachels_dmnd_fills_from_sys.local_ccxDemand data cache fills from L3 cache or different L2 cache in the same CCXls_dmnd_fills_from_sys.near_cacheDemand data cache fills from cache of another CCX when the address was in the same NUMA nodels_dmnd_fills_from_sys.dram_io_nearDemand data cache fills from either DRAM or MMIO in the same NUMA nodels_dmnd_fills_from_sys.far_cacheDemand data cache fills from cache of another CCX when the address was in a different NUMA nodels_dmnd_fills_from_sys.dram_io_farDemand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket)ls_dmnd_fills_from_sys.alternate_memoriesevent=0x43,umask=0x80Demand data cache fills from extension memoryls_dmnd_fills_from_sys.allevent=0x43,umask=0xffDemand data cache fills from all types of data sourcesls_any_fills_from_sys.local_l2Any data cache fills from local L2 cachels_any_fills_from_sys.local_ccxAny data cache fills from L3 cache or different L2 cache in the same CCXls_any_fills_from_sys.local_allAny data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCXls_any_fills_from_sys.near_cacheAny data cache fills from cache of another CCX when the address was in the same NUMA nodels_any_fills_from_sys.dram_io_nearAny data cache fills from either DRAM or MMIO in the same NUMA nodels_any_fills_from_sys.far_cacheAny data cache fills from cache of another CCX when the address was in a different NUMA nodels_any_fills_from_sys.remote_cacheAny data cache fills from cache of another CCX when the address was in the same or a different NUMA nodels_any_fills_from_sys.dram_io_farAny data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket)ls_any_fills_from_sys.dram_io_allAny data cache fills from either DRAM or MMIO in any NUMA node (same or different socket)ls_any_fills_from_sys.far_allAny data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket)ls_any_fills_from_sys.all_dram_iols_any_fills_from_sys.alternate_memoriesevent=0x44,umask=0x80Any data cache fills from extension memoryls_any_fills_from_sys.allAny data cache fills from all types of data sourcesSoftware prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2)Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable)Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access)ls_pref_instr_disp.allevent=0x4b,umask=0x07Software prefetch instructions dispatched (speculative) of all typesSoftware prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hitSoftware prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB)ls_inef_sw_pref.allevent=0x52,umask=0x03ls_sw_pf_dc_fills.local_l2Software prefetch data cache fills from local L2 cachels_sw_pf_dc_fills.local_ccxSoftware prefetch data cache fills from L3 cache or different L2 cache in the same CCXls_sw_pf_dc_fills.near_cacheSoftware prefetch data cache fills from cache of another CCX in the same NUMA nodels_sw_pf_dc_fills.dram_io_nearSoftware prefetch data cache fills from either DRAM or MMIO in the same NUMA nodels_sw_pf_dc_fills.far_cacheSoftware prefetch data cache fills from cache of another CCX in a different NUMA nodels_sw_pf_dc_fills.dram_io_farSoftware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket)ls_sw_pf_dc_fills.alternate_memoriesevent=0x59,umask=0x80Software prefetch data cache fills from extension memoryls_sw_pf_dc_fills.allevent=0x59,umask=0xdfSoftware prefetch data cache fills from all types of data sourcesls_hw_pf_dc_fills.local_l2Hardware prefetch data cache fills from local L2 cachels_hw_pf_dc_fills.local_ccxHardware prefetch data cache fills from L3 cache or different L2 cache in the same CCXls_hw_pf_dc_fills.near_cacheHardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA nodels_hw_pf_dc_fills.dram_io_nearHardware prefetch data cache fills from either DRAM or MMIO in the same NUMA nodels_hw_pf_dc_fills.far_cacheHardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA nodels_hw_pf_dc_fills.dram_io_farHardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket)ls_hw_pf_dc_fills.alternate_memoriesevent=0x5a,umask=0x80Hardware prefetch data cache fills from extension memoryls_hw_pf_dc_fills.allevent=0x5a,umask=0xdfHardware prefetch data cache fills from all types of data sourcesIn-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycleL2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks)L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss)L2 cache requests: prefetch directly into L2L2 cache requests: data cache state change to writable, check L2 for current stateL2 cache requests: instruction cache readsL2 cache requests: data cache shared readsL2 cache requests: data cache storesL2 cache requests: data cache reads including hardware and software prefetchl2_request_g1.all_dcL2 cache requests of common types from L1 data cache (including prefetches)L2 cache requests of common types not including prefetchesl2_request_g1.allevent=0x60,umask=0xffL2 cache requests of all typesCore to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2l2_cache_req_stat.ic_hit_in_l2Core to L2 cache requests (not including L2 prefetch) for instruction cache hitsCore to L2 cache requests (not including L2 prefetch) for instruction cache accessCore to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2Core to L2 cache requests (not including L2 prefetch) for data and instruction cache missesCore to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2l2_cache_req_stat.dc_hit_in_l2Core to L2 cache requests (not including L2 prefetch) for data cache hitsCore to L2 cache requests (not including L2 prefetch) for data and instruction cache hitsl2_cache_req_stat.dc_access_in_l2event=0x64,umask=0xf8Core to L2 cache requests (not including L2 prefetch) for data cache accessl2_cache_req_stat.allevent=0x64,umask=0xffCore to L2 cache requests (not including L2 prefetch) for data and instruction cache accessl2_pf_hit_l2.l2_streamevent=0x70,umask=0x01L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fetch additional sequential lines into L2 cache)l2_pf_hit_l2.l2_next_lineevent=0x70,umask=0x02L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2NextLine (fetch the next line into L2 cache)l2_pf_hit_l2.l2_up_downevent=0x70,umask=0x04L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses)l2_pf_hit_l2.l2_burstevent=0x70,umask=0x08L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache)l2_pf_hit_l2.l2_strideevent=0x70,umask=0x10L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines into L2 cache when each access is at a constant distance from the previous)l2_pf_hit_l2.l1_streamevent=0x70,umask=0x20L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fetch additional sequential lines into L1 cache)l2_pf_hit_l2.l1_strideevent=0x70,umask=0x40L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous)l2_pf_hit_l2.l1_regionevent=0x70,umask=0x80L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region)l2_pf_hit_l2.allL2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all typesl2_pf_miss_l2_hit_l3.l2_streamevent=0x71,umask=0x01L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stream (fetch additional sequential lines into L2 cache)l2_pf_miss_l2_hit_l3.l2_next_lineevent=0x71,umask=0x02L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2NextLine (fetch the next line into L2 cache)l2_pf_miss_l2_hit_l3.l2_up_downevent=0x71,umask=0x04L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses)l2_pf_miss_l2_hit_l3.l2_burstevent=0x71,umask=0x08L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache)l2_pf_miss_l2_hit_l3.l2_strideevent=0x71,umask=0x10L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous)l2_pf_miss_l2_hit_l3.l1_streamevent=0x71,umask=0x20L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stream (fetch additional sequential lines into L1 cache)l2_pf_miss_l2_hit_l3.l1_strideevent=0x71,umask=0x40L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous)l2_pf_miss_l2_hit_l3.l1_regionevent=0x71,umask=0x80L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region)l2_pf_miss_l2_hit_l3.allL2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache cache of all typesl2_pf_miss_l2_l3.l2_streamevent=0x72,umask=0x01L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stream (fetch additional sequential lines into L2 cache)l2_pf_miss_l2_l3.l2_next_lineevent=0x72,umask=0x02L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2NextLine (fetch the next line into L2 cache)l2_pf_miss_l2_l3.l2_up_downevent=0x72,umask=0x04L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses)l2_pf_miss_l2_l3.l2_burstevent=0x72,umask=0x08L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (aggressively fetch additional sequential lines into L2 cache)l2_pf_miss_l2_l3.l2_strideevent=0x72,umask=0x10L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous)l2_pf_miss_l2_l3.l1_streamevent=0x72,umask=0x20L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stream (fetch additional sequential lines into L1 cache)l2_pf_miss_l2_l3.l1_strideevent=0x72,umask=0x40L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous)l2_pf_miss_l2_l3.l1_regionevent=0x72,umask=0x80L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region)l2_pf_miss_l2_l3.allL2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of all typesInstruction cache lines (64 bytes) fulfilled from the L2 cacheInstruction cache lines (64 bytes) fulfilled from system memory or another cacheInstruction cache hitsInstruction cache missesInstruction cache accesses of all typesOp cache hitsOp cache missesOp cache accesses of all typesl3_lookup_state.l3_missl3_lookup_state.l3_hitevent=0x4,umask=0xfeL3 cache hits. Unit: amd_l3 l3_lookup_state.all_coherent_accesses_to_l3L3 cache requests for all coherent accesses. Unit: amd_l3 l3_xi_sampled_latency.dram_nearevent=0xac,umask=0x01Average sampled latency when data is sourced from DRAM in the same NUMA node. Unit: amd_l3 l3_xi_sampled_latency.dram_farevent=0xac,umask=0x02Average sampled latency when data is sourced from DRAM in a different NUMA node. Unit: amd_l3 l3_xi_sampled_latency.near_cacheevent=0xac,umask=0x04Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node. Unit: amd_l3 l3_xi_sampled_latency.far_cacheevent=0xac,umask=0x08Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node. Unit: amd_l3 l3_xi_sampled_latency.ext_nearevent=0xac,umask=0x10Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node. Unit: amd_l3 l3_xi_sampled_latency.ext_farevent=0xac,umask=0x20Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node. Unit: amd_l3 l3_xi_sampled_latency.allevent=0xac,umask=0x3fAverage sampled latency from all data sources. Unit: amd_l3 l3_xi_sampled_latency_requests.dram_nearevent=0xad,umask=0x01L3 cache fill requests sourced from DRAM in the same NUMA node. Unit: amd_l3 l3_xi_sampled_latency_requests.dram_farevent=0xad,umask=0x02L3 cache fill requests sourced from DRAM in a different NUMA node. Unit: amd_l3 l3_xi_sampled_latency_requests.near_cacheevent=0xad,umask=0x04L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node. Unit: amd_l3 l3_xi_sampled_latency_requests.far_cacheevent=0xad,umask=0x08L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node. Unit: amd_l3 l3_xi_sampled_latency_requests.ext_nearevent=0xad,umask=0x10L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node. Unit: amd_l3 l3_xi_sampled_latency_requests.ext_farevent=0xad,umask=0x20L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node. Unit: amd_l3 l3_xi_sampled_latency_requests.allevent=0xad,umask=0x3fL3 cache fill requests sourced from all data sources. Unit: amd_l3 Retired Lock instructions which caused a bus lockRetired CLFLUSH instructionsRetired CPUID instructionsSMIs receivedInterrupts takenCore cycles not in haltRetired instructionsRetired macro-opsNumber of cycles the divider is busyDivide ops executedex_no_retire.emptyevent=0xd6,umask=0x01Cycles with no retire due  to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects)ex_no_retire.not_completeevent=0xd6,umask=0x02Cycles with no retire while the oldest op is waiting to be executedex_no_retire.otherevent=0xd6,umask=0x08Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.)ex_no_retire.thread_not_selectedevent=0xd6,umask=0x10Cycles with no retire because thread arbitration did not select the threadex_no_retire.load_not_completeevent=0xd6,umask=0xa2Cycles with no retire while the oldest op is waiting for load dataex_no_retire.allevent=0xd6,umask=0x1bCycles with no retire for any reasonls_not_halted_p0_cyc.p0_freq_cycevent=0x120,umask=0x1Reference cycles (P0 frequency) not in halt ex_ret_ucode_instrevent=0x1c1Retired microcoded instructionsex_ret_ucode_opsevent=0x1c2Retired microcode opsOps tagged by IBSOps tagged by IBS that retiredRetired fused instructionslocal_processor_read_data_beats_cs0event=0x1f,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 0local_processor_read_data_beats_cs1event=0x5f,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 1local_processor_read_data_beats_cs2event=0x9f,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 2local_processor_read_data_beats_cs3event=0xdf,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 3local_processor_read_data_beats_cs4event=0x11f,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 4local_processor_read_data_beats_cs5event=0x15f,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 5local_processor_read_data_beats_cs6event=0x19f,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 6local_processor_read_data_beats_cs7event=0x1df,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 7local_processor_read_data_beats_cs8event=0x21f,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 8local_processor_read_data_beats_cs9event=0x25f,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 9local_processor_read_data_beats_cs10event=0x29f,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 10local_processor_read_data_beats_cs11event=0x2df,umask=0x7feRead data beats (64 bytes) for local processor at Coherent Station (CS) 11local_processor_write_data_beats_cs0event=0x1f,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 0local_processor_write_data_beats_cs1event=0x5f,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 1local_processor_write_data_beats_cs2event=0x9f,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 2local_processor_write_data_beats_cs3event=0xdf,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 3local_processor_write_data_beats_cs4event=0x11f,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 4local_processor_write_data_beats_cs5event=0x15f,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 5local_processor_write_data_beats_cs6event=0x19f,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 6local_processor_write_data_beats_cs7event=0x1df,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 7local_processor_write_data_beats_cs8event=0x21f,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 8local_processor_write_data_beats_cs9event=0x25f,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 9local_processor_write_data_beats_cs10event=0x29f,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 10local_processor_write_data_beats_cs11event=0x2df,umask=0x7ffWrite data beats (64 bytes) for local processor at Coherent Station (CS) 11remote_processor_read_data_beats_cs0event=0x1f,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 0remote_processor_read_data_beats_cs1event=0x5f,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 1remote_processor_read_data_beats_cs2event=0x9f,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 2remote_processor_read_data_beats_cs3event=0xdf,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 3remote_processor_read_data_beats_cs4event=0x11f,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 4remote_processor_read_data_beats_cs5event=0x15f,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 5remote_processor_read_data_beats_cs6event=0x19f,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 6remote_processor_read_data_beats_cs7event=0x1df,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 7remote_processor_read_data_beats_cs8event=0x21f,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 8remote_processor_read_data_beats_cs9event=0x25f,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 9remote_processor_read_data_beats_cs10event=0x29f,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 10remote_processor_read_data_beats_cs11event=0x2df,umask=0xbfeRead data beats (64 bytes) for remote processor at Coherent Station (CS) 11remote_processor_write_data_beats_cs0event=0x1f,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 0remote_processor_write_data_beats_cs1event=0x5f,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 1remote_processor_write_data_beats_cs2event=0x9f,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 2remote_processor_write_data_beats_cs3event=0xdf,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 3remote_processor_write_data_beats_cs4event=0x11f,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 4remote_processor_write_data_beats_cs5event=0x15f,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 5remote_processor_write_data_beats_cs6event=0x19f,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 6remote_processor_write_data_beats_cs7event=0x1df,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 7remote_processor_write_data_beats_cs8event=0x21f,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 8remote_processor_write_data_beats_cs9event=0x25f,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 9remote_processor_write_data_beats_cs10event=0x29f,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 10remote_processor_write_data_beats_cs11event=0x2df,umask=0xbffWrite data beats (64 bytes) for remote processor at Coherent Station (CS) 11local_socket_upstream_read_beats_iom0event=0x81f,umask=0x7feRead data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0local_socket_upstream_read_beats_iom1event=0x85f,umask=0x7feRead data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1local_socket_upstream_read_beats_iom2event=0x89f,umask=0x7feRead data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2local_socket_upstream_read_beats_iom3event=0x8df,umask=0x7feRead data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3local_socket_upstream_write_beats_iom0event=0x81f,umask=0x7ffWrite data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 0local_socket_upstream_write_beats_iom1event=0x85f,umask=0x7ffWrite data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 1local_socket_upstream_write_beats_iom2event=0x89f,umask=0x7ffWrite data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 2local_socket_upstream_write_beats_iom3event=0x8df,umask=0x7ffWrite data beats (64 bytes) for local socket upstream DMA at IO Moderator (IOM) 3remote_socket_upstream_read_beats_iom0event=0x81f,umask=0xbfeRead data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0remote_socket_upstream_read_beats_iom1event=0x85f,umask=0xbfeRead data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1remote_socket_upstream_read_beats_iom2event=0x89f,umask=0xbfeRead data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2remote_socket_upstream_read_beats_iom3event=0x8df,umask=0xbfeRead data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3remote_socket_upstream_write_beats_iom0event=0x81f,umask=0xbffWrite data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 0remote_socket_upstream_write_beats_iom1event=0x85f,umask=0xbffWrite data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 1remote_socket_upstream_write_beats_iom2event=0x89f,umask=0xbffWrite data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 2remote_socket_upstream_write_beats_iom3event=0x8df,umask=0xbffWrite data beats (64 bytes) for remote socket upstream DMA at IO Moderator (IOM) 3local_socket_inf0_inbound_data_beats_ccm0event=0x41e,umask=0x7feData beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 0local_socket_inf0_inbound_data_beats_ccm1event=0x45e,umask=0x7feData beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 1local_socket_inf0_inbound_data_beats_ccm2event=0x49e,umask=0x7feData beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 2local_socket_inf0_inbound_data_beats_ccm3event=0x4de,umask=0x7feData beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 3local_socket_inf0_inbound_data_beats_ccm4event=0x51e,umask=0x7feData beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 4local_socket_inf0_inbound_data_beats_ccm5event=0x55e,umask=0x7feData beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 5local_socket_inf0_inbound_data_beats_ccm6event=0x59e,umask=0x7feData beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 6local_socket_inf0_inbound_data_beats_ccm7event=0x5de,umask=0x7feData beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 7local_socket_inf1_inbound_data_beats_ccm0event=0x41f,umask=0x7feData beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 0local_socket_inf1_inbound_data_beats_ccm1event=0x45f,umask=0x7feData beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 1local_socket_inf1_inbound_data_beats_ccm2event=0x49f,umask=0x7feData beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 2local_socket_inf1_inbound_data_beats_ccm3event=0x4df,umask=0x7feData beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 3local_socket_inf1_inbound_data_beats_ccm4event=0x51f,umask=0x7feData beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 4local_socket_inf1_inbound_data_beats_ccm5event=0x55f,umask=0x7feData beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 5local_socket_inf1_inbound_data_beats_ccm6event=0x59f,umask=0x7feData beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 6local_socket_inf1_inbound_data_beats_ccm7event=0x5df,umask=0x7feData beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 7local_socket_inf0_outbound_data_beats_ccm0event=0x41e,umask=0x7ffData beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 0local_socket_inf0_outbound_data_beats_ccm1event=0x45e,umask=0x7ffData beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 1local_socket_inf0_outbound_data_beats_ccm2event=0x49e,umask=0x7ffData beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 2local_socket_inf0_outbound_data_beats_ccm3event=0x4de,umask=0x7ffData beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 3local_socket_inf0_outbound_data_beats_ccm4event=0x51e,umask=0x7ffData beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 4local_socket_inf0_outbound_data_beats_ccm5event=0x55e,umask=0x7ffData beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 5local_socket_inf0_outbound_data_beats_ccm6event=0x59e,umask=0x7ffData beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 6local_socket_inf0_outbound_data_beats_ccm7event=0x5de,umask=0x7ffData beats (64 bytes) at interface 0 for local socket outbound data from CPU Moderator (CCM) 7local_socket_inf1_outbound_data_beats_ccm0event=0x41f,umask=0x7ffData beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 0local_socket_inf1_outbound_data_beats_ccm1event=0x45f,umask=0x7ffData beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 1local_socket_inf1_outbound_data_beats_ccm2event=0x49f,umask=0x7ffData beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 2local_socket_inf1_outbound_data_beats_ccm3event=0x4df,umask=0x7ffData beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 3local_socket_inf1_outbound_data_beats_ccm4event=0x51f,umask=0x7ffData beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 4local_socket_inf1_outbound_data_beats_ccm5event=0x55f,umask=0x7ffData beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 5local_socket_inf1_outbound_data_beats_ccm6event=0x59f,umask=0x7ffData beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 6local_socket_inf1_outbound_data_beats_ccm7event=0x5df,umask=0x7ffData beats (64 bytes) at interface 1 for local socket outbound data from CPU Moderator (CCM) 7remote_socket_inf0_inbound_data_beats_ccm0event=0x41e,umask=0xbfeData beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 0remote_socket_inf0_inbound_data_beats_ccm1event=0x45e,umask=0xbfeData beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 1remote_socket_inf0_inbound_data_beats_ccm2event=0x49e,umask=0xbfeData beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 2remote_socket_inf0_inbound_data_beats_ccm3event=0x4de,umask=0xbfeData beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 3remote_socket_inf0_inbound_data_beats_ccm4event=0x51e,umask=0xbfeData beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 4remote_socket_inf0_inbound_data_beats_ccm5event=0x55e,umask=0xbfeData beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 5remote_socket_inf0_inbound_data_beats_ccm6event=0x59e,umask=0xbfeData beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 6remote_socket_inf0_inbound_data_beats_ccm7event=0x5de,umask=0xbfeData beats (32 bytes) at interface 0 for remote socket inbound data to CPU Moderator (CCM) 7remote_socket_inf1_inbound_data_beats_ccm0event=0x41f,umask=0xbfeData beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 0remote_socket_inf1_inbound_data_beats_ccm1event=0x45f,umask=0xbfeData beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 1remote_socket_inf1_inbound_data_beats_ccm2event=0x49f,umask=0xbfeData beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 2remote_socket_inf1_inbound_data_beats_ccm3event=0x4df,umask=0xbfeData beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 3remote_socket_inf1_inbound_data_beats_ccm4event=0x51f,umask=0xbfeData beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 4remote_socket_inf1_inbound_data_beats_ccm5event=0x55f,umask=0xbfeData beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 5remote_socket_inf1_inbound_data_beats_ccm6event=0x59f,umask=0xbfeData beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 6remote_socket_inf1_inbound_data_beats_ccm7event=0x5df,umask=0xbfeData beats (32 bytes) at interface 1 for remote socket inbound data to CPU Moderator (CCM) 7remote_socket_inf0_outbound_data_beats_ccm0event=0x41e,umask=0xbffData beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 0remote_socket_inf0_outbound_data_beats_ccm1event=0x45e,umask=0xbffData beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 1remote_socket_inf0_outbound_data_beats_ccm2event=0x49e,umask=0xbffData beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 2remote_socket_inf0_outbound_data_beats_ccm3event=0x4de,umask=0xbffData beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 3remote_socket_inf0_outbound_data_beats_ccm4event=0x51e,umask=0xbffData beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 4remote_socket_inf0_outbound_data_beats_ccm5event=0x55e,umask=0xbffData beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 5remote_socket_inf0_outbound_data_beats_ccm6event=0x59e,umask=0xbffData beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 6remote_socket_inf0_outbound_data_beats_ccm7event=0x5de,umask=0xbffData beats (64 bytes) at interface 0 for remote socket outbound data from CPU Moderator (CCM) 7remote_socket_inf1_outbound_data_beats_ccm0event=0x41f,umask=0xbffData beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 0remote_socket_inf1_outbound_data_beats_ccm1event=0x45f,umask=0xbffData beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 1remote_socket_inf1_outbound_data_beats_ccm2event=0x49f,umask=0xbffData beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 2remote_socket_inf1_outbound_data_beats_ccm3event=0x4df,umask=0xbffData beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 3remote_socket_inf1_outbound_data_beats_ccm4event=0x51f,umask=0xbffData beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 4remote_socket_inf1_outbound_data_beats_ccm5event=0x55f,umask=0xbffData beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 5remote_socket_inf1_outbound_data_beats_ccm6event=0x59f,umask=0xbffData beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 6remote_socket_inf1_outbound_data_beats_ccm7event=0x5df,umask=0xbffData beats (64 bytes) at interface 1 for remote socket outbound data from CPU Moderator (CCM) 7local_socket_outbound_data_beats_link0event=0xb5f,umask=0xf3eData beats (64 bytes) for local socket outbound data from inter-socket xGMI link 0local_socket_outbound_data_beats_link1event=0xb9f,umask=0xf3eData beats (64 bytes) for local socket outbound data from inter-socket xGMI link 1local_socket_outbound_data_beats_link2event=0xbdf,umask=0xf3eData beats (64 bytes) for local socket outbound data from inter-socket xGMI link 2local_socket_outbound_data_beats_link3event=0xc1f,umask=0xf3eData beats (64 bytes) for local socket outbound data from inter-socket xGMI link 3local_socket_outbound_data_beats_link4event=0xc5f,umask=0xf3eData beats (64 bytes) for local socket outbound data from inter-socket xGMI link 4local_socket_outbound_data_beats_link5event=0xc9f,umask=0xf3eData beats (64 bytes) for local socket outbound data from inter-socket xGMI link 5local_socket_outbound_data_beats_link6event=0xcdf,umask=0xf3eData beats (64 bytes) for local socket outbound data from inter-socket xGMI link 6local_socket_outbound_data_beats_link7event=0xd1f,umask=0xf3eData beats (64 bytes) for local socket outbound data from inter-socket xGMI link 7fp_ret_x87_fp_ops.add_sub_opsRetired x87 floating-point add and subtract opsfp_ret_x87_fp_ops.mul_opsRetired x87 floating-point multiply opsfp_ret_x87_fp_ops.div_sqrt_opsRetired x87 floating-point divide and square root opsfp_ret_x87_fp_ops.allRetired x87 floating-point ops of all typesRetired SSE and AVX floating-point add and subtract opsRetired SSE and AVX floating-point multiply opsRetired SSE and AVX floating-point divide and square root opsRetired SSE and AVX floating-point multiply-accumulate ops (each operation is counted as 2 ops)fp_ret_sse_avx_ops.bfloat_mac_flopsRetired SSE and AVX floating-point bfloat multiply-accumulate ops (each operation is counted as 2 ops)event=0x3,umask=0x1fRetired SSE and AVX floating-point ops of all typesRetired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in exception mask bitsRetired x87 bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executingRetired SSE and AVX control word mispredict trapsRetired SSE and AVX bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executingfp_retired_ser_ops.allevent=0x5,umask=0x0fRetired SSE and AVX serializing ops of all typesfp_ops_retired_by_width.x87_uops_retiredevent=0x8,umask=0x01Retired x87 floating-point opsfp_ops_retired_by_width.mmx_uops_retiredevent=0x8,umask=0x02Retired MMX floating-point opsfp_ops_retired_by_width.scalar_uops_retiredevent=0x8,umask=0x04Retired scalar floating-point opsfp_ops_retired_by_width.pack_128_uops_retiredevent=0x8,umask=0x08Retired packed 128-bit floating-point opsfp_ops_retired_by_width.pack_256_uops_retiredevent=0x8,umask=0x10Retired packed 256-bit floating-point opsfp_ops_retired_by_width.pack_512_uops_retiredevent=0x8,umask=0x20Retired packed 512-bit floating-point opsfp_ops_retired_by_width.allevent=0x8,umask=0x3fRetired floating-point ops of all widthsfp_ops_retired_by_type.scalar_addevent=0xa,umask=0x01Retired scalar floating-point add opsfp_ops_retired_by_type.scalar_subevent=0xa,umask=0x02Retired scalar floating-point subtract opsfp_ops_retired_by_type.scalar_mulevent=0xa,umask=0x03Retired scalar floating-point multiply opsfp_ops_retired_by_type.scalar_macevent=0xa,umask=0x04Retired scalar floating-point multiply-accumulate opsfp_ops_retired_by_type.scalar_divevent=0xa,umask=0x05Retired scalar floating-point divide opsfp_ops_retired_by_type.scalar_sqrtevent=0xa,umask=0x06Retired scalar floating-point square root opsfp_ops_retired_by_type.scalar_cmpevent=0xa,umask=0x07Retired scalar floating-point compare opsfp_ops_retired_by_type.scalar_cvtevent=0xa,umask=0x08Retired scalar floating-point convert opsfp_ops_retired_by_type.scalar_blendevent=0xa,umask=0x09Retired scalar floating-point blend opsfp_ops_retired_by_type.scalar_otherevent=0xa,umask=0x0eRetired scalar floating-point ops of other typesfp_ops_retired_by_type.scalar_allevent=0xa,umask=0x0fRetired scalar floating-point ops of all typesfp_ops_retired_by_type.vector_addevent=0xa,umask=0x10Retired vector floating-point add opsfp_ops_retired_by_type.vector_subevent=0xa,umask=0x20Retired vector floating-point subtract opsfp_ops_retired_by_type.vector_mulevent=0xa,umask=0x30Retired vector floating-point multiply opsfp_ops_retired_by_type.vector_macevent=0xa,umask=0x40Retired vector floating-point multiply-accumulate opsfp_ops_retired_by_type.vector_divevent=0xa,umask=0x50Retired vector floating-point divide opsfp_ops_retired_by_type.vector_sqrtevent=0xa,umask=0x60Retired vector floating-point square root opsfp_ops_retired_by_type.vector_cmpevent=0xa,umask=0x70Retired vector floating-point compare opsfp_ops_retired_by_type.vector_cvtevent=0xa,umask=0x80Retired vector floating-point convert opsfp_ops_retired_by_type.vector_blendevent=0xa,umask=0x90Retired vector floating-point blend opsfp_ops_retired_by_type.vector_shuffleevent=0xa,umask=0xb0Retired vector floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions)fp_ops_retired_by_type.vector_logicalevent=0xa,umask=0xd0Retired vector floating-point logical opsfp_ops_retired_by_type.vector_otherevent=0xa,umask=0xe0Retired vector floating-point ops of other typesfp_ops_retired_by_type.vector_allevent=0xa,umask=0xf0Retired vector floating-point ops of all typesfp_ops_retired_by_type.allevent=0xa,umask=0xffRetired floating-point ops of all typessse_avx_ops_retired.mmx_addevent=0xb,umask=0x01Retired MMX integer addsse_avx_ops_retired.mmx_subevent=0xb,umask=0x02Retired MMX integer subtract opssse_avx_ops_retired.mmx_mulevent=0xb,umask=0x03Retired MMX integer multiply opssse_avx_ops_retired.mmx_macevent=0xb,umask=0x04Retired MMX integer multiply-accumulate opssse_avx_ops_retired.mmx_cmpevent=0xb,umask=0x07Retired MMX integer compare opssse_avx_ops_retired.mmx_shiftevent=0xb,umask=0x09Retired MMX integer shift opssse_avx_ops_retired.mmx_movevent=0xb,umask=0x0aRetired MMX integer MOV opssse_avx_ops_retired.mmx_shuffleevent=0xb,umask=0x0bRetired MMX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions)sse_avx_ops_retired.mmx_packevent=0xb,umask=0x0cRetired MMX integer pack opssse_avx_ops_retired.mmx_logicalevent=0xb,umask=0x0dRetired MMX integer logical opssse_avx_ops_retired.mmx_otherevent=0xb,umask=0x0eRetired MMX integer multiply ops of other typessse_avx_ops_retired.mmx_allevent=0xb,umask=0x0fRetired MMX integer ops of all typessse_avx_ops_retired.sse_avx_addevent=0xb,umask=0x10Retired SSE and AVX integer add opssse_avx_ops_retired.sse_avx_subevent=0xb,umask=0x20Retired SSE and AVX integer subtract opssse_avx_ops_retired.sse_avx_mulevent=0xb,umask=0x30Retired SSE and AVX integer multiply opssse_avx_ops_retired.sse_avx_macevent=0xb,umask=0x40Retired SSE and AVX integer multiply-accumulate opssse_avx_ops_retired.sse_avx_aesevent=0xb,umask=0x50Retired SSE and AVX integer AES opssse_avx_ops_retired.sse_avx_shaevent=0xb,umask=0x60Retired SSE and AVX integer SHA opssse_avx_ops_retired.sse_avx_cmpevent=0xb,umask=0x70Retired SSE and AVX integer compare opssse_avx_ops_retired.sse_avx_clmevent=0xb,umask=0x80Retired SSE and AVX integer CLM opssse_avx_ops_retired.sse_avx_shiftevent=0xb,umask=0x90Retired SSE and AVX integer shift opssse_avx_ops_retired.sse_avx_movevent=0xb,umask=0xa0Retired SSE and AVX integer MOV opssse_avx_ops_retired.sse_avx_shuffleevent=0xb,umask=0xb0Retired SSE and AVX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions)sse_avx_ops_retired.sse_avx_packevent=0xb,umask=0xc0Retired SSE and AVX integer pack opssse_avx_ops_retired.sse_avx_logicalevent=0xb,umask=0xd0Retired SSE and AVX integer logical opssse_avx_ops_retired.sse_avx_otherevent=0xb,umask=0xe0Retired SSE and AVX integer ops of other typessse_avx_ops_retired.sse_avx_allevent=0xb,umask=0xf0Retired SSE and AVX integer ops of all typessse_avx_ops_retired.allevent=0xb,umask=0xffRetired SSE, AVX and MMX integer ops of all typesfp_pack_ops_retired.fp128_addevent=0xc,umask=0x01Retired 128-bit packed floating-point add opsfp_pack_ops_retired.fp128_subevent=0xc,umask=0x02Retired 128-bit packed floating-point subtract opsfp_pack_ops_retired.fp128_mulevent=0xc,umask=0x03Retired 128-bit packed floating-point multiply opsfp_pack_ops_retired.fp128_macevent=0xc,umask=0x04Retired 128-bit packed floating-point multiply-accumulate opsfp_pack_ops_retired.fp128_divevent=0xc,umask=0x05Retired 128-bit packed floating-point divide opsfp_pack_ops_retired.fp128_sqrtevent=0xc,umask=0x06Retired 128-bit packed floating-point square root opsfp_pack_ops_retired.fp128_cmpevent=0xc,umask=0x07Retired 128-bit packed floating-point compare opsfp_pack_ops_retired.fp128_cvtevent=0xc,umask=0x08Retired 128-bit packed floating-point convert opsfp_pack_ops_retired.fp128_blendevent=0xc,umask=0x09Retired 128-bit packed floating-point blend opsfp_pack_ops_retired.fp128_shuffleevent=0xc,umask=0x0bRetired 128-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions)fp_pack_ops_retired.fp128_logicalevent=0xc,umask=0x0dRetired 128-bit packed floating-point logical opsfp_pack_ops_retired.fp128_otherevent=0xc,umask=0x0eRetired 128-bit packed floating-point ops of other typesfp_pack_ops_retired.fp128_allevent=0xc,umask=0x0fRetired 128-bit packed floating-point ops of all typesfp_pack_ops_retired.fp256_addevent=0xc,umask=0x10Retired 256-bit packed floating-point add opsfp_pack_ops_retired.fp256_subevent=0xc,umask=0x20Retired 256-bit packed floating-point subtract opsfp_pack_ops_retired.fp256_mulevent=0xc,umask=0x30Retired 256-bit packed floating-point multiply opsfp_pack_ops_retired.fp256_macevent=0xc,umask=0x40Retired 256-bit packed floating-point multiply-accumulate opsfp_pack_ops_retired.fp256_divevent=0xc,umask=0x50Retired 256-bit packed floating-point divide opsfp_pack_ops_retired.fp256_sqrtevent=0xc,umask=0x60Retired 256-bit packed floating-point square root opsfp_pack_ops_retired.fp256_cmpevent=0xc,umask=0x70Retired 256-bit packed floating-point compare opsfp_pack_ops_retired.fp256_cvtevent=0xc,umask=0x80Retired 256-bit packed floating-point convert opsfp_pack_ops_retired.fp256_blendevent=0xc,umask=0x90Retired 256-bit packed floating-point blend opsfp_pack_ops_retired.fp256_shuffleevent=0xc,umask=0xb0Retired 256-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions)fp_pack_ops_retired.fp256_logicalevent=0xc,umask=0xd0Retired 256-bit packed floating-point logical opsfp_pack_ops_retired.fp256_otherevent=0xc,umask=0xe0Retired 256-bit packed floating-point ops of other typesfp_pack_ops_retired.fp256_allevent=0xc,umask=0xf0Retired 256-bit packed floating-point ops of all typesfp_pack_ops_retired.allevent=0xc,umask=0xffRetired packed floating-point ops of all typespacked_int_op_type.int128_addevent=0xd,umask=0x01Retired 128-bit packed integer add opspacked_int_op_type.int128_subevent=0xd,umask=0x02Retired 128-bit packed integer subtract opspacked_int_op_type.int128_mulevent=0xd,umask=0x03Retired 128-bit packed integer multiply opspacked_int_op_type.int128_macevent=0xd,umask=0x04Retired 128-bit packed integer multiply-accumulate opspacked_int_op_type.int128_aesevent=0xd,umask=0x05Retired 128-bit packed integer AES opspacked_int_op_type.int128_shaevent=0xd,umask=0x06Retired 128-bit packed integer SHA opspacked_int_op_type.int128_cmpevent=0xd,umask=0x07Retired 128-bit packed integer compare opspacked_int_op_type.int128_clmevent=0xd,umask=0x08Retired 128-bit packed integer CLM opspacked_int_op_type.int128_shiftevent=0xd,umask=0x09Retired 128-bit packed integer shift opspacked_int_op_type.int128_movevent=0xd,umask=0x0aRetired 128-bit packed integer MOV opspacked_int_op_type.int128_shuffleevent=0xd,umask=0x0bRetired 128-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions)packed_int_op_type.int128_packevent=0xd,umask=0x0cRetired 128-bit packed integer pack opspacked_int_op_type.int128_logicalevent=0xd,umask=0x0dRetired 128-bit packed integer logical opspacked_int_op_type.int128_otherevent=0xd,umask=0x0eRetired 128-bit packed integer ops of other typespacked_int_op_type.int128_allevent=0xd,umask=0x0fRetired 128-bit packed integer ops of all typespacked_int_op_type.int256_addevent=0xd,umask=0x10Retired 256-bit packed integer add opspacked_int_op_type.int256_subevent=0xd,umask=0x20Retired 256-bit packed integer subtract opspacked_int_op_type.int256_mulevent=0xd,umask=0x30Retired 256-bit packed integer multiply opspacked_int_op_type.int256_macevent=0xd,umask=0x40Retired 256-bit packed integer multiply-accumulate opspacked_int_op_type.int256_cmpevent=0xd,umask=0x70Retired 256-bit packed integer compare opspacked_int_op_type.int256_shiftevent=0xd,umask=0x90Retired 256-bit packed integer shift opspacked_int_op_type.int256_movevent=0xd,umask=0xa0Retired 256-bit packed integer MOV opspacked_int_op_type.int256_shuffleevent=0xd,umask=0xb0Retired 256-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions)packed_int_op_type.int256_packevent=0xd,umask=0xc0Retired 256-bit packed integer pack opspacked_int_op_type.int256_logicalevent=0xd,umask=0xd0Retired 256-bit packed integer logical opspacked_int_op_type.int256_otherevent=0xd,umask=0xe0Retired 256-bit packed integer ops of other typespacked_int_op_type.int256_allevent=0xd,umask=0xf0Retired 256-bit packed integer ops of all typespacked_int_op_type.allevent=0xd,umask=0xffRetired packed integer ops of all typesFloating-point dispatch faults for x87 fillsFloating-point dispatch faults for XMM fillsFloating-point dispatch faults for YMM fillsFloating-point dispatch faults for YMM spillsfp_disp_faults.sse_avx_allFloating-point dispatch faults of all types for SSE and AVX opsfp_disp_faults.allevent=0xe,umask=0x0fFloating-point dispatch faults of all typesumc_mem_clkUnit: uncore_umcpmc memory controllerNumber of memory clock cyclesuncore_umcpmcumc_act_cmd.allNumber of ACTIVATE commands sentumc_act_cmd.rdNumber of ACTIVATE commands sent for readsumc_act_cmd.wrNumber of ACTIVATE commands sent for writesumc_pchg_cmd.allNumber of PRECHARGE commands sentumc_pchg_cmd.rdNumber of PRECHARGE commands sent for readsumc_pchg_cmd.wrNumber of PRECHARGE commands sent for writesumc_cas_cmd.allNumber of CAS commands sentumc_cas_cmd.rdNumber of CAS commands sent for readsumc_cas_cmd.wrNumber of CAS commands sent for writesumc_data_slot_clks.allNumber of clocks used by the data busumc_data_slot_clks.rdNumber of clocks used by the data bus for readsumc_data_slot_clks.wrNumber of clocks used by the data bus for writesStore-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store)Number of memory load operations dispatched to the load-store unitNumber of memory store operations dispatched to the load-store unitNumber of memory load-store operations dispatched to the load-store unitStore-to-load-forward (STLF) hitsNon-cacheable store commits cancelled due to the non-cacheable commit buffer being fullL1 DTLB misses with L2 DTLB hits for 4k pagesL1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pagesL1 DTLB misses with L2 DTLB hits for 2M pagesL1 DTLB misses with L2 DTLB hits for 1G pagesL1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pagesL1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pagesL1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pagesL1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pagesls_l1_d_tlb_miss.all_l2_missL1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizesL1 DTLB misses for all page sizes64B misaligned (cacheline crossing) loads4kB misaligned (page crossing) loadsls_tlb_flush.allInstruction fetches that miss in the L1 ITLB but hit in the L2 ITLBInstruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pagesInstruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pagesInstruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pagesInstruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pagesbp_l1_tlb_miss_l2_tlb_miss.allevent=0x85,umask=0x0fInstruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizesInstruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pagesInstruction fetches that hit in the L1 ITLB for 2M pagesInstruction fetches that hit in the L1 ITLB for 1G pagesbp_l1_tlb_fetch_hit.allevent=0x94,umask=0x07Instruction fetches that hit in the L1 ITLB for all page sizesresyncs_or_nc_redirectsevent=0x96Pipeline restarts not caused by branch mispredictsde_op_queue_emptyCycles when the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enoughde_src_op_disp.decoderOps fetched from instruction cache and dispatchedde_src_op_disp.op_cacheOps fetched from op cache and dispatchedde_src_op_disp.loop_bufferevent=0xaa,umask=0x04Ops dispatched from loop bufferde_src_op_disp.allevent=0xaa,umask=0x07Ops dispatched from any sourcede_dis_ops_from_decoder.any_fp_dispatchNumber of ops dispatched to the floating-point unitde_dis_ops_from_decoder.disp_op_type.any_integer_dispatchNumber of ops dispatched to the integer execution unitNumber of cycles dispatch is stalled for integer physical register file tokensNumber of cycles dispatch is stalled for Load queue tokenNumber of cycles dispatch is stalled for store queue tokensNumber of cycles dispatch is stalled for taken branch buffer tokensNumber of cycles dispatch is stalled for floating-point register file tokensNumber of cycles dispatch is stalled for floating-point scheduler tokensNumber of cycles dispatch is stalled for floating-point flush recoveryNumber of cycles dispatch is stalled for integer scheduler queue 0 tokensNumber of cycles dispatch is stalled for integer scheduler queue 1 tokensNumber of cycles dispatch is stalled for integer scheduler queue 2 tokensNumber of cycles dispatch is stalled for integer scheduler queue 3 tokensNumber of cycles dispatch is stalled for retire queue tokensde_no_dispatch_per_slot.no_ops_from_frontendevent=0x1a0,umask=0x01In each cycle counts dispatch slots left empty because the front-end did not supply opsde_no_dispatch_per_slot.backend_stallsevent=0x1a0,umask=0x1eIn each cycle counts ops unable to dispatch because of back-end stallsde_no_dispatch_per_slot.smt_contentionevent=0x1a0,umask=0x60In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT threadTotal dispatch slots (upto 6 instructions can be dispatched in each cycle)6 * ls_not_halted_cyctotal_dispatch_slotsFraction of dispatch slots that remained unused because the frontend did not supply enough instructions/opsd_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots)frontend_boundPipelineL1Fraction of dispatched ops that did not retired_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots)bad_speculationFraction of dispatch slots that remained unused because of backend stallsd_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots)backend_boundFraction of dispatch slots that remained unused because the other thread was selectedd_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots)smt_contentionFraction of dispatch slots used by ops that retiredd_ratio(ex_ret_ops, total_dispatch_slots)retiringFraction of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses)d_ratio((6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@), total_dispatch_slots)frontend_bound_latencyPipelineL2;frontend_bound_groupFraction of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth)d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - (6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\,cmask\=0x6@), total_dispatch_slots)frontend_bound_bandwidthFraction of dispatched ops that were flushed due to branch mispredictsd_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + resyncs_or_nc_redirects)bad_speculation_mispredictsPipelineL2;bad_speculation_groupFraction of dispatched ops that were flushed due to pipeline restarts (resyncs)d_ratio(bad_speculation * resyncs_or_nc_redirects, ex_ret_brn_misp + resyncs_or_nc_redirects)bad_speculation_pipeline_restartsFraction of dispatch slots that remained unused because of stalls due to the memory subsystembackend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)backend_bound_memoryPipelineL2;backend_bound_groupFraction of dispatch slots that remained unused because of stalls not related to the memory subsystembackend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete))backend_bound_cpuFraction of dispatch slots used by fastpath ops that retiredretiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops))retiring_fastpathPipelineL2;retiring_groupFraction of dispatch slots used by microcode ops that retiredretiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops)retiring_microcodeExecution-time branch misprediction ratio (non-speculative)All data cache accessesAll L2 cache accessesl2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.allL2 cache accesses from L1 instruction cache misses (including prefetch)l2_cache_accesses_from_l1_ic_missesL2 cache accesses from L1 data cache misses (including prefetch)l2_cache_accesses_from_l1_dc_missesL2 cache accesses from L2 cache hardware prefetcherl2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.allAll L2 cache missesl2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.allL2 cache misses from L1 instruction cache missesl2_cache_misses_from_l1_ic_missL2 cache misses from L1 data cache missesl2_cache_misses_from_l1_dc_missL2 cache misses from L2 cache hardware prefetcherl2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.allAll L2 cache hitsl2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.allL2 cache hits from L1 instruction cache missesl2_cache_hits_from_l1_ic_missL2 cache hits from L1 data cache missesl2_cache_hits_from_l1_dc_missL2 cache hits from L2 cache hardware prefetcherL3 cache accessesL3 misses (including cacheline state change requests)Average L3 read miss latency (in core clocks)(l3_xi_sampled_latency.all * 10) / l3_xi_sampled_latency_requests.allOp cache miss ratio for all fetchesInstruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hitL1 data cache fills from DRAM or MMIO in any NUMA nodel1_dcacheL1 data cache fills from a different NUMA nodeL1 data cache fills from within the same CCXl1_data_cache_fills_from_same_ccxL1 data cache fills from another CCX cache in any NUMA nodel1_data_cache_fills_from_different_ccxAll L1 data cache fillsall_l1_data_cache_fillsL1 demand data cache fills from local L2 cachel1_demand_data_cache_fills_from_local_l2L1 demand data cache fills from within the same CCXl1_demand_data_cache_fills_from_same_ccxL1 demand data cache fills from another CCX cache in the same NUMA nodel1_demand_data_cache_fills_from_near_cacheL1 demand data cache fills from DRAM or MMIO in the same NUMA nodel1_demand_data_cache_fills_from_near_memoryL1 demand data cache fills from another CCX cache in a different NUMA nodel1_demand_data_cache_fills_from_far_cacheL1 demand data cache fills from DRAM or MMIO in a different NUMA nodel1_demand_data_cache_fills_from_far_memoryL1 instruction TLB missesbp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.allL2 instruction TLB misses and instruction page walksL1 data TLB missesL2 data TLB misses and data page walksAll TLBs flushedMacro-ops dispatchedMixed SSE/AVX stallsMacro-ops retiredDRAM read data for local processor6.103515625e-5MiBlocal_processor_read_data_beats_cs0 + local_processor_read_data_beats_cs1 + local_processor_read_data_beats_cs2 + local_processor_read_data_beats_cs3 + local_processor_read_data_beats_cs4 + local_processor_read_data_beats_cs5 + local_processor_read_data_beats_cs6 + local_processor_read_data_beats_cs7 + local_processor_read_data_beats_cs8 + local_processor_read_data_beats_cs9 + local_processor_read_data_beats_cs10 + local_processor_read_data_beats_cs11dram_read_data_for_local_processorDRAM write data for local processorlocal_processor_write_data_beats_cs0 + local_processor_write_data_beats_cs1 + local_processor_write_data_beats_cs2 + local_processor_write_data_beats_cs3 + local_processor_write_data_beats_cs4 + local_processor_write_data_beats_cs5 + local_processor_write_data_beats_cs6 + local_processor_write_data_beats_cs7 + local_processor_write_data_beats_cs8 + local_processor_write_data_beats_cs9 + local_processor_write_data_beats_cs10 + local_processor_write_data_beats_cs11dram_write_data_for_local_processorDRAM read data for remote processorremote_processor_read_data_beats_cs0 + remote_processor_read_data_beats_cs1 + remote_processor_read_data_beats_cs2 + remote_processor_read_data_beats_cs3 + remote_processor_read_data_beats_cs4 + remote_processor_read_data_beats_cs5 + remote_processor_read_data_beats_cs6 + remote_processor_read_data_beats_cs7 + remote_processor_read_data_beats_cs8 + remote_processor_read_data_beats_cs9 + remote_processor_read_data_beats_cs10 + remote_processor_read_data_beats_cs11dram_read_data_for_remote_processorDRAM write data for remote processorremote_processor_write_data_beats_cs0 + remote_processor_write_data_beats_cs1 + remote_processor_write_data_beats_cs2 + remote_processor_write_data_beats_cs3 + remote_processor_write_data_beats_cs4 + remote_processor_write_data_beats_cs5 + remote_processor_write_data_beats_cs6 + remote_processor_write_data_beats_cs7 + remote_processor_write_data_beats_cs8 + remote_processor_write_data_beats_cs9 + remote_processor_write_data_beats_cs10 + remote_processor_write_data_beats_cs11dram_write_data_for_remote_processorLocal socket upstream DMA read datalocal_socket_upstream_read_beats_iom0 + local_socket_upstream_read_beats_iom1 + local_socket_upstream_read_beats_iom2 + local_socket_upstream_read_beats_iom3local_socket_upstream_dma_read_dataLocal socket upstream DMA write datalocal_socket_upstream_write_beats_iom0 + local_socket_upstream_write_beats_iom1 + local_socket_upstream_write_beats_iom2 + local_socket_upstream_write_beats_iom3local_socket_upstream_dma_write_dataRemote socket upstream DMA read dataremote_socket_upstream_read_beats_iom0 + remote_socket_upstream_read_beats_iom1 + remote_socket_upstream_read_beats_iom2 + remote_socket_upstream_read_beats_iom3remote_socket_upstream_dma_read_dataRemote socket upstream DMA write dataremote_socket_upstream_write_beats_iom0 + remote_socket_upstream_write_beats_iom1 + remote_socket_upstream_write_beats_iom2 + remote_socket_upstream_write_beats_iom3remote_socket_upstream_dma_write_dataLocal socket inbound data to the CPU (e.g. read data)3.0517578125e-5MiBlocal_socket_inf0_inbound_data_beats_ccm0 + local_socket_inf1_inbound_data_beats_ccm0 + local_socket_inf0_inbound_data_beats_ccm1 + local_socket_inf1_inbound_data_beats_ccm1 + local_socket_inf0_inbound_data_beats_ccm2 + local_socket_inf1_inbound_data_beats_ccm2 + local_socket_inf0_inbound_data_beats_ccm3 + local_socket_inf1_inbound_data_beats_ccm3 + local_socket_inf0_inbound_data_beats_ccm4 + local_socket_inf1_inbound_data_beats_ccm4 + local_socket_inf0_inbound_data_beats_ccm5 + local_socket_inf1_inbound_data_beats_ccm5 + local_socket_inf0_inbound_data_beats_ccm6 + local_socket_inf1_inbound_data_beats_ccm6 + local_socket_inf0_inbound_data_beats_ccm7 + local_socket_inf1_inbound_data_beats_ccm7local_socket_inbound_data_to_cpuLocal socket outbound data from the CPU (e.g. write data)local_socket_inf0_outbound_data_beats_ccm0 + local_socket_inf1_outbound_data_beats_ccm0 + local_socket_inf0_outbound_data_beats_ccm1 + local_socket_inf1_outbound_data_beats_ccm1 + local_socket_inf0_outbound_data_beats_ccm2 + local_socket_inf1_outbound_data_beats_ccm2 + local_socket_inf0_outbound_data_beats_ccm3 + local_socket_inf1_outbound_data_beats_ccm3 + local_socket_inf0_outbound_data_beats_ccm4 + local_socket_inf1_outbound_data_beats_ccm4 + local_socket_inf0_outbound_data_beats_ccm5 + local_socket_inf1_outbound_data_beats_ccm5 + local_socket_inf0_outbound_data_beats_ccm6 + local_socket_inf1_outbound_data_beats_ccm6 + local_socket_inf0_outbound_data_beats_ccm7 + local_socket_inf1_outbound_data_beats_ccm7local_socket_outbound_data_from_cpuRemote socket inbound data to the CPU (e.g. read data)remote_socket_inf0_inbound_data_beats_ccm0 + remote_socket_inf1_inbound_data_beats_ccm0 + remote_socket_inf0_inbound_data_beats_ccm1 + remote_socket_inf1_inbound_data_beats_ccm1 + remote_socket_inf0_inbound_data_beats_ccm2 + remote_socket_inf1_inbound_data_beats_ccm2 + remote_socket_inf0_inbound_data_beats_ccm3 + remote_socket_inf1_inbound_data_beats_ccm3 + remote_socket_inf0_inbound_data_beats_ccm4 + remote_socket_inf1_inbound_data_beats_ccm4 + remote_socket_inf0_inbound_data_beats_ccm5 + remote_socket_inf1_inbound_data_beats_ccm5 + remote_socket_inf0_inbound_data_beats_ccm6 + remote_socket_inf1_inbound_data_beats_ccm6 + remote_socket_inf0_inbound_data_beats_ccm7 + remote_socket_inf1_inbound_data_beats_ccm7remote_socket_inbound_data_to_cpuRemote socket outbound data from the CPU (e.g. write data)remote_socket_inf0_outbound_data_beats_ccm0 + remote_socket_inf1_outbound_data_beats_ccm0 + remote_socket_inf0_outbound_data_beats_ccm1 + remote_socket_inf1_outbound_data_beats_ccm1 + remote_socket_inf0_outbound_data_beats_ccm2 + remote_socket_inf1_outbound_data_beats_ccm2 + remote_socket_inf0_outbound_data_beats_ccm3 + remote_socket_inf1_outbound_data_beats_ccm3 + remote_socket_inf0_outbound_data_beats_ccm4 + remote_socket_inf1_outbound_data_beats_ccm4 + remote_socket_inf0_outbound_data_beats_ccm5 + remote_socket_inf1_outbound_data_beats_ccm5 + remote_socket_inf0_outbound_data_beats_ccm6 + remote_socket_inf1_outbound_data_beats_ccm6 + remote_socket_inf0_outbound_data_beats_ccm7 + remote_socket_inf1_outbound_data_beats_ccm7remote_socket_outbound_data_from_cpuOutbound data from all links (local socket)local_socket_outbound_data_beats_link0 + local_socket_outbound_data_beats_link1 + local_socket_outbound_data_beats_link2 + local_socket_outbound_data_beats_link3 + local_socket_outbound_data_beats_link4 + local_socket_outbound_data_beats_link5 + local_socket_outbound_data_beats_link6 + local_socket_outbound_data_beats_link7local_socket_outbound_data_from_all_linksMemory controller data bus utilizationd_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)umc_data_bus_utilizationmemory_controllerMemory controller CAS command rated_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)umc_cas_cmd_rateRatio of memory controller CAS commands for readsd_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)umc_cas_cmd_read_ratioRatio of memory controller CAS commands for writesd_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)umc_cas_cmd_write_ratioEstimated memory read bandwidth1MB/s(umc_cas_cmd.rd * 64) / 1e6 / duration_timeumc_mem_read_bandwidthEstimated memory write bandwidth(umc_cas_cmd.wr * 64) / 1e6 / duration_timeumc_mem_write_bandwidthEstimated combined memory bandwidth(umc_cas_cmd.all * 64) / 1e6 / duration_timeumc_mem_bandwidthMemory controller ACTIVATE command rated_ratio(umc_act_cmd.all * 1000, umc_mem_clk)umc_activate_cmd_rateMemory controller PRECHARGE command rated_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)umc_precharge_cmd_ratel3_cache_rdL3 cache access, readAttributable Level 3 cache access, readuncore_hisi_ddrc.flux_wcmdDDRC write commands. Unit: hisi_sccl,ddrc DDRC write commandshisi_sccl,ddrcevent-hyphenevent=0xe0,umask=0x00UNC_CBO_HYPHEN. Unit: uncore_cbox UNC_CBO_HYPHENevent-two-hyphevent=0xc0,umask=0x00UNC_CBO_TWO_HYPH. Unit: uncore_cbox UNC_CBO_TWO_HYPHuncore_hisi_l3c.rd_hit_cpipeTotal read hits. Unit: hisi_sccl,l3c Total read hitshisi_sccl,l3cuncore_imc_free_running.cache_missevent=0x12Total cache misses. Unit: uncore_imc_free_running Total cache missesuncore_imc_free_runninguncore_imc.cache_hitsevent=0x34Total cache hits. Unit: uncore_imc Total cache hitssys_ddr_pmu.write_cyclesddr write-cycles event. Unit: uncore_sys_ddr_pmu uncore_sys_ddr_pmusys_ccn_pmu.read_cycles0x01config=0x2cccn read-cycles event. Unit: uncore_sys_ccn_pmu uncore_sys_ccn_pmu�x�=�K�0D�
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Anon7 - 2021